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Wire Bonding to Advanced Copper-LoK Integrated Circuits, (materials, problems,

and proposed solutions)

• George G. Harman, NIST Fellow-ES• Electronics and Electrical Engineering Laboratory• Semiconductor Electronics Division-812

• National Institute of Standards and TechnologyGaithersburg, MD 20899

• <george.harman@nist.gov>

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Introductory Remarks for WEB Version of Presentation Given at CPMT SVC on Sept 17, 2003

• This presentation is an overview of the Cu, Lo-k bonding problem, using data from many Authors including some of my unpublished work. However, the majority was based on the paper, Wire Bonding to Advanced Copper, Low-k Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations, George Harman and Christian Johnson, published in IEEE Trans. on CPMT, Vol 25, no 4, Dec 2002, pp 677-683, which is posted on this same WEB site. Some material presented in the talk, may have copyright restrictions and has been removed from these slides.

• Remember that this was a verbal presentation, and included explanations not written into the slides.

• George Harman

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Wire Bonding to Advanced Copper-LoK Integrated Circuits

1). The Top Surface Coating for Bondabilitya] Metal(s): Cu, Al/barrier/Cu, Au, Au/barrier/Cu.b] OSPs, SAMs and other thin film

organic/inorganic oxidation inhibitors.

2). The Low Dielectric Constant Materialsa] Mechanical prop’s (usually low modulus).b] Dielectric/barriers/electrical.

3). Under-pad Mechanical Support Structuresa] MCM background/understanding essential.

4). Failure Modes of-and-from Bonding

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Problems in Handling Bare Copper: Sawing of Wafers with Exposed Bare Copper Pads

Requires Developing a Cleaning Process (right)

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Oxidation of Leaky (Thin) Protective Layers Over Copper Pads (SiO2, SiN, etc.)

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Thin (nonuniform) <50Å SiO2 Protective Coating after 5 minutes on a bonder at 150 ºC

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High Temperature Storage of Several Interfaces [after Hong Meng Yo, et. al., IMEC. ASM]

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Detail of a Simple Cu/low-k Materials Stack

Si

Nitride (1kA)

Nitride (1kA)

Nitride (1kA)

Low k (7kA)

Electroplated Cu (15kA)

Cu Seed (1kA)Ta (250A)

Thermal oxide (5500A)

Ta (250A)

Electroplated Cu (Pad) (15kA)

Nitride passivation(1kA)

Cu Seed (1kA)

Courtesy, SEMATECH

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Approaches for Protecting Cu with Thin Non-metal Materials During Bonding

• OSPs-None have Proved useful, at normal bonding temperatures ~ 150ºC (either low bondability or are temperature/environmentally sensitive).

• Thin (<50Å) Inorganic layers, Nitride, Oxides. (several organizations) (Weak, Marginal bonding).

• Ceramic hydride layer formed insitu: (some good results, being evaluated: {K&S, OP2} ).

• A Nanotechnology, Organic, Self-Assembled-Monolayer {SAM}: (Some good results, being evaluated: [IMEC, ASM]. This is an unusual approach, and one that bares watching.[3]

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Issues for Thin Cu-Oxide Protectors

• Top coating over Cu pad < 30-50 Å, Pinhole free!

• Must be hard and brittle, like Al2 O3

• Cu pad; soft like Al (annealed) <100 HV

• Supported by hard Ti/W, or underpad structures

• Will be test probe-mark damaged, then will

oxidize/sulfide—requires film application after testing (post Fab!) or elongated pads.

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How the Bonding Process Breaks Through Thin Surface-Oxide-Films,

Pushes Them Aside, and Forms a Weld

Ball & Pad should be ≈ same hardness

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The Two Basic Schemes for Protecting Copper from Oxidation During Bonding

[after C-C. Lee, et., al., ECTC 2003]

m

n

Al/Ta/Cu

Thin-Inorganic, SAM, or a Bondable Metal/Cu

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Effect of Anneal-induced Recrystallization of an Electrodeposited Cu Film on

Microhardness & UTS [after H. D. Merchant]

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Nanohardness of Several Unannealed/annealed Damascene Cu Films in Ar, and Forming Gas

(Anneal is 290ºC for one hr.) [D. Smith, NIST,-raw data]

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COPPER AS A BONDABLE MATERIAL (with gold balls)

A] Damascene process Cu is harder than Al [Cu nanohardness (~ 2 GPa), but a fused Au ball ~0.4 to 0.5 GPa], Annealing this Cu in Argon drops it to the 1 GPa range, but results are ambiguous/process-dependent.

B] Indentation Modulus ranges around 130 GPa and ~50 GPa for 30 min. @ 300 ºC (Argon) annealed vs 15-40 GPa for Al films).

C] Cu Softens with US energy and temperature. Thin bond pads will “cup” if not supported.

D] Need to understand the copper/gold-diffusion/superlatticesystem resulting from thermal stress tests (up to 400 ºC)!

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Reliability of the Gold-Copper Interface

TemperatureDependence of Time toDecrease Au-Cu bondStrength 40% Below theas-bonded Strength. (The dotted Line ●● is thegeneralized fit to thedata. After Hall, et. al.)

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Au-Cu Phase Diagram (note: no intermetallic compounds, only ductile

super-lattices) [after Hansen]

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Shear Strength of Gold Ball Bonds on Copper Pads after Baking at 175 ºC

[after C-C. Lee, et., al., ECTC 2003]

Bonded Ball Diameter, Approx. 40 µm

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Bonding Over Lo-k, Low-Modulus Dielectrics

(What We learned from Multi-chip Modules)

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Generic, Bond-pad and Polymer of an MCM-D or Cu/LoK Bonding Structure

[Harman, Wire Bonding in Microelectronics, McGraw Hill]

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Cupping of Bond & Pad-Metal Into a Low Modulus Polymer

Pad Peeling

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Rigidized Metal-Pad Structure that will not be Softened or “Cupped” by Ultrasonic Energy

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A SMALL “rigidized” Bond Pad “sinking” into a Soft Polymer, upon Application of Bonding

Force [Harman, Wire Bonding in Microelectronics]

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The Lo-k, Low Modulus, Dielectrics Used/proposed for Incorporation in

Multilayer Copper Metallization, Chip Structures

(note: Lo-k materials usually defined as haveing a dielectric constant < 3)

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Current Problems for Incorporating Low–k Dielectric Materials into Copper Chips (2003)

All companies are having problems incorporating these Lo-kmaterials in their Cu metallization devices. Because of Lo-k integration problems (e.g., adhesion, CTE, fragility), some havetemporarily switched back to Fluorinated Silicate Glasses (dielectric const ~ 3.6-3.8, not much improvement over SiO2)

They all must be CMP compatible. FSGs are CVD (not spin-ons) and process similar to SiO2. Some are working with improved OSGs. Several major houses are in limited production with these. The situation is changing/improving, as solutions are found.

Future problems will increase when porous dielectrics are introduced. Some feel the latter will never be incorporated intoproduction chips.

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Bonding and Fab. Materials Issues of Low Dielectric Constant Materials

• Thermo/Mechanical Propertiesa) Modulus, Fracture Toughness, Cu Diffusion, b) CTE, CTC, Tg/Stability > 400 ºC

• Electricala) Dielectric Constant/Loss, Copper-Drift/Diffusion

• Wafer Fab Issuesa) Manufacturability/Compatibilityb) Diffusion Barrier Compatibilityc) Adhesion, Moisture Uptake

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Wire Bonding Problems Encountered with Low-k, Low Modulus Dielectrics

Under Bond Pads

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Silicon Cracks (below) from Wire Bonding (above) [after Ming Shuoh Liang-TSMC]

G G H-’03Used by Permission of Texas Instruments (L. Stark), Agere Systems (D. Chesire) and International Sematech

via level organic polymer

low-k dielectric

Cu

Cu

Bond

Failure Modes Resulting from Bonding To Pads Over Low-Modulus Materials

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Examples of Bond Pad Peeling over LoK [after Ming Shuoh Liang-TWMC-6th VLSI Packaging WS]

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A Process Window for Bonding to Cu-Lok to Avoid Pad Peeling [after Ming Shuoh Liang-TSMC]

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Cu-LoK/MCM BONDING MACHINE CONSIDERATIONS

A) Use finer diameter wire (e.g., 18 vs 25 µm dia.); if ball bonding, make smaller balls, both are necessary for future fine pitch ( 20 µm). (requires lower force/power).

B) If Al wedge bonding, use softer wire (12-14 vs 16-18 gm BL for 25-µm).

C) May require 10-30% higher bonding machine parameters for same wire if pad sinks.

D) Delay applying ultrasonic energy (~25-50 ms) to allow "sinking" and "cupping" to stabilize after bonding force is applied.

E) Use high frequency ultrasonic energy (>60 kHz).

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Problems in incorporating Copper as Chip Metallization (2003)

• Electromigration of Copper is different with the line length and width! Changes with each downsizing.

• Resistivity changes.• Surface: CMP changes surface and its

properties.• Worse with finer linewidth!

• Properties of Al are simple and predictable (normal, plus some known fixed value).

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The Lo-k Metal-Dielectric Stacks

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Metallurgical Effect of Barriers/Testing on Design for Wire Bonding and Flip Chip

• Copper drift into LoK through cracked barriers requires high Temp/Bias Tests to qualify!

• Tests range from 250-400 ºC for one hr.• (If done after bonding-requires ceramic or >BT

packaging.)• Bond metallurgy must stand this stress!• Au/Al wire bonds are out, if T> 200 ººC.C.• If Au/Cu: complete interdiffusion—OK• If Cu/Cu: requires oxide-free surface.• Barrier Cracking leads to Lifetime Thermal

Stress Failures

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Detail of a Simple Cu/low-k Materials Stack

Si

Nitride (1kA)

Nitride (1kA)

Nitride (1kA)

Low k (7kA)

Electroplated Cu (15kA)

Cu Seed (1kA)Ta (250A)

Thermal oxide (5500A)

Ta (250A)

Electroplated Cu (Pad) (15kA)

Nitride passivation(1kA)

Cu Seed (1kA)

Courtesy SEMATECH

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A Proposed, Complex, Cu-Lo-k Under-pad Structure [courtesy SEMATECH]

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Example of the “Hybrid Structure” (in whichstrong SiO2 Layers Surround Weak Lo-k Layers). This Increases effective Dielectric Constant of Lo-k by ~ 20 %

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The Flip Chip LoK Reliability Problem

• Flip Chips do not have a reliability problem during soldering / reflow.

• Horizontal stress during lifetime temperature-cycling causes:

a) solder fatigueb) delamination of UBMc) delamination of Cu/barrier/LoK

• FC chips cannot be hi-temp stress tested for barrier integrity except at wafer level.

• LoK structures similar to wire bonding are also good for FC.

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Bonding to Copper with Lo-k under the pad ismore difficult than to conventional Al over Si/SiO2. You must use DOE development ofbonding windows to eliminate Pad-Peeling and other under Pad damage. However, you must also know more about the under-pad structures and the materials, as well as the material properties of the dielectrics than you cared to know for wire bonding in the past. An understanding of Materials Science issues will be required for bonding engineers in the future.

Conclusions