wiresandvias - sharif

27
Wires and Vias Somayyeh Koohi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by author

Upload: others

Post on 02-Feb-2022

6 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: WiresandVias - Sharif

Wires and Vias

Somayyeh KoohiDepartment of Computer Engineering

Sharif University of TechnologyAdapted with modifications from lecture notes prepared by

author

Page 2: WiresandVias - Sharif

Topics

� Wire and via structures� Wire parasitics

�Capacitance

Modern VLSI Design: Chap2 2 of 27Sharif University of Technology

�Capacitance�Resistance

� Transistor parasitics

Page 3: WiresandVias - Sharif

Wires and viasmetal 3

metal 2

vias

Modern VLSI Design: Chap2 3 of 27Sharif University of Technology

p-tub

poly poly

n+n+

metal 1vias

Page 4: WiresandVias - Sharif

Metal Layers

� M1thin : narrowest� High density cells

� M2-M4

Modern VLSI Design: Chap2 4 of 27Sharif University of Technology

� For longer wires

� M5-M6: thickest� For VDD, GND, clk

Page 5: WiresandVias - Sharif

Metal migration

� Current-carrying capacity of metal wiredepends on cross-section�Height is fixed (according to metal layer)

Modern VLSI Design: Chap2 5 of 27Sharif University of Technology

�Width determines current limit� Metal migration: when current is too high,

electron flow pushes around metal grains�Higher resistance increases metal migration �

destruction of wire

Page 6: WiresandVias - Sharif

Metal migration problems andsolutions

� Marginal wires will fail after a small operatingperiod: infant mortality

� Solution

Modern VLSI Design: Chap2 6 of 27Sharif University of Technology

�Decrease current density (J=I/A)�Normal wires must be sized to accommodate

maximum current flow�Imax = 1.5 mA/µm of metal width

� Mainly applies to VDD/VSS lines

Page 7: WiresandVias - Sharif

Topics

� Wire and via structures� Wire parasitics

�Capacitance

Modern VLSI Design: Chap2 7 of 27Sharif University of Technology

�Capacitance�Resistance

� Transistor parasitics

Page 8: WiresandVias - Sharif

Diffusion wire capacitance

� Capacitances formed by p-n junctions�Total capacitance: sidewall capacitances + bottomwall

capacitancedepletion regionsidewall

capacitances

Modern VLSI Design: Chap2 8 of 27Sharif University of Technology

n+ (ND)

substrate (NA)bottomwallcapacitance

p

Page 9: WiresandVias - Sharif

Typical 0.5 micron diffusioncapacitance values

� n-type�bottomwall: 0.6 fF/µm2

� sidewall: 0.2 fF/µm

Modern VLSI Design: Chap2 9 of 27Sharif University of Technology

� sidewall: 0.2 fF/µm� p-type

�bottomwall: 0.9 fF/µm2

� sidewall: 0.3 fF/µm� In 0.5 micron process, λ = 0.25 µm

Page 10: WiresandVias - Sharif

Diffusion capacitance example

� Perimeter = 32λ� Area = 52 λ2

� sidewall/bottomwall capacitances = ?

Modern VLSI Design: Chap2 10 of 27Sharif University of Technology

sidewall/bottomwall capacitances ?� total capacitance = ?

12 λ

3 λ 4 λ

Page 11: WiresandVias - Sharif

Depletion region capacitance

� Zero-bias depletion capacitance� Cj0 = εsi/xd

� Depletion region width (zero bias)� x = sqrt[(1/N + 1/N )2ε V /q]

Modern VLSI Design: Chap2 11 of 27Sharif University of Technology

� xd0 = sqrt[(1/NA + 1/ND)2εsiVbi/q]

� Vbi: built-in voltage� Vbi=KT/q ln(NAND/ni

2)

� Junction capacitance is function of voltage across junction� Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

� Vbi � Xd0 � Cj0 � Cj

Page 12: WiresandVias - Sharif

Poly/metal wire capacitance

� Two components�Parallel plate�Fringe

Modern VLSI Design: Chap2 12 of 27Sharif University of Technology

�Fringe

plate

fringe

Page 13: WiresandVias - Sharif

Typical poly/metal capacitance valuesfor 0.5 micron process� poly

� plate: 0.09 fF/µm2

� fringe: 0.04 fF/µm

� metal 2� plate: 0.02 fF/µm2

� fringe: 0.06 fF/µm

Modern VLSI Design: Chap2 13 of 27Sharif University of Technology

� metal 1� plate: 0.04 fF/µm2

� fringe: 0.09 fF/µm

� metal 3� plate: 0.009 fF/µm2

� fringe: 0.02 fF/µm

Page 14: WiresandVias - Sharif

Metal coupling capacitances� Can couple to

� Adjacent wires on same layer� Wires on above/below layers

� Orthogonal wire in different layers

Modern VLSI Design: Chap2 14 of 27Sharif University of Technology

� Orthogonal wire in different layers� Reduction of coupling capacitance

between layersmetal 2

metal 1 metal 1

Page 15: WiresandVias - Sharif

Example: parasitic capacitancemeasurement

� n-diffusion� bottomwall=2 fF� sidewall=2 fF

� metal� l t 0 15 fF

Modern VLSI Design: Chap2 15 of 27Sharif University of Technology

� plate=0.15 fF� fringe=0.72 fF

1.5 µm

3 µm

0.75 µm 1 µm 2.5 µm

Page 16: WiresandVias - Sharif

Wire resistance

� Resistance of any size square is constant� Compute sheet resistance (Rsquare)

� Rtotal = Rsquare* (# of square)

Modern VLSI Design: Chap2 16 of 27Sharif University of Technology

q

Page 17: WiresandVias - Sharif

Typical resistance values for our 0.5micron process� Poly: 4 ohms/square� metali > metali+1 (upper layer metals are thicker)

� metal 1: 0.08 ohms/square

Modern VLSI Design: Chap2 17 of 27Sharif University of Technology

� metal 2: 0.07 ohms/square� metal 3: 0.03 ohms/square

� ndiff: 2 ohms/square� pdiff: 2 ohms/square

Page 18: WiresandVias - Sharif

Calculating resistance

� Determine current flow, then aspect ratio

20

Modern VLSI Design: Chap2 18 of 27Sharif University of Technology

I2

vs.

I2

20

Page 19: WiresandVias - Sharif

Current around corners

� Resistance at corner of two equal-width wires isapproximately 1/2 square� Smaller area

Modern VLSI Design: Chap2 19 of 27Sharif University of Technology

1/2 square

Page 20: WiresandVias - Sharif

Via resistance

� Determined by current flow through via cut� Typical metal1-poly contact: 2.5 ohms� Typical metal1-metal2 contact: 0.5 ohms

Modern VLSI Design: Chap2 20 of 27Sharif University of Technology

Page 21: WiresandVias - Sharif

Topics

� Wire and via structures� Wire parasitics

�Capacitance

Modern VLSI Design: Chap2 21 of 27Sharif University of Technology

�Capacitance�Resistance

� Transistor parasitics

Page 22: WiresandVias - Sharif

Skin effect

� At low frequencies : most of copperconductor’s cross section carries current

� As frequency increases : current moves to skin

Modern VLSI Design: Chap2 22 of 27Sharif University of Technology

� As frequency increases : current moves to skinof conductor�Back EMF induces counter-current in body of

conductor� Skin effect most important at Ghz frequencies

Page 23: WiresandVias - Sharif

Skin effect, cont’d

� Isolated conductor � Conductor and ground:

Modern VLSI Design: Chap2 23 of 27Sharif University of Technology

Low frequency

High frequency

Low frequency

High frequency

Page 24: WiresandVias - Sharif

Skin depth

� Skin depth is depth at which conductor’scurrent is reduced to 1/3 = 37% of surfacevalue

Modern VLSI Design: Chap2 24 of 27Sharif University of Technology

�δ = 1/sqrt(π f µ σ)� f = signal frequency� µ = magnetic permeability� σ = wire conducitvity

Page 25: WiresandVias - Sharif

Effect on resistance

� Low frequency resistance of wire� Rdc = 1/ (σ wt)� W & h : width & height of the semiconductor

Modern VLSI Design: Chap2 25 of 27Sharif University of Technology

� High frequency resistance with skin effect� Rhf = 1/ (2 σ δ (w + t))

� Resistance per unit length� Rac = sqrt(Rdc

2 + κ Rhf2)

� Typically κ = 1.2

Page 26: WiresandVias - Sharif

Transistor gate parasitics

� Gate-source/drain overlap capacitance

t

Modern VLSI Design: Chap2 26 of 27Sharif University of Technology

gate

source drain

overlap

Page 27: WiresandVias - Sharif

Transistor source/drain parasitics

� Source/drain have significant capacitance,resistance�Significant effect on circuit performance

Modern VLSI Design: Chap2 27 of 27Sharif University of Technology

�Significant effect on circuit performance� Measured same way as for wires