work in progress --- not for publication 1 pids 7/11/00 pids itwg meeting pids itwg emerging...

Work in Progress --- Not for Publication

1 PIDS

7/11/00

PIDS ITWG Meeting

PIDS ITWG Emerging Research Devices Working Group Face-to-Face

Meeting

Jim Hutchby - FacilitatingRoom: Mont Blanc 2

Atria Novotel - Grenoble, France8:00 a.m - 4:00 p.m.

April 25, 2001


2 PIDS

7/11/00

PIDS ITWG Novel Devices Working Group Participants

George Bourinaoff Intel/SRC Joop Bruines Philips Joe Brewer U. Florida Jim Chung Compaq Peng Fang AMAT Steve Hillenius Agere Toshiro Hiramoto Tokyo U. Jim HutchbySRC Dae Gwan Kang Hyundai

Makoto Yoshimi Toshiba Kentarou Shibahara Hiroshima U. Kristin De Meyer IMEC Tak Ning IBM Byong Gook Park Seoul N. U. Luan Tran Micron Bin Zhao Conexant Victor Zhirnov SRC/NCSU Ramon Compano Europe Com


3 PIDS

7/11/00

PIDS ITWG Emerging Devices Working Group Working Group Objectives

Prepare a sub-section of the 2001PIDS ITRS Assess advanced non-bulk CMOS-related

technologies Assess potential and issues related to novel

devices and technologies related to: Logic Memory Information Processing Architectures


4 PIDS

7/11/00

PIDS ITWG Emerging Devices Working Group Meeting Objectives & Desired Outcomes

Complete the Emerging Research Devices Tables– Non Bulk CMOS– Research Memory Devices– Logic Devices– Technologies– Architectures

Complete design and layout of the Emerging Technology Sequence Chart

Set Working Group Agenda for completing our section– Emerging Technology Sequence Chart (July ITRS Mtg.)– Text descriptions of Table Entries (July ITRS Mtg.)– Reference text for Table Entries (July ITRS Mtg.)– Completed Emerging Research Devices Section (8/30)


5 PIDS

7/11/00

PIDS ITWG Emerging Devices Working Group Agenda

8:00 Introductions 8:15 Review meeting objectives and agenda Hutchby8:30 Review status of Emerging Research Hutchby

Devices Section Tables (technology entries & row metrics)

– Identify points of consensus– Identify issues not having consensus

Emerging Technology Sequence Chart9:00 Discuss Tables

9:00 Non-Bulk CMOS Table Yoshima 9:45 Memory Table Zhirnov

10:00 Break10:15 Memory Table (continued) Zhirnov11:00 Logic Table Compano

12:00 Lunch 1:00 Technology Table Hutchby

2:00 Architecture Table Bourianoff 3:00 Emerging Technology Sequence Chart Hutchby 4:00 Adjourn Meeting

Model Table for Non-Bulk CMOS Devices PIDS ITWG Emerging Research Devices Working Group

Device

FD SOI High mobility channelbulk/SOI

BOX

Source Drain

Source

Gate

Drain

Si fin - Body! BOX

Source Drain

Source

Gate

Drain

Si fin - Body!

Concept -Fully-depleted SOI -High carrier mobility-Conventional structure

-Double or surround gate-Three-terminal operation

-Double or surround gate-Four-terminal operation

Maturity DevelopmentApplication/ Driver Performance; functional density; power

Advantages -Extension of PD SOI-Performance advantageunclear (scales worst thanbulk )

-Compatible withconventional bulk and SOICMOS

-Higher drive current-Improved subthreshold slope (60 mV/decade at RT) -Stacked NAND

-Higher drive current (in 3-terminal mode only)-Multiple-Vt in four-terminaloperation-Stacked NAND

Challenges: process Thin silicon layer High-mobility materials Complexity ComplexityChallenges: design -Device characteristics

-CADNone -Device characteristics

-PD vs. FD-CAD

-Device characteristics-PD vs. FD-CAD

Timing

Near future Far future


7 PIDS

7/11/00

Emerging Research Memory DevicesPIDS ITWG Emerging Research Devices Sub-Group

Baseline 2001Technologies Magnetic RAM

PhaseChangeMemory

CrestedTunnelBarriers

CoulombBlockadeMemories

MolecularMemory

StorageMechanism

ChargedCapacitor

FloatingGate

Device Types DRAM FlashPseudo-

Spin-Valve

MagneticTunnelJunction

OUM NOVORAM Nanocrystal Quantum dot

Bistable switch Molecular NEMS Spin basedmolecular devices

Availability 2001 > 2003 > 2003 >2003 >2005 >2007 >2010Cell size 8F2 10F2 ~10F2 ~40F2 ~6F2 ~ 6F2 2F2 to 9F2 ~2F2

Access time <20 ns ~80 ns <25 ns <10 ns <100 ns <10 ns <10 ns ~10 nsStore time <20 ns ~1 ms <25 ns <10 ns <100 ns <10 ns <100 ns ~10 nsRetention 64 ms >10 yrs >10 yrs >10 yrs >10 yrs >10 yrs >10 yrs DaysE/W cycles >1E5 >1E15 >1E13 >1E13 >1E6 >1E9 >1E15Maturity production development development concept demonstrated demonstrated

GeneralAdvantages

DensityEconomy

NonvolatileNonvolatile, Fast read & write,Compatible with Si technologies,Rad Hard, NDRO

Nonvolatile,Low Power,NDRORad Hard

Nonvolatile, Fastread & write

Density, Power

Density, PowerIdentical switcheslarge 1/0 difference Opportunities for 3DEasier to interconnectDefect tolerant circuitry

ChallengesReliability, Integration,Material Quality, Control magneticproperties for write operations

New materials& integration

Material QualityDimension control,Background charge

VolatileThermal stability


8 PIDS

7/11/00

Emerging Research Logic Devices1 PIDS ITWG Emerging earch Devices

Working Group

1The time horizon for entries increases from left to right in these tables

Device RTD - FET SET

Rapid SingleQuantumFlux Logic

NanotubeDevices

MolecularDevices

Maturity Demonstrated Demonstrated Demonstrated Concept ConceptAdvantages Density,

Performance,RF

Density High Speed,Potentiallyrobust andscalable

Density,Power

Identity ofindividualswitches (e.g.Size, Properties)on sub-nm level.Potentialsolution tointerconnectproblem

Challenges Logic for twoterminaldevice,Matching ofdevicepropertiesacross wafer

New device &System. Roomtemp operationquestionable.Noise (offsetcharge). Lackof drive current

Very lowtemperaturesrequired,New materialsneeded

New Device& System,No route forfabricatingcomplexcircuitry

Thermal &environmentalstability: twoterminaldevices: needfor newarchitectures


9 PIDS

7/11/00

Model Table for Emerging Technologies1 PIDS ITWG Novel Devices Working Group

1The time horizon for entries increases from left to right in these tables

Technology PlasticTransistors

Nano-Electro-Mechanical

Systems

All OpticsLogic &Storage

DNA & BiologicalComputing

Maturity Development Demonstration Concept ConceptAdvantages Very low cost;

flexible substrate,human scalecomputing

Unique capabilities-sensor/actuators,Very low powerdissipation andsensitivity

Speed,bandwidth,noiseimmunity

Opportunities for parallelcomputing, self assemby,self-repair, re-configuredsystems, ultra high density

Challenges Slow; limitedniche applications

High frequencyoperations; lack ofdesign tools,integration

Scaling,difficultmaterials andmanufacturing

Thermal and environmentalstability, interface toconventional CMOS,


10 PIDS

7/11/00

Emerging Research Architectures PIDS ITWG Emerging Research Devices

Working GroupArchitecture

3-D Integration

Quantum Cellular Automata

Defect

Tolerant architecture

Molecular architecture

Cellular Nonlinear

networks

Quantum Computing

Device Implementation

CMOS with dissimilar material

systems

Quantum Dots Many self assembled

nanodevices

Molecular switches and

memories

Single electron array architectures

Spin resonance transistors, NMR devices

Single flux quantum devices

Pro

Less interconnect delay

Enables mixed technology solutions

High functional density

No interconnects No clock

Supports imperfect hardware

Supports memory

based computing

Enables utilization of single electron devices at room temperature,

memory based computing

Exponential performance scaling, enables unbreakable

cryptography

Con

Heat removal No design tools

Difficult test and measurement

Limited fan out Low temperatures

Requires pre-computing test

Limited functionality

Subject to background noise, tight tolerances

Extreme application limitation, extreme

technology requirements

Maturity Demonstration Demonstration Demonstration Concept Concept Concept

Issues

Asynchronous architecture


11 PIDS

7/11/00

Feature Size:

Technology Progression

Well doping

channelDepletion layer

isolation

halo

Bulk CMOS

PD SOI CMOS

back-gate

channel

isolation

buried oxide

channel

top-gate

Double-Gate CMOS

High mobility (strained Si on SiGe)

High k gate dielectric

Molecular devices

Self-assembly

Metal gate

Nanotube

Wafer bonding & layer transfer

3D, heterogeneous integration

100 nm 15 nm

Time

2 nm

Nanometer-scale CMP

Air bridge

Cu interconnect

Low-k ILD

Technology features (add-on’s)

Mo

lecu

lar

dev

ices

Nan

ote

chn

olo

gy

Contacts to nanodevices

Interconnects for nanodevices


12 PIDS

7/11/00

Critical Size

Emerging Technology Sequence11This chart is intended to guide research. It is not intended to predict future technologies

Well doping

channelDepletion layer

isolation

halo

Bulk CMOS

PD SOI CMOS

back-gate

channel

isolation

buried oxide

channel

top-gate

Double-Gate CMOS

High mobility (strained Si / SiGe)

Hig

h k

gate

diel

ectr

ic

Molecular devices

Sel

f-as

sem

bly

Met

al g

ate

Nanotube

Waf

er b

ondi

ng &

laye

r tr

ansf

er

3D-integration

100 nm 15nm

Nan

omet

er-

scal

e C

MP

Air

bri

dge

Cu

inte

rcon

nect

Low

-k IL

D

Con

tact

s to

nano

devi

ces

Inte

rcon

nect

s

for

nano

devi

ces

2005 2020Year

2nm50nm

2010

CNN & QCA networks

Dev

ices

Arc

hit

ectu

reT

ech

no

log

y


13 PIDS

7/11/00

NDWG IssuesNon Bulk CMOS Devices

Should we have an entry for Fully Depleted SOI or just a single entry for SOI without specifying PD or FD. We are all agreed that we should have some kind of entry for SOI. The question is whether the entry should refer to SOI or to FD-SOI?

Double gate structures. The Japan Region proposes to discuss 1) Vertical MOSFET, 2) DELTA, 3) double-gate MOSFET separately.


14 PIDS

7/11/00

NDWG IssuesEmerging Logic Devices

Novel Logic Devices. Should we refer to this table as the “Emerging Logic Devices Table”? Other tables could be similarly named, e.g., “Emerging Memory Devices Table”, etc.

What position should we take regarding application of the NDWG’s judgement on the various entries? Should we leave any out if we think they are too speculative?

Added Row Metric. The US Group added a new row metric entitled “Maturity”. This metric is proposed to be added to all the tables


15 PIDS

7/11/00

NDWG IssuesEmerging Logic Devices

Given our position on the RTD and its lack of potential, due to its being a 2-terminal device, what position should we take on the newer versions of 2-terminal devices, such as molecular switches, consisting of single molecules operating in a tunneling mode? We all agree that we should have an entry for single molecular devices and for Carbon Nanotubes. Also, the Far East Region view is that we should keep the sub-category for RTD 2-terminal devices. The US Region agrees that we should keep the entry for the RTD 2-terminal device in the RTD-FET section.


16 PIDS

7/11/00

NDWG IssuesEmerging Memory Devices

MRAM. Should we separate the entries for GMR and Tunnel Junction Devices?

MRAM. The title “Pseudo-Spin-Valve Memory” might be substituted for “GMR Memory”.


17 PIDS

7/11/00

NDWG IssuesEmerging Memory Devices

We need more discussion of how best to group these different memory types, and how best to categorize them with descriptive titles. Cell size, access time, retention time, write cycles and power.

Should the “Yano Device” be a separate entry to the Memory Table?

Crested Tunnel Barrier Memory. A concern is this title is specific to Prof. Liharev’s approach. Several other names including Nano Floating Gate have been suggested.

Coulomb Blockade Memory. Concern has been expressed that this title is not descriptive. Another title of “Single Electron Memory” has been suggested.


18 PIDS

7/11/00

NDWG IssuesEmerging Architectures

We need to decide whether and where to put 3-D Heterogeneous Integration? Specifically, do we put the 3-D Heterogeneous Integration in the Emerging Architecture Table? The US Region agrees this should be in the Emerging Architectures Table.

We need to decide whether or not to keep the entries for Defect Tolerant Architecture and Molecular Computing in the Emerging Architecture Table?

work in progress --- not for publication 1 pids 7/11/00 pids itwg meeting pids itwg emerging...

Documents

pids itwg emerging devices

emerging logic devices

emerging memory devices

pids itwg novel devices

emerging technologies

group slide

u kristin

bulk cmos devices ushould