work in progress --- not for publication itrs conference, december 6, 2000 the device copper...

Work in Progress --- Not for Publication

ITRS Conference, December 6, 2000

THE DEVICE

Copper Conductors(8 Levels)

Low-kDielectric

CopperPlugs

1% of the thickness with60% of the issues

100 nm High End MPU & ASIC Device

Updates to the 1999 ITRS, and Previews of International FEP TWG Plans for the 2001 ITRS


Scope of FEP TWG Activities

• Covers starting silicon wafer through contact formation and pre-metal dielectric layer deposition

• Focus has been on requirements for high performance logic transistors & DRAM storage capacitors

• Mission is to define comprehensive needs and potential solutions for the key technology areas in the front-end-of-line (FEOL) wafer fabrication processing of integrated circuits


FEP Roadmap Scope

A: Gate Stack B: Source/Drain - ExtensionC: Isolation D: ChannelE: Wells F: DRAM Capacitor Stack/Trench G: Starting Material H: Contacts I: PMD

CE D

A

B

F

H

G

I


Thrusts & Sub-TWG Organization

• Starting Materials- Tables 32a&b, Figure 17• Surface Preparation-Tables 33a&b, Figure 18• Front End Etch Processes-Tables 34a&B, Figure 21• Transistor Doping-Tables 34a &b, Figure 20• Thermal Processing and Thin Films-Tables 34a &b,

Figure 19• Stack Capacitor- Table 35, Figure 22• Trench Capacitor-Table 36• Device Modeling


Contacts for Commentary & Criticism • Overall & Table 31: Mike Jackson- [email protected]

Walter Class- [email protected]

• Tables 32a & 32b: Howard Huff- [email protected]

David Myers- [email protected]

• Tables 33a & 33b: Scott Becker- [email protected]

Glenn Gale- [email protected]

• Tables 34a &b Etch: Robert Kraft- [email protected]

• Tables 34a &b Doping: Larry Larson- [email protected]

Kevin Jones- [email protected]

• Tables 34a&b Carlton Osburn- [email protected]

Thermal/Films: Howard Huff- [email protected]


Contacts for Commentary & Criticism

• Table 35: Seiichiro Kawamura - [email protected]

• Table 36: Martin Gutsche - [email protected]


THE DEVICE

Copper Conductors(8 Levels)

Low-kDielectric

CopperPlugs

1% of the thickness with60% of the issues

100 nm High End MPU & ASIC Device

2000 Update- Overview of changes


Summary of Major Changes since 1999 • Since publication of the 1999 ITRS device scaling has

occurred more rapidly than forecasted– Several manufacturers are forecasting 130nm node device

manufacture in the year 2001, rather than 2002 as originally forecasted

• The MPU/ASIC technology gap has been eliminated– Leading edge MPU and ASIC gate lengths are now equal

• Recognition of widespread industry practices that yield a physical gate lengths that are smaller than the resist printed feature size

• The DRAM Stack capacitor scaling (cell “a” Factor) is scaling more slowly than forecasted. – DRAM storage cell areas shrink less rapidly than 1999 forecast

• 450mm wafers may be required earlier than originally forecasted


Summary of Changes That Impact FEP


Summary of FEP Year 2000 Updates & 2001 Plans


Starting Materials & Surface Preparation Update & 2001 Plans

Technical Requirments Tables 32a&b and Tables 33a&b


Summary of Actions and Plans for Starting Materials & Surface Preparation

• 1999 ITRS Tables 32a & b, and Tables33a&b have not been updated to reflect the new proposed technology node parameters

• Changes have a very significant effect on bulk and surface defect requirements

• Defect requirements also have a very strong impact on wafer cost and availability

• New tables will be generated when technology node consensus is achieved, and new, validated yield/defect algorithms have been generated


Node Changes Drive New Defect Requirements for Starting Materials and Surface Preparation

New DRAM cell “a”factors and Bit Capacity

New Lithography Field Sizes

New MPU Cache

Requirements

Cost Considerations

New Chip Sizes, “Active Areas”, &Kill

Ratios

Statistics Based Defect-yield Algorithm

New Starting Materials

Metal,COPS, Particle, & SF Requirements

New Surface Prep Particle,

Metal, and Water Mark

RequirementsNew MPU & DRAM 1/2 pitch and gate lengths


Starting Materials and Surface Preparation 2001 Plans

• Update and Validate inputs to the the Defect-Yield Algorithms used to generate defect requirements forecasts– Reverse engineering studies of current manufactured products to

validate• Chip Size

• DRAM, SRAM and Logic transistor densities

• DRAM, SRAM, and Logic active areas

– Develop methodology for forecasting chip size, transistor densities and active areas

– Apply Statistical Yield/Defect equation to new validated parameters to re-forecast future defect requirements.

• Begin discussion on 450mm wafer requirements.


Thermal Thin Films, Gate Etch, and Doping Updates and 2001 Plans

RequirementsTables 34a & b

Potential Solutions Figures 19, 20, & 21


Summary of actions and plans• Tables 34a &b 2000 updated for years 1999, 2000, &

2001 to reflect current transistor gate lengths in production.

• Remaining updates will be made in 2001 upon achievement of consensus regarding new forecasts for ASIC and MPU gate lengths

• New forecasted physical gate lengths will have the effect of bringing “red walls” closer. – 2004 need for high gate dielectric materials– 2004 need for dual metal gates– 2004 need for ultra-shallow highly activated drain extensions


Thermal Films Year 2001IssuesYear of Introduction"Technology Node"

1999180 nm

20002001

130nm2002

2003 2004 90nm2005

DriverMPU/ASIC Gate Length (nm) 120 100 90 85-90 80 70 65 MPU/ASIC

Final Physical Bottom Gate Length after Etch, Proposed (nm) [A2]

100 90 80 80 70 65 60 MPU/ASIC

Equivalent physical Oxide Thickness Tox(nm) (A) 1.9-2.5 1.5-1.9 1.5-1.9 1.5-1.9 1.5-1.9 1.2-1.5 1.0-1.5 MPU/ASIC

Gate Dielectric Leakage @ 100°C (nA/µm) High Performance (B) 7 8 10 10 13 16 20MPU/ASIC

Gate Dielectric Leakage @ 100°C (pA/µm) Low Power (B) 7 8 10 10 13 16 20 MPU/ASIC

• Accelerated MOSFET gate length scaling creates:•Accelerated need for high-k gate dielectric solution

•Accelerated need for dealing with increased MOSFET leakage

•Concurrent ASIC and MPU accelerated solutions

• The achievement of the high-k dual metal gate solution is

unlikely in the 2004 time frame


Transistor Contact & Doping- 2001 IssuesYear of Introduction"Technology Node"

1999180 nm

20002001

130nm2002

2003 2004 90nm2005

DriverMPU/ASIC Gate Length (nm) 120 100 90 85-90 80 70 65 MPU/ASIC

Final Physical Bottom Gate Length after Etch, Proposed (nm) [A2]

100 90 80 80 70 65 60 MPU/ASIC

Active Poly Doping to achieve 10% GOx depletion(M) 2.2x1020 3.1x1020 3.1x1020 3.1x1020 3.1x1020 3.9x1020 4.6x1020 MPU/ASIC

Contact silicide sheet Rs (/sq) (O) 3.3 3.8 4.4 4.4 4.7 5.4 6.0 MPU/ASIC

Contact maximum resistivity (-cm2) (P) < 2.5 x 10-7

< 2.0 x 10-7

< 1.7 x 10-7

<1.7 x 10-7

<1.6 x 10-7

<1.1 x 10-7

<1.0 x 10-7

MPU/ASIC

Maximum Silicon consumption (nm) (Q) 32-60 26-50 22-43 22–43 20-40 18-36 16-33 MPU/ASIC

Contact Xj (nm) (R) 65-125 55-105 45-90 45-90 43-85 38-75 35-70 MPU/ASIC

Drain extension Xj (nm) (S) 36-60 30-50 25-43 25-43 24-40 20-35 20-33 MPU/ASIC

Drain Extension Sheet Resistance (/sq) 310-760 280-730 250-700 250-700 240-675 220-650 200-625 MPU/ASIC

• Accelerated MOSFET Gate Length Scaling Creates:

•Accelerated need for dual metal gate electrodes

•Accelerated need for next generation contact solutions

•Accelerated need for ultra-shallow highly activated extensions

•ASIC and MPU accelerated solutions that are concurrent in time

• Achievement of these solutions by 2004 is questionable


Potential Interim Scaling Solutions

• Scaled MOSFET’s with Ion/Ioff tailored for specific applications– High performance desktop

– Low Operating Power

– Low Standby Power

– Embedded DRAM transfer devices

• Multiple Tailored MOSFET’s on the same chip• Doping strategies to achieve dynamic threshold

voltage adjustment• Design approaches for power management• Expanded use of SOI for low power applications


2001 ITRS Plans for Thermal Films & Doping

• Forecast scaling-driven MOSFET technical requirements and potential solutions for:– Desktop applications

– Low operating power applications

– Low standby power applications

– embedded DRAM transfer devices

• Expand roadmap scope by developing new requirements for pre-metal dielectric layers– Logic devices

– DRAM’s


Proposed New Physical Gate Length IssuesYear of Introduction"Technology Node"

1999180 nm

2000 20012002

130 nm2003 2004

2005100 nm Driver

Was: MPU Gate Length (nm) 140 120 100 85 80 70 65 M Gate

Is: MPU/ASIC Gate Length (nm) 140 120 100 90 80 70 65 MPU/ASIC

New: Proposed Final Physical Bottom Gate Length after Etch (nm)

120 100 90 80 70 65 60 MPU/ASIC

•1999 ITRS assumed post-etch gate length equal to feature size printed in the resist

• Industry practice has been to vary the gate etch process to achieve a physical gate length

after etch that is smaller than the printed feature size

• New proposed reduced post-etch gate length is achieved more complex etching processes

• New etch processes add variance to the final physical gate length

• Two etch processes have been identified that result in a reduced post-etch gate length


Gate Etch Proposed Process AlternativesResist

Polysilicon Gate Material

Silicon

Resist Isotropic Etch

Poly Vertical Etch

Poly Vertical Etch

Poly Isotropic Etch


Year 2001 CD Etch Process Plans

• Collaborate with Lithography TWG to develop a variance budget for Lithography and CD Etch– Proposed budget; Lithography = 2/3 of total allowed variance

CD Etch = 1/3 of total allowed variance

• Generate new CD Etch requirements needed to conform to allowed variance budget


FEP DRAM Update & 2001 Plans


Impact of New DRAM cell “a” Factor

Cell Area Factor “a”

DRAM 1/2 Pitch, “F”

Cell size = aF2

Chip Area Available for 35fF Storage

Capacitor

Stack Capacitor Height, Shape,

Electrode Material, Dielectric value & Layer Thickness

Trench Depth, Trench Capacitor Shape, Electrode

Material, Dielectric value & Layer

Thickness

FEP Table 35

FEP Table 36

DRAM DRAMYear Technology Half- Pitch Half- Pitch for

Node (nm) 2001 ITRS (nm) ITRS '99 ITRS2000 ITRS '99 ITRS20001999 180nm 180 180 8 8 0.26 0.262002 130nm 130 115 6 8 0.1 0.142005 100nm 100 80 4.4 6 0.044 0.062008 70nm 70 60 3.6 6 0.018 0.032011 50nm 50 40 3 4 0.0075 0.012014 35nm 35 30 2.5 4 0.0031 0.005

Cell size (um2)Cell size factora

180 130 100 70 50 35

Technology Node (nm)180 130 100 70 50 35

Technology Node (nm)

0.001

0.01

0.1

1

Cel

l siz

e (u

m2)

Cel

l siz

e fa

ctor

a

0

2

4

6

8

10

DRAM Cell size factor and Cell size

ITRS ‘99

ITRS 2000

ITRS ‘99

ITRS 2000

DRAM DRAMYear Technology Half- Pitch Half- Pitch for

Node (nm) 2001 ITRS (nm) ITRS '99 ITRS2000 ITRS '99 ITRS20001999 180nm 180 180 1 1 400 4002002 130nm 130 115 3 2.6 460 5382005 100nm 100 80 8 6.1 530 5402008 70nm 70 60 24 13.9 630 6002011 50nm 50 40 64 32 710 4642014 35nm 35 30 192 73.5 860 530

DRAM Capacity Chipsize(Introduction Gbit) (Introduction mm2)

180 130 100 70 50 35

Technology Node (nm)180 130 100 70 50 35

Technology Node (nm)

DR

AM

Cap

acit

y (G

bit

)

Ch

ip s

ize

(mm

2)0

200

400

600

800

1000

1

10

100

1000

DRAM Capacity and Die size

ITRS ‘99

ITRS 2000

ITRS ‘99

ITRS 2000

X4/4Years

X4/4Years

X4/5Years

0

100

200

300

400

500

600

700

800

1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016

Chi

p Siz

e (m

m2)

Year 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 Technology Node 180 130 100 70 50 35

F (nm) 180 165 150 130 120 110 100 90 80 70 60 55 50 45 40 35 31 28Cell Area Factor 8 8 8 8 8 8 6 6 6 6 6 6 4 4 4 4 4 4Cell Area (um2) 0.26 0.22 0.18 0.14 0.12 0.10 0.06 0.05 0.04 0.03 0.022 0.018 0.010 0.008 0.006 0.005 0.004 0.003

1G

2G4G 8G 16G 32G 64G

Introduction1chip/Field

256M

2G512M 1G

4G 8G 16G

Production2chips/Field

Year

128G

32G

Calculated DRAM chip size


Summary of year 2000 & 2001 DRAM Issues

• Increased cell “a” factor (2000 update)– results in larger chip area allocation for storage cell

– chip size for a given DRAM capacity is increased

– Storage capacitor scaling requirements less challenging

• Proposed, more aggressive, DRAM 1/2 Pitch scaling (2001 ITRS)– results in smaller chip area allocation for storage cell

– chip size for given DRAM capacity is decreased

– Storage capacitor scaling requirements become more challenging


Memory Year 2000 Update and 2001 Plans

• 2000 Update: Tables 35 & 36 Updated to reflect new DRAM cell area factors– Less aggressive “a” factors increase storage area size

– Impacts future chip sizes and future bits/Chip

– Tables 35 & 36 not updated to reflect new proposed 2001 DRAM 1/2 pitch forecasts

• Year 2001 Plans– Update Tables 35 & 36 to reflect consensus DRAM 1/2 pitch forecasts

– Continue to review DRAM chip size, “a” factor and future bits/chip

• Year 2001 New Memory Projects– Generate New Requirements for Flash Memory (Europe TWG)

– Generate New Requirements for Ferroelectric RAM (Japan TWG)

work in progress --- not for publication itrs conference, december 6, 2000 the device copper...

Documents

ab slide

materials tables

changes slide

itrs slide

new defect requirements

itrs tables

forecasted slide

availability new tables