Workshop on “Digital Circuit Design in FPGA”

Presented By

Mohammed Abdul Kader

Assistant Professor, Dept. of EEE, IIUC

Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com

Session-1

Workshop on "Digital Circuit Design in FPGA Platform",

The field-programmable gate array (FPGA) is a semiconductor device that can be

programmed after manufacturing. Instead of being restricted to any

predetermined hardware function, an FPGA allows you to program product

features and functions, adapt to new standards, and reconfigure hardware

for specific applications even after the product has been installed in the field—hence

the name "field-programmable".

You can use an FPGA to implement any logical function that an application-specific

integrated circuit (ASIC) or, application-specific standard product (ASSP)

could perform, but the ability to update the functionality after shipping offers advantages

for many applications.

What is an FPGA? 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

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Workshop on "Digital Circuit Design in FPGA Platform",

IOB

Input/Output Block.

CLB

Configurable Logic Block.

PSM

Programmable Switch Matrix.

Connection Lines

Clock Circuitry

FPGA Architecture 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

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Workshop on "Digital Circuit Design in FPGA Platform",

Microcontroller:

• Micro-computer in a single chip.

• Configuring a predefined hardware

by programming.

FPGA Vs Microcontroller

FPGA:

• Developing Hardware by

programming

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

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Workshop on "Digital Circuit Design in FPGA Platform",

FPGA Programming

Schematic Entry Hardware Description language

Verilog HDL

RTL Verilog Code

Structural Verilog Code

Behavioral Verilog Code

VHDL

FPGA Programming

5

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

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Workshop on "Digital Circuit Design in FPGA Platform",

Schematic Design in FPGA

X

Y

Z

S = X ⊕ Y ⊕ Z

C = Z(X ⊕ Y) + XY

Steps:

a) Open a new project Wizard.

b) Open a new schematic file.

c) Draw the circuit.

d) Compilation.

e) Pin Planer.

f) Compilation

g) Upload

6

Implementation of Full adder circuit

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Workshop on "Digital Circuit Design in FPGA Platform",

Open a new project Wizard.

7

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Schematic Design in FPGA(Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

Family and Device Settings

8

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Schematic Design in FPGA(Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

Drawing circuit in New Schematic File

9

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Schematic Design in FPGA(Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

Pin Planner

10

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Schematic Design in FPGA(Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

Loading Program

11

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Schematic Design in FPGA(Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Verilog HDL – Structural Verilog Code

12

Workshop on "Digital Circuit Design in FPGA Platform",

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Verilog HDL – Structural Verilog Code

13

Workshop on "Digital Circuit Design in FPGA Platform",

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

Verilog HDL – RTL Verilog Code

14

RTL Verilog Coding of Digital Circuit

Structural Verilog code is not practicable for designing complex circuit. In that case, RTL Verilog code

is used to design digital circuit. RTL Verilog code of a digital design can be written in two ways:

1) Using continuous assignment structures.

2) Using Procedural assignment structures.

Continuous assignment Vs Procedural assignment

• It is named as continuous assignment because the assignments written in this procedure are

evaluated continuously whereas in procedural assignment structure execution of a statement waits

for the clock or other parameter. The expression (in continuous assignment structure) is evaluated

whenever any of the operands changes.

• RTL coding using continuous assignment is usually used to model combinational circuit which is

more complex than can be handled by structural modeling.

• The declaration ‘module’, ‘input’, ‘output’ and ‘endmodule’ are same as they are used in

structural Verilog code. The difference is the keyword ‘assign’ is used to write the continuous

assignment.

Workshop on "Digital Circuit Design in FPGA Platform",

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

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RTL Verilog Code using Continuous Assignment

15

RTL Verilog code using Continuous Assignment to follow the logic equations given

below.

Verilog Code:

Workshop on "Digital Circuit Design in FPGA Platform",

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

RTL Verilog Code using Continuous Assignment

a: Segment designation b: Numerical designation for display

BCD to Seven Segment Decoder by RTL Verilog Coding using Continuous assignment

A BCD to seven-segment decoder is a combinational circuit that accepts a decimal digit in BCD and

generates the appropriate outputs for the selection of segments in a display indicator used for displaying

the decimal digit. The seven output of the decoder (a,b,c,d,e,f,g) select the corresponding segments in

the display as shown in figure a. The numeric designation chosen to represent the decimal digit is shown

in figure b. Design the BCD to seven segment decoder circuit.

16

Workshop on "Digital Circuit Design in FPGA Platform",

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

From truth table we obtained-

a= ∑ (0,2,3,5,6,7,8,9)

b= ∑ (0,1,2,3,4,7,8,9)

c= ∑ (0,1,3,4,5,6,7,8,9)

d= ∑ (0,2,3,5,6,8,9)

e= ∑ (0,2,6,8)

f= ∑ (0,4,5,6,8,9)

g= ∑ (2,3,4,5,6,8,9)

Don’t care conditions,

d= ∑ (10,11,12,13,14,15)

17

RTL Verilog Code using Continuous Assignment (Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

From truth table we obtained-

a= ∑ (0,2,3,5,6,7,8,9) b= ∑ (0,1,2,3,4,7,8,9) c= ∑ (0,1,3,4,5,6,7,8,9) d= ∑ (0,2,3,5,6,8,9)

e= ∑ (0,2,6,8) f= ∑ (0,4,5,6,8,9) g= ∑ (2,3,4,5,6,8,9) Don’t care , d= ∑ (10,11,12,13,14,15)

X X X X

X X

AB

CD

X X X X

X X

AB CD

a= A+C+BD+BD

X X X X

X X

AB CD

b= B +CD+CD c= B +C+D d= A +BD+BC+BCD+CD

X X X X

X X

AB CD

X X X X

X X

AB CD

e= BD+CD

AB CD

X X X X

X X

f= A+CD+BD+BC g= A+BC+BC+BD

AB CD

X X X X

X X

18

RTL Verilog Code using Continuous Assignment (Cont.)

Workshop on "Digital Circuit Design in FPGA Platform",

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

a= A+C+BD+BD

b= B +CD+CD

c= B +C+D

d= A +BD+BC+BCD+CD

f= A+CD+BD+BC

g= A+BC+BC+BD

e= BD+CD

19

RTL Verilog Code using Continuous Assignment (Cont.)

module seven_segment (a,b,c,d,e,f,g,A,B,C,D);

input A,B,C,D;

output a,b,c,d,e,f,g;

assign a=A|C|(~B&~D)|(B&D);

assign b=(~B|(~C&~D)|(C&D));

assign c=B|~C|D;

assign d=A|(~B&~D)|(~B&C)|(B&~C&D)|(C&~D);

assign e=(~B&~D)|(C&~D);

assign f=A|(~C&~D)|(B&~D)|(B&~C);

assign g=A|(~B&C)|(B&~C)|(B&~D);

endmodule

Logic Equations Verilog Code

Workshop on "Digital Circuit Design in FPGA Platform",

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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010

010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010 20

RTL Verilog Code using Continuous Assignment (Cont.)

Verilog code to design 4-bit adder-subtractor circuit using continuous assignment

structure.

Verilog Code: