wp4 m24 deliverables catania, nov. 10 th , 2010

WP4 Meeting 19/04/2023

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WP4 M24 Deliverables

Catania, Nov. 10th, 2010

Architectural to system level: modeling, analysis and design

WP4 Kick-off Meeting 19/04/2023

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Task T4.1: Variability-aware Design• Partners: LETI, UPC

– Task leader: Edith BEIGNE (LETI)

• Definition and development of (self-) adaptive compensation and optimization techniques to cope with increasing PV variations

• Development of new adaptive voltage and frequency scaling (AVFS) techniques which can be exploited either after testing or at run-time


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Task T4.1: Variability-aware Design• LETI will develop a network of distributed on-chip

controllers to optimize the SoC global performance by exploiting the resource monitors designed in WP3– Distributed and interconnected controllers will be used to adjust

locally and dynamically the power supply level, threshold voltages, and operating frequency, while satisfying the global system constraints

• UPC will define and design specific functional blocks for AVFS such as monitors and level shifters to tune the operating frequency and power supply levels and to connect different voltage islands– A test vehicle will be taped out with the designed sensor and

level shifter circuits


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Task T4.2: Variation-tolerant, Robust, Low-noise and Low-EMI Architectures/Micro-architectures

• Partners: TMPO, LETI, ELX, POLI, ST I, TEKL– Task leader: Jordi CORTADELLA (ELX)

• Development and design of advanced macro-blocks for robust and reliable systems

• Development and design of adaptive architectures based on asynchronous and de-synchronization techniques for:– Computational units and memories– On-chip communication schemes based on GALS paradigm

• Synthesis of PV-tolerant asynchronous/de-synchronized functional blocks and architectures for low-EMI design


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• TMPO will design and characterize PV-tolerant, low-noise and low-EMI asynchronous macro-blocks

• LETI will study asynchronous and de-synchronized communication schemes in GALS-type architectures– Quasi-delay-insensitive (QDI) and de-synchronized approaches

will be evaluated in a NoC– Adaptive communication architectures based on globally

asynchronous or de-synchronized communication will be optimized for PV variations

• ELX will develop a complete automatic design flow for the synthesis of asynchronous circuits either from RTL specifications or from a post-placement gate-level netlists


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• POLI will develop a new asynchronous synthesis prototype tool starting from untimed (or partially-timed) SystemC description– New synthesis techniques to improve the performance

and (by using dynamic voltage scaling) reducing power consumption

• ST I will provide the industrial test cases and design flows to validate these novel asynchronous design methodologies

• TEKL will develop the methodology and support for integrating its novel power shaping optimization technology for EMI reduction into existing synchronous mainstream design flows


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Task T4.3: Design of Reliable Systems

• Partners: THL, NMX, ST F, ISD– Task leader: Stratos POLITIS (ISD)

• Design of highly reliable analog, mixed-mode, digital, and NVM systems based on unreliable foundations subject to large PV variations and degradation– New mechanisms to recognize faulty devices and

structures before the overall system collapses will be developed along with procedures to reconfigure the system so that it continues operating, although at a lower frequency, thus allowing a graceful degradation


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Task T4.3: Design of Reliable Systems• THL and ST F will study and develop a parallel architecture for

safety-critical applications compatible with PV variability for robust and time-predictable design– Multi-core architecture will be based on fault detection, isolation, and

communication dynamic reconfiguration– Design of a processing core for a parallel architecture with real-time

and time-predictable capabilities– In particular ST F will extend Spidergon STNoC to cope with the

requirements of the multi-core architecture

• ISD will design highly-reliable analog, mixed-mode, and digital blocks implemented in a moderately reliable CMOS process. Moreover, ISD plans to investigate fault-tolerant routing, as well as fault diagnosis and dynamic reconfiguration schemes

• NMX will design highly-reliable and fault-tolerant NVM systems


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Task T4.4: Design of Regular Architectures and Circuits for High Manufacturability and Yield

• Partners: TMPO, UPC, ST-I, UNBO– Task leader: Roberto CANEGALLO (ST I)

• Design of customizable circuits, macro-blocks, and architectures based on regular structures to improve manufacturability and predictability


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Task T4.4: Design of Regular Architectures and Circuits for High Manufacturability and Yield

• TMPO will design variability-tolerant asynchronous functional blocks using regular structures to evaluate the yield improvement, while satisfying low-noise/low-EMI requirements

• UPC will develop a via-configurable regular transistor array to improve parametric yield, and manufacturability

• ST I will design customizable via-programmable macro-blocks and mask-programmable IPs suitable for a fast and efficient SoC design and mapping on regular transistor arrays

• UNBO will design a customizable architecture for homogeneous multi-threading based on modular elementary computational blocks– The silicon structure for architectural mapping will be the regular

transistor array developed in cooperation with ST I


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Task T4.5: Distributed reconfigurable PV-robust architectures

• Partners: THL, LIRM– Task leader: Philippe Bonnot (THL)

• Programming methods and tools for predictable and PV-robust MPSoC computing architectures will be developed to consider PV variations at the software/system level, since specific formalisms for execution-time management for critical applications embedded into multi-core architectures are required as early as possible in the design cycle


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Task T4.5: Distributed reconfigurable PV-robust architectures

• THL will develop programming methods and tools for predictable processing architectures to take into account PV variations

• LIRM will study self-adaptive mechanisms to allow application task run-time remapping onto a distributed reconfigurable multi-core architecture, maintaining a given functionality with the same level of performance under PV variability– The remapping policy will be based on the information

obtained from on-die monitors


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M24 Deliverables

D4.2.2 TMPO, LETI, TEKL

M24 Reports on PV-tolerant noise and EMI reduction techniques, and on asynchronous and de-synchronized communication scheme benchmarking

D4.2.3 ELX, POLI, ST I

M24 Advanced asynchronous/de-synchronization flow

Delivery of the first de-synchronized design

D4.1.1 LETI, UPC M24 Reports on PV-aware (self-) adaptive compensation and optimization techniques, including on-chip monitors

D4.3.2 THL, NMX M24 High-level and comprehensive models for robust and predictable blocks and architectures, also including NVM design, and robustness assessment report

D4.3.3 ISD M24 Functional and test specs for a validated controller for ADC and PLL componentsFault-tolerant on-chip global communication scheme on a multi-core SoC virtual platform


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M24 Deliverables

D4.4.1 UPC, TMPO

M24 Report on yield prediction tool and regular structures for PV-tolerant asynchronous blocks

D4.4.2 ST I, UNBO

M24 Report on customizable and regular architectures for homogeneous multi-threading and signal processing, and on programming and customization model based on C language extensionsDelivery of a design flow for mapping on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths

D4.5.1 THL, LIRM

M24 Report on programming methods and tools for PV-tolerant, reliable, and predictable MPSoC architectures

CONFIDENTIAL

WP4 Domain Overview per Task and Partner

15MODERN General MeetingsCatania, Nov. 9 & 10, 2010

T4.1 T4.2 T4.3 T4.4 T4.5

Digital IPs/macros UPC, LETI ST I, UNBO

Analog/AMS IPs/macros UPC, LETI ISD

Asynchronous IPs/macros/cells TMPO, LETI TMPO

Regular/configurable IPs/fabrics ST I, UPC

Architectures/Micro-architectures LETI LETI ISD, THL, ST F, NMX ST I, UNBO LIRM

Interconnect schemes and on-chip communication LETI ISD, THL, ST F

CAD algorithms POLI

CAD flows and integration ELX, TMPO, TEKL, POLI ST I

Design methodologies ELX, TMPO ST I, UNBO

Variability LETI, UPC ELX, TMPO, LETI TMPO LIRM (?)

EMC/EMI ELX, TMPO, TEKL, POLI, ST I

Reliability/Fault tolerance ISD, THL, ST F, NMX THL

Manufacturability and yield ST I,UPC, UNBO, TMPO

Reconfigurability ST F, THL, ISD UNBO LIRM, THL

Software and programming methods ST I, UNBO LIRM, THL

CONFIDENTIAL

WP4 Technology Overview per Task and Partner


Technology T4.1 T4.2 T4.3 T4.4 T4.5

90nm w/- eNVM POLI, ST I, TEKL, ELX

65nm UPC TMPO ST F, ISD UPC, ST I, UNBO, TMPO LIRM (?)

45nm LETI (?)

40nm ELX, TMPO ISD ST I, UPC, TMPO32nm LETI LETI THL THLNVM NMX

CONFIDENTIAL

WP4 Cooperations

In T4.1 collaboration between LETI and ST F on technology transfer

In T4.1 cooperation between LETI and UPC on the temperature monitoring activity, and to coordinate the activities of both institutions in MODERN

In T4.1 cooperation between ELX and UPC on voltage variation measurements across chip

In T4.2 cooperation between ELX, POLI, and ST I on the design flow for desynchronization and on EMI reduction techniques

In T4.2 cooperation between TEKL and ST I on the power shaping methodology for EMI reduction and flow definition and integration of TEKL’s tool into ST design flow

In T4.2 cooperation between LETI and TMPO on QDI asynchronous logic implementation


CONFIDENTIAL

WP4 Cooperations

In T4.3 common research activities and cooperation between ISD and THL, and between THL and ST F

In T4.3 cooperation between ST F and UNBO has started on STNoC technology

In T4.4 cooperation between ST I, UPC and TMPO on the evaluation of the impact of regular design

In T4.4 ST I and UNBO are cooperating on a design flow for mapping applications on mask-programmable computational blocks, regular transistor arrays, and via-/metal-programmable datapaths

In T4.5 cooperation between LIRM and LETI on fine-grain power optimization under variability

In T4.5 cooperation between LIRM and ST F on MPSoC fault tolerance


CONFIDENTIAL

WP4 Link w/- Other MODERN’s WPs


WP3

T3.3

WP4

T4.1

T4.2

T4.3

T4.4

T4.5

WP5

T5.2

T5.3

UPC, LETI UPC, LETI

LETI, TMPO

UPC, TMPO, ST I

THL

THL, LIRM

T3.4ST I

ST I

CONFIDENTIAL

Published PapersF. Campi, T. Bjerregaard, M. Stensgaard, and D. Pandini, “Power Shaping Methodology for Supply Noise and EMI Reduction,” Design Automation Conf., Jun. 2010.

I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. VARI, May 2010

C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio,” in Proc. Intl. Symp. on VLSI, Jul. 2010.

C. Jalier, D. Lattard, A. A. Jerraya, G. Sassatelli, P. Benoit, and L, Torres, “Heterogeneous vs. Homogeneous MPSoC Approaches for a Mobile LTE Modem,” in Proc. DATE, Mar. 2010.

J. Altet, D. Gómez, C. Dufis, J. L. González, D. Mateo, X. Aragonés, F. Moll, and A. Rubio, “On Evaluating Temperature as Observable for CMOS Technology Variability,” in Proc. VARI 2010, May 2010.

J. Cortadella, L. Lavagno, D. Amiri, J. Casanova, C. Macián, F. Martorell, J. A. Moya, L. Necchi, D. Sokolov, and E. Tuncer, “Narrowing the Margins with Elastic Clocks,” in Proc. Intl. Conf. on Integrated Circuits Design and Technology, Jun. 2010.

C. Jalier, D. Lattard, G. Sassatelli, P. Benoit, and L. Torres, “Flexible and Distributed Real-Time Control on a 4G Telecom MPSoC,” in Proc. ISCAS, Jun. 2010.

I. Mansouri, C. Jalier, F. Clermidy, P. Benoit, and L. Torres, “Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory,” in Proc. Intl. Symp. on VLSI, Jul. 2010.

I. Mansouri, F. Clermidy, P. Benoit, and L. Torres, “A Run-time Distributed Cooperative Approach to Optimize Power Consumption in MPSoCs,”, in Proc. Intl. SOC Conf., Sep. 2010.

N. Hebert, P. Benoit, G. Sassatelli, and L. Torres, ‘’D-Scale: A Scalable System-level Dependable Method for MPSoCs,’’ in Proc. Asian Test Symposium, Dec. 2010.

M. Pons, F. Moll, A. Rubio, J. Abella, X. vera, and A. González, “VCTA: A Via-Configurable Transistor Array Regular Fabric”, VLSI-SOC 2010.

N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, “Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” in Proc. VARI, May 2010.

N. Andrikos, L. Lavagno, F. Campi, and D. Pandini, "Improving EMI of Embedded Systems Through Jittered-Delay Desynchronization,” JOLPE, vol. 6, n. 4, Dec. 2010.


CONFIDENTIAL

WP4 Summary

Four WP4 meetings to prepare M24 deliverables– F2f meetings ELX/UPC on July 12th and 19th and on October 5th, 2010.– Web meeting Sep. 17th

– F2f meeting ST Catania Nov. 9th

Demonstrators– System MPSoC platform, with task migration, failure analysis, power

optimization considering variability effects, and HW implementation of several blocks to propose online optimization – LIRM T4.5

All M24 deliverables are on track– No major criticality detected/reported by task leaders and partners


wp4 m24 deliverables catania, nov. 10 th , 2010

Documents

emi reduction

system level

optimization techniques

complete automatic design

pv variations elx

desynchronization techniques

tolerant asynchronousde

level shifters