VHDL 360©

by: Mohamed Samy Samer El-Saadany

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VHDL 360 © 2

Objective

• Modeling more complicated logic using sequential statements

• Skills gained:– Model simple sequential logic using loops– Control the process execution using wait

statements

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Sequential Statements

• Sequential Statements– Case statement – If statement– loop statements

• While Loop • For Loop

– Wait statement

Think Hardware

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While-Loop

<Loop_Label> While <condition> loop -- list of sequential statements

end loop;

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A: (7 DOWNTO 0), count: integer range 0 to 8;

PROCESS (A) IS VARIABLE tempCount, iteration: integer range 0 to 8; BEGIN

iteration := 0; tempCount := 0; my_loop: WHILE (iteration <= 7) LOOPif A(iteration) = '1' then

tempCount := tempCount + 1; end if; iteration := iteration + 1; END LOOP;

Count <= tempCount; END PROCESS;

Example 1: count number of ONES in vector A

Syntax:• Keep looping while <condition> is true– <Loop_Label> optional label to identify the loop– <condition> Boolean expression that evaluates to

either TRUE or FALSE

Skills Check

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While count < 10 loopcount <= count + 1;

End loop;

After the loop finishes what will be the value of “count” signal?

• This is an infinite loop since “count” is a signal which will only update its value when the process suspends

• To fix this :– “count” must be a variable

Skills Check (Soln.)

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While count < 10 loopcount := count + 1;

End loop;

Golden rules of thumb– Variables are updated immediately– Signals are updated after the process suspends

Or

– the process should be suspended inside the while loop using a wait statement

While count < 10 loopcount <= count + 1; <wait statement> -- more on “Wait” later

End loop;

Sequential Statements

• Sequential Statements– Case statement – If statement– loop statements

• While Loop • For Loop

– Wait statement

Think Hardware

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For-Loop

<Loop_Label> for <idenifier> in <range> loop -- list of sequential statements

end loop;

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Example 2: Anding A with each bit in the vector B_bus

Syntax:• For-loop– <Loop_Label> optional label to identify the loop– <identifier> loop iterator that can only be read inside

the loop and is not available outside it – <Range> loop range and can be one of the following <integer> to <integer> <integer> downto <integer>

SIGNAL A: std_logic;SIGNAL B_bus, C_bus: std_logic_vector(7 downto 0); …

process ( A, B_bus ) begin

for i in 7 downto 0 loop C_bus(i) <= A and B_bus(i);

end loop; End process;

For-Loop

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Example 3: 8-bit shift registerLibrary ieee;Use ieee.std_logic_1164.all;entity shift_register is

Port (clk, D, enable : in STD_LOGIC; Q : out STD_LOGIC);

end entity;architecture Behavioral of shift_register is

signal reg: std_logic_vector(7 downto 0); begin process(clk) begin

if rising_edge(clk) then if enable = '1' then

reg(7) <= d; for i in 7 downto 1 loop

reg(i-1) <= reg(i); end loop;

end if; end if;

end process; Q <= reg(0); end Behavioral;

Exercise 1 • The following diagram and flow chart show a “Serial In

Parallel Out” register’s interface and describe how it behaves.

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Exercise 1• To complete the “Serial In Parallel Out” we need to do the following:

– Add necessary assignments to the reset condition– Add a for loop to shift each bit of the internal register “reg” to the right– Decide the condition by which the 8 queued values goes outside the register

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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity serialinparallelout is port(clk : in std_logic; d : in std_logic; rst : in std_logic; enable : in std_logic; ready : out std_logic; q : out std_logic_vector (7 downto 0) ); end serialinparallelout;

Exercise 1architecture behave of serialinparallelout is signal count: std_logic_vector(2 downto 0); begin process(clk) variable reg: std_logic_vector(7 downto 0); begin if rising_edge(clk) then if rst = '1' then Q <= X"00"; -- hexadecimal format

<Here> else Ready <= '0'; if enable = '1' then

< Add the loop Here> reg(7) := d; count <= count+1;

…

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Exercise 1 … if count = ?? then Q <= reg; count <= "000"; Ready <= '1'; end if; end if; end if; end if; end process; end behave;

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Sequential Statements

• Sequential Statements– Case statement – If statement– loop statements

• While Loop • For Loop

– Wait statement

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Wait Statement

wait [ sensitivity clause ] [ condition clause ] [timeout clause] ;

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Syntax:• Process’ sensitivity list is only one means for controlling when a process is executed. Process execution can also be controlled with one or more wait statements– The wait statement causes suspension of a

process• Sensitivity clause, condition clause and

timeout clause can optionally coexist in the same wait statement– sensitivity_clause: on signal_name– Condition clause: until condition– timeout_clause: for time_expression

Example 4:wait; -- suspends process foreverwait on clock; -- suspends process execution until an event occurs on clock wait for 10 ns; -- suspends process execution for 10 ns wait until A < B and enable = '1'; -- suspends process until the condition is truewait until A = '0' for 2 ns; -- after A equals 0 wait 2 ns then resume execution of process

Wait StatementExample 5: Counter generator 1

Architecture waveform of testbench is signal z : std_logic_vector(2 downto 0);

Begin process -- no sensitivity list begin for i in 0 to 7 loop z <= conv_std_logic_vector(i, 3); -- converts integer to std_logic_vector wait for 20 ns; end loop; wait; End process; End architecture;

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Skills Check

Architecture waveform of testbench is signal z : std_logic_vector(2 downto 0);

Begin process begin for i in 0 to 7 loop z <= conv_std_logic_vector(i, 3); wait for 20 ns; end loop; -- wait; End process; End architecture;

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What will happen if we remove this “wait”?

Skills Check (Soln.)Architecture waveform of testbench is

signal z : std_logic_vector(2 downto 0); Begin process begin for i in 0 to 7 loop z <= conv_std_logic_vector(i, 3); wait for 20 ns; end loop; -- wait; End process; End architecture;

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The waveform will not stop when Z reaches “111”, Z will start over again from “000”

Skills Check

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Architecture behave1 of clk_gen is -- signal declaration signal clk_int : std_logic;Begin process begin clk_int <= '1'; wait for 20 ns; clk_int <= '0'; wait for 20 ns; end process; End architecture;

Architecture behave2 of clk_gen is -- signal declaration signal clk_int : std_logic;Begin process begin clk_int <= not clk_int; wait for 20 ns; end process;End architecture;

Catch

me If

you can!

• Spot any problems in the below code• After fixing the problems, draw the waveforms• When do you think one of them can’t be used for clock generation?

Skills Check (Soln.)

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Architecture behave1 of clk_gen is -- signal declaration signal clk_int : std_logic;Begin process begin clk_int <= '1'; wait for 20 ns; clk_int <= '0'; wait for 20 ns; end process; End architecture;

Architecture behave2 of clk_gen is -- signal declaration signal clk_int : std_logic := ‘0';Begin process begin clk_int <= not clk_int; wait for 20 ns; end process;End architecture;

• Initialization is a must in architecture “behave2”• Architecture “behave2” can’t generate a clock with duty cycle other than 50%

Wait Statement• Signals in the sensitivity list form an implied wait condition

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Process 1 Process 2 Process 3

process (A, B) begin C <= A + B;end process;

process begin C <= A + B; Wait on A, B;end process;

process begin Wait on A, B; C <= A + B; end process;

• Both Process 1 & Process 2 yield exactly the same simulation results• Process 3 differs only at initialization time…afterwards the simulation results

will be similar to Process 1 & Process 2

Skills Check

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process (A, B) begin C <= A and B; C <= '1'; end process;

process begin C <= A and B; Wait on A, B; C <= 1; Wait on A, B;end process;

• Are these equivalent in Simulation?

Skills Check (Soln.)

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process (A, B) begin C <= A and B; C <= '1'; end process;

process begin C <= A and B; Wait on A, B; C <= 1; Wait on A, B;end process;

• Are these equivalent in Simulation?

They are not equivalent

Conversion Functions

conv_integer (std_logic_vector);

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Syntax:conv_integer()– Converts a std_logic_vector type to an integer;– Requires:

• library ieee;• use ieee.std_logic_unsigned.all;Or• use ieee.std_logic_signed.all;

Example 6:

library ieee; use ieee.std_logic_unsigned.all;

signal tour: std_logic_vector(3 downto 0); signal n: integer;

n <= conv_integer(tour);

Reference page

Conversion Functions

conv_std_logic_vector (integer, number_of_bits)

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Syntax:conv_std_logic_vector()

– Converts an integer type to a std_logic_vector type – Requires:

• library ieee;• use ieee.std_logic_arith.ALL;

Example 7:

library ieee; use ieee.std_logic_arith.all;

signal tour: std_logic_vector(3 downto 0); signal n: integer;

tour <= conv_std_logic_vector(n, 4);

Reference page

SHARPEN YOUR SAW

Lab work• Write the code for a Fibonacci sequence

generator: Output is the sum of the two previous outputs (0,1,1,2,3,5,8,13,…)

Port names & types must be:

Clk, rst: std_logic

Fib_out : integer

Don’t use inout ports

rst: synchronous reset

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Knight Rider LEDs

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• Write the code for a knight rider circuit: The shining led moves from left to right then from right to left…etc

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Port names & types must be:

Clk, rst, enable: std_logic

knight: std_logic_vector(7 downto 0)

Don’t use inout ports

rst: synchronous reset

Contacts

• You can contact us at:– http://www.embedded-tips.blogspot.com/

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