xilinx confidential. design axi master page 1. xilinx confidential. understanding zynq axi master ip...
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XILINX CONFIDENTIAL.
Design AXI Master
Page 1
XILINX CONFIDENTIAL.
© Copyright 2012 Xilinx
Understanding Zynq AXI Master
IP axi_user_npi
Page 2
Agenda
XILINX CONFIDENTIAL.
© Copyright 2012 Xilinx
AXI is Part of AMBA: Advanced
Microcontroller
Page 3
What is AXI?
Variations of AXI
XILINX CONFIDENTIAL.
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AXI4– Memory mapped
Page 4
Variations of AXI
AXI4-Lite: – Register mapped
AXI4-Stream: – Streaming
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Why Xilinx Choose AXI?
Page 5
ExternalMemoryExternalMemory
TimerTimer SRAMSRAM UARTUARTGPIOGPIO
Microblaze
BRAM LMB
MPMC
PLBv46
Video
TEMAC
Custom IP
VFBC
Local Link
NPI
PLB to IPIF Bridge
PLB to IPIF Bridge Custom IPCustom IP
IPIF
Xilinx Cache Link
Hardware Accelerator
FSL
1
2
3
4
56
7
8
TOO COMPLEX….
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Why Xilinx Choose AXI?
Page 6
ExternalMemoryExternalMemory
TimerTimer SRAMSRAM UARTUARTGPIOGPIO
Microblaze
BRAM LMB
MPMC
AXI
Video
TEMAC
Custom IP
AXI
AXI
AXI
AXI to IPIF Bridge
AXI to IPIF Bridge Custom IPCustom IP
IPIF
AXI
Hardware Accelerator
AXI
1
2
2
2
22
2
3
Too Simple ….
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Channel– Read address
– Write address
– Read data
– Write data
– Write response
Page 7
AXI Protocol, Channel
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AXI Protocol, AXI4
Single address multiple data– Burst up to 256 data beats
Data width parameterizable– 32, 64, 128, 256
AXI4 READ
AXI4 WriteBest for memory access
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AXI Protocol, AXI4_LITE
Single address Single data– No Burst
Data width– 32
AXI4-Lite Read
AXI4-Lite Write
Best for register access
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AXI Protocol, AXI4_STREAM
No address channel
Not read and write, always just master to slave
Unlimited burst length
Best for video, audio
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ZYNQ
High Performance Port
General Performance Port
AXI Master
AXI Slave
Master
MasterSlave
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How to Design AXI Master
CIP
Select AXI type
Select Master
XILINX CONFIDENTIAL.
Page 13
How to Design AXI Master, example
MPD– Default parameter
PAO– Order for synthesis
TEST_IP.VHD– Top level
USER_LOGIC.VHD– User logic
XILINX CONFIDENTIAL.
Page 14
How to Design AXI Master
User_logic.vhd– Control
Burst Transaction
XILINX CONFIDENTIAL.
Page 15
Why Design AXI Master
To access DDRx Memory
Why don’t you use BRAM?
Because BRAM is EASY
But BRAM is TOO SMALL
DDRx is LARGE
But DDRx is not EASY
DDRx max 1GB
Zynq Bram 220KB ~ 2180KB
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FIFO Instead of IPIC
DDRxIPIC & State
Machine
Remove Complexity
FIFOUserLogicRemove complexity…
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Master IP with FIFO, axi_user_npi
IP catalog
Bus
Port
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Master IP with FIFO, axi_user_npi
User logic interface
– Simple
– It is FIFO
component system is port (
... wr_fifo_wr_en : in std_logic; wr_fifo_clk : in std_logic; npi_wr_ready : out std_logic; rd_fifo_rd_en : in std_logic; npi_rd_ready : out std_logic; wr_fifo_data : in std_logic_vector(31 downto 0); rd_fifo_clk : in std_logic; rd_fifo_full : out std_logic; rd_fifo_data : out std_logic_vector(31 downto 0); rd_fifo_empty : out std_logic; wr_fifo_full : out std_logic; wr_fifo_empty : out std_logic ); end component;
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Master IP with FIFO, axi_user_npi
How to Run?
– Device Driver
Read– Start add– Read Burst Cnt– Repeat Cnt
Write– Start add– Read Burst Cnt– Repeat Cnt
void npi_stop(){}
void npi_start(){}
void axi_npi_rd(int reg, int src, int cnt_burst, int cnt_repeat){}
void axi_npi_wr(int reg, int src, int cnt_burst, int cnt_repeat){}
void axi_npi_reset0(){}
int npi_status(int reg){}
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Simulation Result
Burst Write
Burst Read
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Q&A