xlinx - vlsi practical lab manual

PRACTICAL 1

AIM : Introduction to Xlinx 9.2i Project Navigator.

Open Xlinx 9.2i Project Navigator. The above screen will appear.

Goto File New Project. Enter the project name and specify its location. Top level source type should be HDL. Click Next.

The above dialog box appears. The following should be the settings:Product Category - AllFamily - Spartan3Device - XC3S400Package - PQ208Speed - -5 or -4

Click Next.

The above dialog box appears. Click on New Source button.

Select VHDL Module, Enter the name of the file and click Next.

Mention the input and output pins. Click Next.

Click Finish.

Click Next. Again click Next for the next two dialog boxes and at last click Finish.

The above screen will appear. The right hand side window is your code window.

On the left top corner there is a Source Window and below it there is Processes Window.

Type your code as shown in the figure and SAVE it.

Go to Processes window Synthesize – XST Check Syntax.

Right click in the sources window and select New Source. Select Test Bench Waveform, enter the file name and click Next. Again click Next and then Finish.

Select Combinatorial option in Clock Information for input waveform. Select Single Clock for system clock.

Give the necessary waveform of x and SAVE the file. In the Sources Window Select Behavioral Simulation and select the .tbw file. In the Processes window go to Xilinx ISE Simulator Simulate Behavioral

Model.

The above output waveform will appear of y.

Go to Processes Window User Constraints Assign Package Pins. Enter the pins numbers for input and output pins. SAVE the file Click OK Close the file.

Now in Processes window select Synthesize – XST.

After synthesizing process gets over click on Implement Design.

Now after the Implement design gets completed go to Generate File Generation Report Programming File Generation Report.

Go to Generating Programming File Configure Device Click Finish.

Select the .bit file name. Click Open.

Right click on the device and select Get Device from the drop down menu.

The Device Id will appear on the screen.

Again right click on the device and click on Program from the drop down menu.

The above dialog box will appear on the screen. Make sure that the Verify option is disabled. Click OK and the device will be programmed.

PRACTICAL: 2

AIM: Implementation of Logic Gates and its Testing

CODE: Entity dm is

Port (A: in STD_LOGIC; B: in STD_LOGIC;

S: out STD_LOGIC; T: out STD_LOGIC; U: out STD_LOGIC;

V: out STD_LOGIC; W: out STD_LOGIC;

X: out STD_LOGIC; Y: out STD_LOGIC;

Z: out STD_LOGIC);End dm;Architecture Behavioral of dm isBegin

S<=A AND B;T<=A NAND B;U<=A OR B;V<=A NOR B;W<= NOT A;X<= A XOR B;Y<= A XNOR B;Z<= A;

End Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented all the logic gates in Xilinx 9.2i Project Navigator and also observed the simulation graph of all the gates.

PRACTICAL: 3

AIM: Implementation of Full Adder circuit and its Testing.

CODE:

Entity LO is Port (A: in STD_LOGIC;

B: in STD_LOGIC; Cin: in STD_LOGIC;

SUM: out STD_LOGIC; Cout: out STD_LOGIC);

End LO;

Architecture Behavioral of LO isBegin

SUM<= A XOR B XOR Cin;Cout<= (A AND B) OR (B AND Cin) OR (A AND Cin);

End Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the Full Adder circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL: 4(a)

AIM: Implementation of 4:1 Multiplexer and its Testing.

CODE:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX4_1 isPort ( a : in STD_LOGIC;

b : in STD_LOGIC; c : in STD_LOGIC;

d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC);end MUX4_1;

architecture Behavioral of MUX4_1 isbegin

WITH sel SELECTy <= a when "00",

b when "01",c when "10",d when OTHERS;

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the 4 : 1 MULTIPLEXER circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL: 4(b)

AIM: Implementation of 1:4 Demultiplexer and its Testing.

CODE:


entity demx1_4 is Port ( i : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0));end demx1_4;

architecture Behavioral of demx1_4 isbegin

y(0) <= i and (not sel(1)) and (not sel(0));y(1) <= i and (sel(1)) and (not sel(0));y(2) <= i and (not sel(1)) and (sel(0));y(3) <= i and (sel(1)) and (sel(0));

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the 1 : 4 DEMULTIPLEXER circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL: 5(a)

AIM: Implementation of 4:2 ENCODER and its Testing.

CODE:

library IEEE;entity encoder4_2 is

Port ( en : in STD_LOGIC; i : in STD_LOGIC_VECTOR (3 downto 0);

x : out STD_LOGIC_VECTOR (1 downto 0));end encoder4_2;

architecture Behavioral of encoder4_2 isbegin

P1 : process (en,i(0),i(1),i(2),i(3))begin

if (en = '1') thenif (i = "0001") then

x <= "00";elsif (i = "0010") then

x <= "01";elsif (i = "0100") then

x <= "10";elsif (i = "1000") then

x <= "11";else

x <= "ZZ";end if;

elsex <= "00";

end if;end process P1;

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the 4 : 2 ENCODER circuit in

Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL: 5(b)

AIM: Implementation of 2:4 DECODER and its Testing.

CODE:

library IEEE;entity decoder2_4 is

Port ( en : in STD_LOGIC; i : in STD_LOGIC_VECTOR (1 downto 0);

x : out STD_LOGIC_VECTOR (3 downto 0));end decoder2_4;

architecture Behavioral of decoder2_4 isbegin

P1 : process (en,i(0),i(1))begin

if (en = '1') thenif (i = "00") then

x <= "0001";elsif (i = "01") then

x <= "0010";elsif (i = "10") then

x <= "0100";elsif (i = "11") then

x <= "1000";else

x <= "ZZZZ";end if;

elsex <= "0000";

end if;end process P1;

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the 2 : 4 DECODER circuit in

Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 6

AIM : To design and implement 4-bit Ripple Carry Adder.


entity FA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; Cin : in STD_LOGIC; sum : out STD_LOGIC; Cout : out STD_LOGIC);end FA;

architecture Behavioral of FA is

beginsum <= (a Xor b) Xor Cin;Cout <= (a and b) or (b and Cin) or (a and Cin);

end Behavioral;


entity RCA is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); Cin : in STD_LOGIC; sum : out STD_LOGIC_VECTOR (3 downto 0); Cout : out STD_LOGIC);end RCA;

architecture Behavioral of RCA iscomponent FA

port( a, b, Cin : in std_logic; sum, Cout : out std_logic );

end component;

signal c : std_logic_vector(2 downto 0); begin

FA1 : FA port map( a(0) , b(0) , Cin , sum(0) , c(0) );FA2 : FA port map( a(1) , b(1) , c(0) , sum(1) , c(1) ); FA3 : FA port map( a(2) , b(2) , c(1) , sum(2) , c(2) ); FA4 : FA port map(a (3) , b(3) , c(2) , sum(3) , Cout);

end;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the 4-bit RIPPLE CARRY ADDER circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 7(a)

AIM : To design and implement Edge Triggered JK Flip Flop.


entity JK_FF_EDGE is Port ( CLK : in STD_LOGIC; J : in STD_LOGIC; K : in STD_LOGIC; RST : in STD_LOGIC; Q : inout STD_LOGIC; Qbar : inout STD_LOGIC);end JK_FF_EDGE;

architecture Behavioral of JK_FF_EDGE isbegin

P1 : process (CLK, J, K)begin

if (RST = '1') thenQ <= '0';Qbar <= '1';

elsif (CLK = '1' AND CLK 'EVENT) thenif (J = '0' AND K='0') then

Q <= Q;Qbar <= Qbar;

elsif (J = '0' AND K='1') thenQ <= '0';Qbar <= '1';

elsif (J = '1' AND K='0') thenQ <= '1';Qbar <= '0';

elsif (J = '1' AND K='1') thenQ <= not Q;Qbar <= not Qbar;

else Q <= 'Z';Qbar <= 'Z';

end if;

elseQ <= Q;

Qbar <= Qbar;end if;end process P1;end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the JK Flip Flop circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 7(b)

AIM : To design and implement Edge Triggered D Flip Flop.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity D_FF is Port ( CLK : in STD_LOGIC; D : in STD_LOGIC; RST : in STD_LOGIC; Q : inout STD_LOGIC; Qbar : inout STD_LOGIC);end D_FF;

architecture Behavioral of D_FF isbeginP1 : process (CLK, D)begin

if (RST = '1') thenQ <= '0'; Qbar <= '1';

elsif (CLK = '1' AND CLK 'EVENT) thenif (D = '0') then

Q <= '0'; Qbar <= '1';elsif (D = '1') then

Q <= '1'; Qbar <= '0';else

Q <= 'Z'; Qbar <= 'Z';end if;

elseQ <= Q; Qbar <= Qbar;

end if;end process P1;end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the D Flip Flop circuit in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 8

AIM : To design and implement Synchronous Counter with Asynchronous Reset.


entity andgate is Port ( a : in STD_LOGIC;

b : in STD_LOGIC; y : out STD_LOGIC);

end andgate; AND BLOCK

architecture Behavioral of andgate isbegin

y<= a and b;

end Behavioral;

entity tff2 is Port ( clk : in std_logic; rst : in std_logic; t : in std_logic; q : inout std_logic; qbar : inout std_logic);end tff2;

architecture Behavioral of tff2 isbeginprocess (clk,rst,t)begin

if(rst='1')thenq<='0';qbar<='1';

elsif(clk='1' and clk'event)thenif(t='0')then

q<=q;qbar<=qbar;

elseq<=not(q);qbar<=not(qbar);

end if;else

q<=q;qbar<=qbar;

end if;end process;end Behavioral;

T-FF BLOCK

entity syncount is Port ( clk : in std_logic; rst : in std_logic; dout : inout std_logic_vector(3 downto 0));end syncount;

architecture structural of syncount iscomponent tff2 Port ( clk : in std_logic; rst : in std_logic; t : in std_logic; q : inout std_logic;

qbar : inout std_logic);end component;component andgate

Port ( a : in std_logic; b : in std_logic; y : out std_logic);

end component;

signal x1,x2:std_logic;signal xdum:std_logic:='1';signal x3,x4,x5,x6:std_logic:='Z';begin

t1:tff2 port map(clk,rst,xdum,dout(0),x3); t2:tff2 port map (clk,rst,dout(0),dout(1),x4); a1:andgate port map(dout(0),dout(1),x1); t3:tff2 port map(clk,rst,x1,dout(2),x5); a2:andgate port map(x1,dout(2),x2); t4:tff2 port map(clk,rst,x2,dout(3),x6);

end structural;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented the Synchronous Counter in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

SYNC COUNTER BLOCK

PRACTICAL : 9(a)

AIM : To design and implement a 3-bit SISO register.


entity dff is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; q : inout STD_LOGIC);end dff;

architecture Behavioral of dff is

beginP1:process(rst,clk,d)beginif(rst='1') then

q<='0';

elsif(clk='1' and clk' event) thenif(d='0') then

q<='0';elsif(d='1') then

q<='1';else

q<='Z';end if;

elseq<=q;


entity siso is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; Din : in STD_LOGIC; q : inout STD_LOGIC);end siso;

architecture Behavioral of siso iscomponent dff Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; q : inout STD_LOGIC);end component;

D-FF BLOCK

signal t: std_logic_vector(2 downto 0);

begin

FF1: dff port map(rst,clk,Din,t(2));FF2: dff port map(rst,clk,t(2),t(1));FF3: dff port map(rst,clk,t(1),t(0));FF4: dff port map(rst,clk,t(0),q);

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented a 3-bit SISO register in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 9(b)

AIM : To design and implement a 3-bit SIPO register.


entity dff is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; q : inout STD_LOGIC);end dff;

architecture Behavioral of dff is

beginP1:process(rst,clk,d)beginif(rst='1') then

q<='0';

elsif(clk='1' and clk' event) thenif(d='0') then

q<='0';elsif(d='1') then

q<='1';else

q<='Z';end if;

elseq<=q;


entity sipo is Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; Din : in STD_LOGIC; q : inout STD_LOGIC_VECTOR(3 downto 0));end sipo;

architecture Behavioral of sipo iscomponent dff Port ( rst : in STD_LOGIC; clk : in STD_LOGIC; d : in STD_LOGIC; q : inout STD_LOGIC);end component;

D-FF BLOCK

signal t: std_logic_vector(2 downto 0);

begin

FF1: dff port map(rst,clk,Din,q(3));FF2: dff port map(rst,clk,q(3),q(2));FF3: dff port map(rst,clk,q(2),q(1));FF4: dff port map(rst,clk,q(1),q(0));

end Behavioral;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented a 3-bit SIPO register in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

PRACTICAL : 10

AIM : To design and implement an 8-bit ALU.


entity ALU is Port ( A : in std_logic_vector(7 downto 0); B : in std_logic_vector(7 downto 0); Cin : in std_logic;

SEL : IN STD_LOGIC_VECTOR(3 DOWNTO 0); Y : out std_logic_vector(7 downto 0));end ALU;

architecture ARCHALU of ALU isSIGNAL ARITH,LOGIC: STD_LOGIC_VECTOR (7 DOWNTO 0);BeginWITH SEL(2 DOWNTO 0) SELECT

ARITH<= A WHEN "000", A + 1 WHEN "001", A - 1 WHEN "010",

B WHEN "011",B + 1 WHEN "100",B - 1 WHEN "101",

A + B WHEN "110",A+B+CIN WHEN OTHERS;

WITH SEL(2 DOWNTO 0) SELECT LOGIC<= (NOT A) WHEN "000",

(NOT B) WHEN "001", (A AND B) WHEN "010", (A OR B) WHEN "011", (A NAND B) WHEN "100", (A NOR B) WHEN "101", (A XOR B) WHEN "110", (A XNOR B ) WHEN others;

WITH sel(3) SELECT Y<= ARITH WHEN '0',

LOGIC WHEN OTHERS;

end ARCHALU;

WAVEFORM:

CONCLUSION: Thus in the above practical we implemented an 8-bit ALU in Xilinx 9.2i Project Navigator and also observed the simulation graph of it.

xlinx - vlsi practical lab manual

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