Mansoura University

Faculty of Engineering

Department of Electronics and. . ." .

Communications Engineering

3rd Year Electronics & Comm

Second Semester - Final Exam.

Exam Time: 3 Hours

Subject: Microprocessors .Course code:COM 9323

.Exam Date: 20-6-2011

Attempt all questions. Assume any missed data. Full Mark is 100

Q.1) Correct the errors, if any, in the following statements: [20 Marks]

a. The "JMP" instruction is a basis for the explanation of data-addressing modes.b. Immediate data are constant data, while the data transferred from a register are variable

data.c. MOV AL,'AB' copies an ASCII AB

d. Relative program memory addressing is less used than other types.e. In real mode, a far jump accesses any location within the first 1KB of memory.

f. The RET instruction uses the stack to hold the return address for procedureg. Designers use SRAM because it is much 'denser' and uses less power than DRAM

h. The LRU algorithm is based on spatial locality. .

i. Write-through policy updates both the cache and the main memory simultaneously on everywrite.

j. Every process has its own page table that typically resides in main memory.k. In paging, a dirty bit can be added toIndicate the page usage.I. TLB is implemented as associative cache .m. In paging combined with seqmentation.jhe physical address is divided into two fields.n. The 8284A performs clock generation inthe 8086 microprocessor.

o. Minimum mode is obtained by grounding the mode selection pin in the 8086 lJP.

p. In.80186, the DMA controller has three fully-independent DMA channels.q. The 286 operates in both the real and protected modes.r. The 80386 lJP addresses 2GB of memory through 16-bit data bus and 32-bit address.

s. The. 804~6 contains 8 general-purpos.~},2,"~.i.tregi~ters.t. Data transfers between Pentium II and the. chipset are four bytes wide.

Q.2) Complete the following statements:

a. The tells the microprocessor which operation to perform.

b. In register addressing, may not be the destination register.

c. Direct data addr~ssing has two types.. .. ::: and -: .d. In. base-plus-index addressing, the register holds the beginning location of a memory

array.e. ...... is the least used addressing mode.f. The stack memory is' maintained by two registers; and : .. 'g. ...... is the memory to which computer speciftcatlons refer .

[15 Marks]

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h. Erasing the contents of requires a special tool that emits ultraviolet light.

i. is the time required to process a miss.j. In locality, recently-accessed items tend to be accessed again in the nearfuture.k. The is a special group of bits derived from the main memory address that is stored

with its corresponding block in cache.I. is unusable space within a given partition.m. The 8086/8088 use memory and I/O in periods called .n. In 8086, '" .. : is an extra clock period Jnsertedbetween T2 and'T3 to lengthen the bus

cycle.o. In 80186, all internal peripherals are controlled by a set of 16-bit wide registers located in

the .

p. The.. . ... is an operating system used in embedded applications that performs tasks in apredictable amount of time.

q. In 80386, is a series of 8 bytes that describe and locate a memory segment.r. There are three types of descriptor tables: -,.~.~., .'~'.,., and ,•......s. In 80386, contains the location of up to 1024 page translation tables.t. In 80486, .. :... is a special memory 'where four 32.:.bit numbers are fetched from the

memory system in five clocking periods.u. The baslcPentium Pro memory cycle consists of two sectlcns; , and .v. In order to better control the thermal conditions of the system, the Intel Core Duo processor

presents two new concepts: and '"w. In order to save l~akage power,. the .~f,"lt~!.G.qre Quo system uses mainly two techniques;

...... and .

Q.3) Choose the most suitable answer in each of ~hefollowing:. . ~ . .. [10 Marks]

1. The pin is used to insert wait states into the timing of the 808(3 microprocessor.

a) READY

b) NMI

c) 1~"fRd) ClK .

2. In 80186, the .... pin informs the !JP that" the memory is ready for read/write

a) RD

b) ARDY

c)SRDY

d)WR

3. In 80386, the pin is driven by a clock signal that is twice the operating frequency of the80386.

a) B832

b) BU8Y

c) ClK2

d) SREQ

4. In 80486, the pin provides a memory system like the 1 MS real memory system in 8086.

a)A20

b) ADS

c) A2

d) A20M

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5. In Pentium, the pin provides even parity for the memory address.

a) APCHK

b) BUSCHK

'c) BCHK

d)AP

6. In Pentium Pro, the pin is used to invalidate internal caches.a) CACHE c) HIT

. b) KEN ". d) FLUSH

7. The pin allows Pentium Pro to enter the power down state.a)CLK c)STPCLKb) SPCLK d) TCK

8. The ..... : pin = 0 when the temperature of the Pentium II exceeds 1300 C.a) POWERGOOO c) THIRMTRIPb)TESTHI d)STPCLK

9. The is an input that is placed at a logiC 1 when the power supply and clock havestabilized in Pentium 11.

a) TESTHIb) POWERGOOD

c) THERMTRIPd)WBIWT

10. The ..... : pin must be grounded to prevent Pentium from generating or receiving noise.a) SMI c) EMIb) TDI d) TOO

Q.4) Give a short answer to each of the following questions: [10x3=30 Marks]

a. "To access data at a given virtual address, the system performs some paging steps". Statethe main paging steps if the valid bit = O.

b. Compare between paging and segmentation. Do you think that paging combined withsegmentation can introduce better performance? Justify your answer.

c. Define "fan-our. What modifications must' be done to attach more than 10 unit loads to anybus pin in a 8086 microprocessor?

d. "The 80186180188 are called embedded controllers". Justify this statement. Sketch a blockdiagram for the main components of the 80186 microprocessor.

e. "In 80386, each bus cycle contains two clocking states with each state containing twoclocking periods". Using sketches only, compare between the non-pipelined timing and thetiming using wait states for the 80386 ~P.

f.. Sketch a block diagram for the Pentium memory system. How is a 32-bit memory systemconnected to Pentium?

g. Explain the following terms for Pentium ~P: Branch prediction logic and Super-scalararchitecture.

h. Sketch a block diagram for the internal structure of Pentium pro IJP.

i. If bus speed increases to 200 MHz,. what problems would you expect? How to overcomethese problems. .

j. Sketch the internal structure of the jntel Core Duo microprocessor. State the mainperformance improvements introduced by this generation.

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Q.5.a) Implement the following instructions (Assum~ EBX=100, EDI=1000, D5=100)

a. MOVCH,77

b. MOVAL, OS

c. MOV EAX,[EBX+Ebl+10] [8 Marks]

Q.5.b) For the 80486 microprocessor memory system with size' of 1 MB~ cache has 64 blocks. Findthe number of words in each block. Determine the number of bits in each field of the main memoryaddress. State the cache writing policy.' [5 Marks]

Q.5.c) Suppose that cache access time is 10 ns, main memory access time is 100 ns, and thecache hit rate is 98.5%. Find the effective access time. If paging is used and the page fault rate is1% and it costs us 10 me to access a paqe not in memory, find the effective access time.Comment on results. . [5 Marks]

Q.S.d) A system implements a paged virtual address space foreach process using a one-lever page table. Assume that the sizeof virtual memory is 8 KB. Sketch the page table, then find:

• The size of physical memory

• The number of bits in virtual address

• The number of bits iii physical address

• The page size

• The frame size

• The number of bits in page field and offset field

• To which physical address will the virtual address 80translate? [7 Marks]

V,ilual MOll)Ot)' PlrfSlcaI Memory

3

o

Q.5~e)Write 'a program that- uses a loop to' calculate the first six values In the Fibonaccl numbersequence {1, 1,2,3,5,8}. Place each value in the EAX register and display it with a call OumpRegsstatement inside the loop. [5 Marks]

My best wishes to all of you/!

)lssis. Prof. Hossam PI4Jin :Moustafa

_. ~-~.

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