you were given a hint to look at pages 132 and 133 and ......you were given a hint to look at pages...

6. Decoders and Muxes 6.1 From pages 114, 132, 133 of the class notes You are given the following design in the class notes for a non-inverting mux (meaning the selected input reaches the output without experiencing any inversion). So, if you are given a 2-to-4 decoder, 4 2-input AND gates and 1 4-input OR gate, you can build this 4-to-1 mux. But when you went to the lab, you found only 2-to-4 decoders with active-low output. Choose other 5 gates accordingly (and do not use any inverters) to complete your design!

You were given a hint to look at pages 132 and 133 and choose appropriate barrier gate and choose a final gathering gate.

Enable

F=A•B if Enable =1, F = 0, otherwise

S1S0=00

S1S0=01

S1S0=10

S1S0=11

AND Gates acting asbarrier gates

Final OR gate takes 3zero’s and one selected

2-to-4 Decoder

Enable

F=A•B if Enable = ____,otherwise F=____

Enable

F=A+B if Enable = ____,otherwise F=____

Enable

6. Decoders and Muxes 6.1 From pages 114, 132, 133 of the class notes You are given the following design in the class notes for a non-inverting mux (meaning the selected input reaches the output without experiencing any inversion). So, if you are given a 2-to-4 decoder, 4 2-input AND gates and 1 4-input OR gate, you can build this 4-to-1 mux. But when you went to the lab, you found only 2-to-4 decoders with active-low output. Choose other 5 gates accordingly (and do not use any inverters) to complete your design!

You were given a hint to look at pages 132 and 133 and choose appropriate barrier gate and choose a final gathering gate.

Enable

F=A•B if Enable =1, F = 0, otherwise

S1S0=00

S1S0=01

S1S0=10

S1S0=11

AND Gates acting asbarrier gates

Final OR gate takes 3zero’s and one selected

2-to-4 Decoder

Enable

F=A•B if Enable = ____,otherwise F=____

Enable

6.2 From page 149 of the class notes You are familiar with the building of wide muxes. Name the mux below on the left. On the right, show how would you build a 2-bit wide 4 to 1 mux which will select one of the 4 2-bit items {A1A0, B1B0, C1C0, D1D0}into the output Y1Y0, based on the select lines S1S0.

Based on the experience gained in the above exercise, state, how many 1-bit wide 2-to-1 muxes you need to build a 4-bit wide 8-to-1 mux. How many select lines it has and how many levels of 2-to-1 mux exist in your design. Summary of information learnt: Degree of selection and width of selection are two different aspects of a mux design. The degree of selection (2-to-1, 4-to-1, 8-to-1) determines the number of select lines (1, 2, 3) and also the number of levels of the simple 2-to-1 muxes if the bigger mux was built from these smallest muxes. On the other hand width increase does not change the number of select lines or number of levels. If the width of a 1-bit wide n-to-1 mux is increased to m-bits width, then simply use m of 1-bit wide n-to-1 muxes!

6.2 From page 149 of the class notes You are familiar with the building of wide muxes. Name the mux below on the left. On the right, show how would you build a 2-bit wide 4 to 1 mux which will select one of the 4 2-bit items {A1A0, B1B0, C1C0, D1D0}into the output Y1Y0, based on the select lines S1S0.

Based on the experience gained in the above exercise, state, how many 1-bit wide 2-to-1 muxes you need to build a 4-bit wide 8-to-1 mux. How many select lines it has and how many levels of 2-to-1 mux exist in your design. Summary of information learnt: Degree of selection and width of selection are two different aspects of a mux design. The degree of selection (2-to-1, 4-to-1, 8-to-1) determines the number of select lines (1, 2, 3) and also the number of levels of the simple 2-to-1 muxes if the bigger mux was built from these smallest muxes. On the other hand width increase does not change the number of select lines or number of levels. If the width of a 1-bit wide n-to-1 mux is increased to m-bits width, then simply use m of 1-bit wide n-to-1 muxes!

6.3 From page 150 in class notes: If the muxes have enable inputs, then the last level of 2-to-1 mux can be simplified to a single gathering gate as shown below!

I0I1I2I3

Now tell us a situation where you would use a single 4-input gathering gate at final level what it replaced. Suggestive incomplete schematic:

What did you build above? Mr. Trojan says that you can replace the four 4-to-1 muxes above any 4 muxes (say 4 8-to-1 muxes) without changing the final 4-input OR gate!

6.3 From page 150 in class notes: If the muxes have enable inputs, then the last level of 2-to-1 mux can be simplified to a single gathering gate as shown below!

I0I1I2I3

Now tell us a situation where you would use a single 4-input gathering gate at final level what it replaced. Suggestive incomplete schematic:

What did you build above? Mr. Trojan says that you can replace the four 4-to-1 muxes above any 4 muxes (say 4 8-to-1 muxes) without changing the final 4-input OR gate!

7. Adders 7.1 from pages 160-161 of class notes Build a FA (Full Adder) with 2 HA (Half Adders)

8. I will review the following from the class notes pages 172-178, 182-197 and also from EE101Lecture15.pdf and EE101Lecture15_sol.pdf

except for the carry-look-ahead adder

We need to finish combinational logic this week so that after the quiz, we can start with sequential logic.

7. Adders 7.1 from pages 160-161 of class notes Build a FA (Full Adder) with 2 HA (Half Adders)

8. I will review the following from the class notes pages 172-178, 182-197 and also from EE101Lecture15.pdf and EE101Lecture15_sol.pdf

except for the carry-look-ahead adder

We need to finish combinational logic this week so that after the quiz, we can start with sequential logic.

you were given a hint to look at pages 132 and 133 and ......you were given a hint to look at pages...

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