zone ltr description date approved · pdf file · 2006-01-191 b c a approved 5 6 a...
TRANSCRIPT
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale
ENGINEER
CHECKED
PREPARED
rev
4
DescriptionltrZone DateRevisions
3
2
1
CBA
Approved
5
6
A B C
6
5
1
2
3
4
sheet of
Bp
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
H
GND
CMDSTRB
EXPWR
EXPRD
EXPINTR
EXPACK
DATA[15:0]
ADDRESS[15:0]
CMDENBL
SUBBUS
64
H
CCLK
DATA
CECEO
RESET
XC17256
/OE
H
GND
H
GND
H
GND
+5VH
+5VH
XCHECKER TestH
1. M[2:0] 2. Vcc3. RT5. RD
4. GND
15. USER0 16. USER114. RESET12. INIT
13. CLKO
7. TRIG6. CCLK
11. CLKI9. DIN 10. PROG
8. DONE
Interface
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
2SOX
4DOX
6ROX
12LAX
9LBX
7ZRX
5SAX
3SBX
18SO
16DO
14RO
8LA
11LB
13ZR
15SA
17SB
IDX
_BU
F
CMDSTRB_NOT
SB6
ZR6
ZR5
ZR4
ZR3
ZR2
ZR1
USER1
USER0
TRIG
SO6
SO5
SO4
SO3
SO2
SO1
SB5
SB4
SB3
SB2
SB1
SA6
SA5
SA4
SA3
SA2
SA1
RO6
RO5
RO4
RO3
RO2
RO1
PROGRAM
M2M1M0
LB6
LB5
LB4
LB3
LB2
LB1
LA6
LA5
LA4
LA3
LA2
LA1
JP1
JP0
INIT
EXPWR_NOT
EXPRD_NOT
EXPINTR_NOT
EXPACK_NOT
D_NOT[15:0]
DONE
DO6
DO5
DO4
DO3
DO2
DO1
DIN
CMDENBL_NOT
CLKO
CLKI
CCLK
A_NOT[15:0]
XCRESET
XCRT
XCRD
XXIDX
VDD;J4,D3,D10,D16,J15,R15,R10,R4GND;G3,D4,C7,D9,C12,D15,G16,K15,M16,R16,T12,R9,T7,R3,M3,K4
NTA
34-7005
Indexer Board SchematicIDX_BD.1
V15,U15,T15,V16,U16,V17,T16,T17,U18,R17,T18,R18,P16,P17,P18,N16
V1
U6
U5
V2
U3
N1
G1
A4
A12
D18
K17
U17
T9,V8,U9,V9,U10,V10,V11,T10,U11,T11,V12,U12,V13,U13,V14,U14
U1
T2
V4
U4
J16
R1
R2
K1
C1
A8
A16
H17
M17
J1
B1
A9
A17
H18
N18
A18C15C16
V18
U7
V5
M1
E1
A6
A14
F18
L17
V7
M2
F1
A5
A13
E18
L18
N2
H2
A3
A11
C18
P1
H1
B3
A10
B18
J18
V6
T5
T4
L1
D1
A7
A15
G18
M18
K18
V3
U8
U6
U5
JP0
XCHK3
XCHK5
XCHK[16:1]
XCHK16
XCHK15
XCHK14
XCHK13
XCHK12
XCHK11
XCHK7
XCHK1
JP2
220UF
C16
CMDSTRB_NOT
R6R5R4R3R2
C13C12C11C10C9C8
C6C5C4C3
1J2
2J2
EXPACK_NOT
EXPINTR_NOT
EXPWR_NOT
EXPRD_NOT
D_NOT[15:0]
A_NOT[15:0]
C1 C2
R1
C7
JP1
JP1
CMDENBL_NOT
XCHK9
XCHK8
XCHK6
XCHK10
3J2
2
1
46
3
U7
C14
C15
SO1
DO1
RO1
LA1
LB1
ZR1
SA1
SB1
DO2
RO2
LA2
LB2
ZR2
SA2
SB2
SO3
DO3
RO3
LA3
LB3
ZR3
SA3
SB3
SO4
DO4
RO4
LA4
LB4
ZR4
SA4
SB4
U3
U4
U2SO5
DO5
RO5
LA5
LB5
ZR5
SA5
SB5
U1SO6
DO6
RO6
LA6
LB6
ZR6
SA6
SB6
4JTEST
5JTEST
7JTEST
9JTEST
11JTEST
12JTEST
13JTEST
SO2 15JTEST
17JTEST
18JTEST
20JTEST
22JTEST
24JTEST
25JTEST
26JTEST
28JTEST
30JTEST
31JTEST
33JTEST
35JTEST
37JTEST
38JTEST
39JTEST
42JTEST
44JTEST
45JTEST
47JTEST
49JTEST
51JTEST
52JTEST
53JTEST
55JTEST
57JTEST
58JTEST
60JTEST
62JTEST
64JTEST
65JTEST
66JTEST
68JTEST
70JTEST
71JTEST
73JTEST
75JTEST
77JTEST
78JTEST
79JTEST
43JTEST
46JTEST
56JTEST
59JTEST
69JTEST
72JTEST 80
JTEST
76JTEST
74JTEST
67JTEST
63JTEST
61JTEST
54JTEST
50JTEST
48JTEST
41JTEST
40JTEST
36JTEST
34JTEST
27JTEST
23JTEST
21JTEST
14JTEST
10JTEST
32JTEST
29JTEST
19JTEST
16JTEST
6JTEST
8JTEST
IDX_BD
1-19-2006_15:12 1 1
A.1
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
DIG_GND
H
28V_BATH
ANA_GND
H
+28VH
+5VH
-15VH
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
+15VH
28V
H
RTN
MR SUBBUS Connector Definition
4
MR
64SB1
63SB1
61SB1
45SB1
17SB1
18SB1
54SB1
EXPINTR
EXPACK56SB1
DATA[15:0]
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DATA15
ADDRESS[15:0]
ADDRESS3
ADDRESS14
ADDRESS13
ADDRESS12
ADDRESS11
ADDRESS10
ADDRESS9
ADDRESS8
ADDRESS7
ADDRESS6
ADDRESS5
ADDRESS4
ADDRESS2
ADDRESS1
ADDRESS0
ADDRESS15
5SB1
11
A1-19-2006_15:25
SUBBUS
1SB1
2SB1
3SB1
4SB1
6SB1
10SB1
11SB1
12SB1
13SB1
14SB1
15SB1
16SB1
21SB1
22SB1
23SB1
24SB1
25SB1
26SB1
28SB1
29SB1
31SB1
32SB1
33SB1
34SB1
36SB1
30SB1
50SB1
52SB1
CMDSTRB
EXPWR
EXPRD
CMDENBL
20SB1
58SB1
59SB1
47SB1
49SB1
51SB1
53SB1
55SB1
35SB1
46SB1
48SB1
43SB1
37SB1
38SB1
39SB1
40SB1
41SB1
42SB1
9SB1
7SB1
8SB1
EXPEN6
EXPEN5
EXPEN4
EXPEN3
EXPEN2
EXPEN1
EXPEN0EXPEN[6:0]
27SB1
19SB1
62SB1
TERMPWR
44SB1
57SB1
60SB1
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
H
GND
+5VH
11. CLKI
14. RESET
13. CLKO
15. USER0
16. USER1
8. DONE
7. TRIG
6. CCLK
5. RD
4. GND
3. RT
1. M-pins
2. Vcc
10. PROG
9. DIN
XCHECKER Test Interface
Connector DefinitionMR
MR
NO
12. INIT
R7
16JTST
15JTST
14JTST
13JTST
7JTST
5JTST
3JTST
8JTST
6JTST
9JTST
4JTST
2JTST
10JTST
1JTST
11JTST
12JTST
XCHECKER12
XCHECKER11
XCHECKER16
XCHECKER15
XCHECKER14
XCHECKER13
XCHECKER7
XCHECKER5
XCHECKER3
XCHECKER1
XCHECKER10
XCHECKER6
XCHECKER8
XCHECKER9XCHECKER[16:1]
Z1
11
AXCHECKER
1-19-2006_15:24
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
A4
Y1
Y2
Y4
Y3
A1
A2
A3
G
54HC244
+5VH
H
GND
H
GND
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
IDX_BUF.1Buffer Block for Indexer
BOARD MODIFICATIONS:Cut Pin 6 off Z1-Z6 pullups, and install 10k pulldown to GND.
11
A1-19-2006_15:22
IDX_BUF
DOX
C42
C46
98
76
54
32
1Z7
SOX
LA
ROX
SB
DO
RO
LAX
SO
SA
C45
C44
C43
LB LBX
ZRX
SBX
SAX
ZR
U6
U6
IBUF
PU
LLUP
IPAD
IO[15:0]
IOPAD16
STYLE=
A O
INVMASK=
ANDBUS
D_OUTSEL
EN ERRORSEL_
DECODE
X B[7:0]BUS_IF08
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
XOR2
AND3
XB[15:0]BUS_IF16
INV16IBUF16
OPAD
IPAD
IPAD
IPAD
I[15:0]
IPAD16
OPAD
IBUF
INVIBUF
INVIBUF
XOR2
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
XBLOX_BUS
BUS_DEF
INV
PU
LLUP
IPADIBUF
F8M
F16K
F800
F160
F3200
GC
LKS
IPADIBUF
A[15:0]
EXPINTR_NOT
EXPACK_NOT
D_NOT[15:0]
WR
RD
IREQ
INTA
ICSEL
BDSEL
D[15:0]
SBIF
See also B34-7005
A34-7005
Indexer Xilinx Chip
XXIDX.1
NTA
1 of 18
USER0
WR
EXPACK_NOT
EXPINTR_NOT
BDSEL
CMDENBL
RD
D_NOT[15:0]
ENCODING=ONE_HOTBOUNDS=7:0
A[15:0]
1-19-2006_15:12
XXIDX
1 3
A
EXPRD_NOT
EXPWR_NOT
CMDENBL_NOT
BA_NOT[15:0]
A[15:0]
A7
A6
XA XAD
BDSEL
CE[7:0]
SLICE=11:8
SLICE=5:3
XAM
BDSEL
CE0
INTA
IREQ
XCE
DECODEMASK=2#1010#
A_NOT[15:0]
D[15:0]
JP0
JP1
XJP0
XJP1
F[4:0]
F2
F4
F3
F1
F0
E
BUFE
IPAD
OPAD
OPAD
OPAD
IPAD
IPAD
IPAD
IPAD
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
IPAD
OPAD
OPAD
OPAD
IPAD
IPAD
IPAD
IPAD
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
E
BUFEE
BUFE
E
BUFE
E
BUFE
AND2
E
BUFE
IPAD
OPAD
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
INV
PU
LLUP
OPAD
OPAD
IPAD
IPAD
IPAD
IPAD
E
BUFE
A34-7005
Channel 3
Channel 2Channel 1
NTAIndividual Channels
XXIDX.2
2 of 18
CMDENBL
D5
D4
D3
RUN6
RUN5
RUN3
RUN2
D2
D1
F[4:0]
D[15:0]
A1
A2
IREQ
1-19-2006_15:28
XXIDX
2 3
A
SO1
DO1
RO1
LA1
LB1
ZR1
SA1
SB1
SVC_NOT
WR
RD
INTA
CE1
CMDENBL
RUN1
SVC_NOT
CE0
RD
RUN1 D0
RUN4
SB2
LB2
LA2
RO2
DO2
SO2
CE2
RUN2
F[4:0]
D[15:0]
A1
A2
ZR2
SA2
SVC_NOT
WR
RD
INTA
CMDENBL
SA3
ZR3
LB3
LA3
RO3
RUN3
CE3
F[4:0]
D[15:0]
A1
A2
SO3
DO3
SB3
SVC_NOT
WR
RD
INTA
CMDENBL
D7
INVIBUF
Q3
Q2
Q1Q4
GTS
GSR
DONEINCLK
STARTUP
RIP
CLK
TRIG
DATA
READBACK
PU
LLUP
OPADOBUF
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
IPAD
OPAD
OPAD
OPAD
IPAD
IPAD
IPAD
IPAD
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
IPAD
OPAD
OPAD
OPAD
IPAD
IPAD
IPAD
IPADIPAD
IPAD
IPAD
IPAD
OPAD
OPAD
OPAD
IPAD
ZREF_NOT
SVC_NOT
STB_NOT
STA_NOT
LIMB_NOT
LIMA_NOTWR
STEPOUT
RUNOUTRD
INTA
D[15:0]
DIROUT
CE
A2
A1
CMDENBL
RUNNING
F[4:0]
IDXCHAN
IBUFIPAD
IOPAD
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of3 of 18
AA34-7005
XXIDX.3
Channel 6
Channel 5Channel 4
NTA
1-19-2006_15:30
XXIDX
3 3
A
XCRD
XCRT
SB5
SO5
CMDENBL
INTA
RD
WR
SVC_NOT
A2
A1
D[15:0]
F[4:0]F[4:0]
D[15:0]
A1
A2
SVC_NOT
WR
RD
INTA
CMDENBL
RO6
RUN6
F[4:0]
D[15:0]
A1
A2
SVC_NOT
WR
RD
INTA
CMDENBL
RUN4
CE4
SO4
DO4
RO4
LA4
LB4
ZR4
SA4
SB4RUN5
CE5
DO5
RO5
LA5
LB5
ZR5
SA5
CE6
SO6
DO6
LA6
LB6
ZR6
SA6
SB6
XCRESET
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
IOPAD
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: Adrawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family IOPAD16 Macro
1
A
16-bit Input-Output Pad
23rd February 1993
IO0
IO6
IO[15:0]
IO1
IO2
IO3
IO4
IO5
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF08
B2
B0
B1
B4
B5
B7
B6
B[7:0]X
B3
ELEM=7
ELEM_7
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_3
ELEM=3
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
IBUF
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: Adrawn by KSCopyright (c) 1993, Xilinx Inc.
25th January 1993 1
A
16-bit Input Buffer
XC4000 Family IBUF16 Macro
I[15:0]
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
O[15:0]
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
IPAD
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
16-bit Input Pad
23rd February 1993
A
1
XC4000 Family IPAD16 Macro
I1
I0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I5
I4
I3
I2
I[15:0]
I6
CLK_OUT
ASYNC_CTRL
SYNC_CTRL
EN
CLOCK
CLK_DIV
CLK_OUT
ASYNC_CTRL
SYNC_CTRL
EN
CLOCK
CLK_DIV
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
GND
CLK_OUT
ASYNC_CTRL
SYNC_CTRL
EN
CLOCK
CLK_DIV
CLK_OUT
ASYNC_CTRL
SYNC_CTRL
EN
CLOCK
CLK_DIV
AA34-70054 of 18
Global Rate ClocksNTA
GCLKS.1
F3200
F16K
F160
F800
DIVIDE_BY=512DUTY_CYCLE=256
F8M
DIVIDE_BY=5DUTY_CYCLE=2
1-19-2006_15:26
GCLKS
1 1
A
DUTY_CYCLE=2DIVIDE_BY=5
DUTY_CYCLE=2DIVIDE_BY=4
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND3B1
X B[5:0]BUS_IF06
AND2
SYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
D[7:0]IREQ
INTA
IREQBIT
BE[7:0]D[15:0]
OE
RD
D_NOT[15:0]
SDBIF
AND2
BO
AORBUS1
GND
E
OBUFEAND2
OR2
XB[5:0]BUS_IF06
XB[15:0]BUS_IF16
XNOR2
XNOR2
D_OUTSEL
EN ERRORSEL_
DECODEX B[7:0]
BUS_IF08
XB[2:0]BUS_IF03
OR2
A O
INVMASK=
ANDBUS
SUB_STARTS_AT=
MAIN SUB
OUTSLICE
BA
CAST
AND4
E
OBUFE
GND
A34-7005
NTASubbus Interface
SBIF.1
5 of 18
WR
ICSEL
EXPINTR_NOT
A_BOUNDS=7:0A_ENCODING=ONE_HOT
B_BOUNDS=7:0B_ENCODING=UBIN
D[7:0]
SUB=11:3SLICE=11:3
DECODEMASK=2#0000_0100_0#
STYLE=DECODE
BITEN[7:0]
XA XAI
A2
ICP3
ICP4
INTA
XBE
D[15:0]
D[5:0] ICP[5:0]XICPXCPD
XICPLICP[2:0]
EXPACK_NOT
BDSEL
INTA
RD
WR
A1
INVMASK=0
XBITEN
XBEU
RD
BDSEL
BITEN[7:0]
ASYNC_VAL=0
RD
IREQ
INTA
INTA
IREQ
A[15:0]ICP5
D_NOT[15:0]
RD
BDSEL
11
A1-19-2006_15:38
SBIF
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
I
RDCLK
TRIG
RIP
DATA
RDBK
29th March 1993
LCA Bitstream Readback Controller
XC4000 Family READBACK Macro
drawn by KSCopyright (c) 1993, Xilinx Inc. A
1
CLK
TRIG DATA
RIP
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
XOR2
ZREF_NOTRESETPOS
OUTLIMIT
LIMITLIMB_NOT
LIMA_NOT
INLIMIT
OUT
CP1
CP0
F0
LIMITS
C
D Q
IFD
A1
A2
CE
D[15:0]
OUTRD
RESETPOS
STEPCLK
WR
ZEROCT
F8M
CTRS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
RUNNING
STEPCLKSTEPENBL
RCLK
STEPCLK
AND3B2
XOR2
XOR2
RCLKRC[3:0]
F[4:0]
RATEGEN
OBUF
OBUF
OBUF
C
D Q
IFD
C
D Q
IFD
A34-7005
IDXCHAN.1Indexer Channel
NTA
9 of 18
F0
F0
LIMB_NOT
LIMA_NOT
F0
RCLK
F0
RUNNING
RD
WR
CE
A2
A1
CP1
CP0
F[4:0]
CP[11:8]
OUT
OUT
INLIMIT
CP2
CP3
CP4
OUTLIMIT
CMDENBL
D[15:0]
31
A1-19-2006_15:31
IDXCHAN
STEPOUT
RUNOUT
DIROUT
ZREF_NOT ZRNF0
LBN
LAN
ZRN
LBN
LAN
AND2B1
BUFOD
QD
C
FD
QD
C
FD
OR2
IBUF
IBUF
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
E
BUFE4
E
BUFE4AND4
INV
INV
INV
OR3
AND2
AND2B1
AND2B1
AND2B1
s: Servicedn: Not Requested (NRQD)
10: nsI: INTAR: Running
LEGEND:
R I
R
R
I
I
R I
R I
R I
Channel Status, Service Req.
IDXCHAN.2
NTA
10
R I
R I
A34-7005
00
0111
10 of 18
INTA
NRQDINTA
F0
RUNNING
ZRN
SVC_NOT
A2
A1
D7
D6
D5
D4
D3
D2
D1
RD
D0INLIMIT
CE
RUNNING
OUT
32
A1-19-2006_15:32
IDXCHAN
OUTLIMIT
STA_NOT
STB_NOT
NRQD
CMDENBL
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
SUB=SUB_STARTS_AT=
MAIN SUB
OUTSLICE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
XB[15:0]BUS_IF16
SYNC_VAL=ASYNC_VAL=
CLK_EN
D_IN
ASYNC_CTRL
Q_OUT
SYNC_CTRL
CLOCK
STYLE=
DATA_REG
X B[4:0]BUS_IF05
X B[3:0]BUS_IF04
AND3
AND2
A34-7005
NTAChannel Configuration Port
IDXCHAN.3
11 of 18
D5
WR
CP[11:8]
CP[4:0]
XCPH
XCPL
XDH
XDLXDD[15:0]
CE
A2
A1
1-19-2006_15:33
IDXCHAN
3 3
A
SLICE=4:0
SLICE=11:8
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF06
B0
B1
B3
B4
B5
B[5:0]X
B2
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
E
BUFE4
E
BUFE4
A34-7005
NTAInterrupt Acknowledge
IREQBIT.1
8 of 18
IREQ
D[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
INTA
1-19-2006_15:40
IREQBIT
1 1
A
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
AND2B1
AND2
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
D_NOT
WRE
RDE
DIOBITA
A34-7005 A
NTASubbus Data Bus Interface
SDBIF.1
6 of 18
D_NOT10
D_NOT13
D_NOT14
D_NOT15D_NOT7
D_NOT6
D_NOT4
D_NOT3
D_NOT2
D_NOT[15:0]
WRE
WRE
WRE
D8
WRE
RDE
WRE
RDE
BE0
D0
WRE
BE[7:0]
WRE
WRE
WRE
WRE
D1
D2
D3
D4
D5
D6
D7
BE1
BE2
BE3
BE4
BE5
BE6
BE7
RD
OE
RDE
WRE
RDE
WRE
RDE
WRE
RDE
WRE
RDE
WRE
RDE
WRE
RDE
WRE
D9
D10
D11
D12
D13
D14
D15
11
A1-19-2006_15:17
SDBIF
D_NOT0
D[15:0]
D_NOT1
D_NOT5
D_NOT12
D_NOT11
D_NOT8
D_NOT9
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF06
B0
B1
B3
B4
B5
B[5:0]X
B2
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF08
B2
B0
B1
B4
B5
B7
B6
B[7:0]X
B3
ELEM=7
ELEM_7
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_3
ELEM=3
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 7/21/93
A
1
XBLOX Family BUS_IF03
B[2:0]
B2
B0
B1
XELEM_0
ELEM=0
ELEM_2
ELEM=2
ELEM=1
ELEM_1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
OR2
QD
C
FDO
S0
D0
D1
M2_1B2
O
S0
D0
D1
M2_1B2 OR2
QD
C
FDAND2
AND2B1OR2
A34-7005 A
Indexer Limit SwitchesNTA
LIMITS.1
12 of 18
F0
CP0
F0
OUT
ARMZERO
LIMIT
INLIMIT
OUTLIMIT
LIMA_NOT
LIMB_NOT
21
A1-19-2006_15:35
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
AND2B1
AND3B2
OR2B1
AND2
AND4B2
QD
C
FD
QD
C
FD
OR2
B "Zero Armed" StateRESETPOS Output
00
A: ARMZERO Input
A+Z
AZ
A
A
11
00
A34-7005
LIMITS.2
NTAIndexer Limit Switches
10
01
Z: OZ Qualified Zeroref
13 of 18
ZREF_NOT
F0
F0
CP1
OUT
B
RESETPOS
ARMZERO
OZ
22
A1-19-2006_15:36
LIMITS
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
W
R
S
CLK
L
K
ctstate
AND2
AND2
AND2
INVCEO
D[15:0]Q[15:0]
L
CLRC
CE
UP
TC
CC16CLED
AND3B1
H
GND
EBUFE16
INV
16
CEOCE
CCLR
L
D[15:0]Q[15:0]
TC
CC16CLE
GND
C
CE
CLR
D Q
FDCEAND2B1
AND2OR2
A34-7005
CTRS.1
NTAIndexer Channel Counters
15 of 18
WR
POSEN
CTEN
CTEN
D[15:0]
D[15:0]
RESETPOS
RPOS
RPOS
DBAR[15:0]
OUT
CE
A2
A2
CE
ZEROCT
POSEN
A1
DP[15:0]
WR
DC[15:0]
STEPCLK
RPOS
F8M
POSEN
RDA1
OUT
CTEN
11
A1-19-2006_15:37
CTRS
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
QD
C
FD_1
AND3
QD
C
FD
A34-7005
STEPCLK.1
NTAIndexer Channel Step Gen
14 of 18
STEPCLK
STEPENBL
RCLK
RUNNING
1-19-2006_15:35
STEPCLK
1 1
A
of
B
A
1
1234
234
B
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED
rev
Al
QD
C
FD_1
QD
C
FD
QD
C
FD
XOR2
QD
C
FD
QD
C
FD
S0
OD1
D0M2_1
D0
D1
D2
D3
E
O
S0
S1
M4_1E
INV
VCC
INV
S0
OD1
D0M2_1
QD
C
FD
INV
RATEGEN.1Channel Rate Selection
NTA
Divide by 3/2
A34-700518 of 18
RC3
RC2
RCLK
F0
F[4:0]
F1
RC[3:0]
F2
F3
F4
RC1
RC0F0
F0
11
A1-19-2006_15:37
RATEGEN
WAND1
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family BUFOD Macro
Open-Drain Buffer
1
A
6th April 1993
OI
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A Rev:
Ver:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Date:
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
7/21/93
XBLOX Family BUS_IF_IF16
ELEM_7
ELEM=7
ELEM=15
ELEM_15
ELEM=14
ELEM_14
ELEM=13
ELEM_13
ELEM=12
ELEM_12
ELEM=11
ELEM_11
ELEM=10
ELEM_10
ELEM=9
ELEM_9
ELEM=8
ELEM_8
ELEM=6
ELEM_6
ELEM=5
ELEM_5
ELEM=4
ELEM_4
ELEM=3
ELEM_3
ELEM=2
ELEM_2
ELEM=1
ELEM_1
ELEM=0
ELEM_0
X
B7
B0
B1
B2
B3
B4
B5
B6
B8
B9
B10
B11
B12
B13
B14
B15
B[15:0]
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF05
B0B[4:0]
B4
B3
B1
B2
XELEM_0
ELEM=0
ELEM_1
ELEM=1
ELEM_3
ELEM=3
ELEM_4
ELEM=4
ELEM=2
ELEM_2
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
XBLOX_BUSELEM
ELEMENT
Sheet Size: A
B
A
1
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234
B
A
Rev:
Ver:
Title:
Comments:
Date:
A
17/21/93
XBLOX Family BUS_IF04
B0
B1
B3
B[3:0]X
B2
ELEM=3
ELEM_3
ELEM=1
ELEM_1
ELEM=0
ELEM_0
ELEM_2
ELEM=2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
T
BUFT
T
BUFT
T
BUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
w/ an Active High Enable4-Bit 3-State Buffer
XC4000 Family BUFE4 Macro
23rd February 1993 1
A
T
O0I0
O1I1
I2 O2
I3 O3
E
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
E
BUFE
INV
INV
IBUF
E
OBUFE
A
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
NTA Data Bus Bit Interface
IOBITA.1
7 of 1811
A1-19-2006_15:17
IOBITA
D
WRE
RDE
D_NOT
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
AND2B2
AND2B1
OR2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1
A
1st March 1993
XC4000 Family M2_1B2 Macro
Copyright (c) 1993, Xilinx Inc.drawn by KS
D0 & D1 Inverted2-to-1 Mutiplexer w/
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
OR2
OR2
AND2B1
OR2
QD
C
FD
QD
C
FD
QD
C
FD
QD
C
FD
OR2B1
AND4B2
OR2AND2
AND2
AND2B1
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AND2B1AND3B2
A34-7005 A
State Machine for Counter LatchNTA
CTSTATE.1
16 of 18
KD
S
S
L
K
R
W
CLK
LD
4-20-2005_16:20
ASHEET
1 1
AA
ATMOSPHERIC RESEARCH PROJECT
Drawing No.
TITLE
HARVARD UNIVERSITY
Code ID No.size
Scale sheet
ENGINEER
CHECKED
PREPARED5
4
3
2
1
5
4
3
2
1
A B
A B
rev
of
AA34-7005
"both" as a source."either" as a destination andx in a state block indicates
KD: Clocked StateLD: Latched StateK: Counter Clock Output
L: Latch OutputW: Write InputS: Step Clock Input
LEGEND:
S WS W
S W
S W
WW
S W
S W
S WS W
S
SS
S W
S W
S W
11x00000 0010
010x 011x
001111x110x10001
S W
S W
S W
S
W 10x0
10x0
State Machine for Counter LatchNTA
CTSTATE.2
17 of 18
AND2B2
S0
OD1
D0M2_1
H
G
F
E
H
G
F
E
C
A
B
C
D
8 7 6 5 4 3 2 1
D
B
A
8 7 6 5 4 3 2 1
Rev:
Ver:
Title:
Comments:
Date:
Sheet Size: E
XOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
CY4_25DEC-FG-CIINC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18 CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
XOR2
XOR2
XOR2
XOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
XNOR2
XOR2
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
XOR2
XNOR2
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INV
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
XNOR2
INV
DEC-FG-0
CY4_26
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
XOR2
XOR2
XOR2
XOR2
XOR2
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
CY4_25DEC-FG-CI
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-1
CY4_19
S0
OD1
D0M2_1
XOR2
S0
OD1
D0M2_1
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
OR2
OR2
OR2
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
INC-FG-CI
CY4_18
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
AND2
AND2
Copyright (c) 1993, Xilinx Inc.drawn by KS
XC4000 Family CC16CLED Smart Macro
1
A
Counter w/ Clk En & Async Clr (using CY4)16-Bit Cascad,Loadable,Dir Bin
14th June 1993
L_CECE
CLR
C
UP
L
TC_UP
CO_UP
CEO
TC
TC_DN
C14_DN
RLOC=R8C1.F
RLOC=R8C1.G
RLOC=R7C1.F
RLOC=R7C1.G
RLOC=R6C1.F
RLOC=R6C1.G
RLOC=R5C1.F
RLOC=R4C1.F
RLOC=R5C1.G
RLOC=R4C1.G
RLOC=R3C1.G
RLOC=R3C1.F
RLOC=R2C1.F
RLOC=R2C1.G
RLOC=R1C1.F
RLOC=R1C1.G
MD13_UP
MD14_UP
MD15_UP
RLOC=R2C1.FFXQ12
RLOC=R3C1
RLOC=R8C0.G
RLOC=R7C0.F
RLOC=R7C0.G
RLOC=R6C0.G
RLOC=R5C0.F
RLOC=R5C0.G
RLOC=R3C0.G
RLOC=R4C0.F
RLOC=R4C0.G
RLOC=R3C0.F
RLOC=R2C0.F
RLOC=R2C0.G
RLOC=R1C0.F
RLOC=R1C0.G
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
Q14RLOC=R1C1.FFX
Q15RLOC=R1C1.FFY
RLOC=R3C1.FFXQ10
RLOC=R3C1.FFYQ11
RLOC=R2C1.FFYQ13
RLOC=R4C1.FFYQ9
RLOC=R4C1.FFXQ8
RLOC=R0C1RLOC=R0C0
MD0
MD6_UP
RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R8C1
Q7RLOC=R5C1.FFY
Q5RLOC=R6C1.FFY
Q4RLOC=R6C1.FFX
Q3RLOC=R7C1.FFY
Q2RLOC=R7C1.FFX
Q0RLOC=R8C1.FFX
RLOC=R7C1
RLOC=R6C1
Q1RLOC=R8C1.FFY
MD0_UP
MD1_UP
MD2_UP
MD3_UP
MD5_UP MD5
MD4
MD2
MD3
MD1
MD7
RLOC=R5C1
RLOC=R8C0.F
RLOC=R6C0.F
Q6RLOC=R5C1.FFX
MD6
MD7_UP
MD4_UP
MD10_UP
RLOC=R2C1
MD11_UP
MD9_UP
MD8_UP
RLOC=R4C1
RLOC=R3C0
RLOC=R2C0
RLOC=R4C0
RLOC=R1C0 RLOC=R1C1
MD0_UP
C14_UP
C13_UP
C12_UP
C11_UP
C10_UP
C9_UP
C8_UP
C7_UP
D8
D9
D10
D11
D12
D13
D15
D14
Q14
L
Q8
Q9
Q10
Q11
Q12
Q13
L
MD11_UP
MD12_UP
MD14_UP
MD15_UP
MD13_UP
MD10_UP
MD9_UP
MD8_UP
MD8_UP
MD10_UP
MD11_UP
MD14_UP
MD15_UP
Q15
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C13_DN
C14_DN
MD15_UP
MD14_UP
MD12_UP
MD11_UP
MD10_UP
MD9_UP
MD8_UP
Q8
Q11
Q14MD14
MD15
MD12
MD10
MD11
MD13
MD8
MD9
CO_DN
MD9_UP
C7_DN
C8_DN
C9_DN
C10_DN
C11_DN
C12_DN
C7_UP
C9_UP
C8_UP
C10_UP
C11_UP
C12_UP
C13_UP
C14_UPTQ15_DN
TQ13_DN
TQ12_DN
TQ10_DN
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD2_UP
C1_DN
C6_DN
MD7_UP
MD2_UP
MD4_UP
MD5_UP
MD6_UP
D7
L
MD6_UP
TQ6_UP
C4_UP
C3_UP
C2_UP
C1_UP
C0_UP
C6_UP
MD5_UP
MD4_UP
MD0
C0_DN
C2_DN
C3_DN
C4_DN
MD3_UP
MD1_UP
TQ5_UP
TQ4_UP
TQ3_UP
TQ2_UP
TQ1_UP
TQ0_UP
TQ7_DN
TQ6_DN
MD7
MD6
TQ5_DN
TQ4_DN
MD5
TQ3_DN
TQ2_DN
MD3
MD2
MD1
TQ1_DN
TQ0_DN
MD4
D0
Q0
L
C0_UP
D1
Q1
L
L
Q2
D2
C1_UP
C2_UP
D3
Q3
L
C3_UP
D4
Q4
L
L
Q5
D5
C4_UP
L
Q6
D6
C5_UP
C5_DN
TQ7_UPC6_UP
C5_UP
MD7_UP
MD0_UP
MD1_UP
MD3_UP
MD7
C6_DN
MD7_UP
Q7
L_UP
MD6
C5_DN
MD6_UP
Q6
L_UP
MD5
C4_DN
MD5_UP
Q5
L_UP
L_UP
Q4
MD4_UP
C3_DN
MD4
L_UP
Q3
MD3_UP
C2_DN
MD3
MD2
C1_DN
MD2_UP
Q2
L_UP
L_UP
Q1
MD1_UP
C0_DN
MD1
L_UP
Q0
MD0_UPMD0
L_UP
Q9
L_UP
Q10
L_UP
L_UP
L_UP
Q12
L_UP
Q13
MD13_UP
L
L
L
TQ8_DN
TQ9_DN
TQ11_DN
TQ8_UP
TQ9_UP
TQ10_UP
TQ11_UP
L
TQ14_UP
TQ14_DN
L
L_UP
L_UP
MD15
TQ15_UPQ15
L
Q7
D15
D14
D13
D11
D10
D9
D8
D[15:0]
D0
D1
D2
D3
D4
D5
D6
D7
D12
TQ12_UP
TQ13_UP
MD12_UP
MD13_UP
Q[15:0]
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q5
Q4
Q1
Q0
Q2
Q3
Q6
MD12_UP_
C13_DN
L_UP
INV
T
BUFTT
BUFTT
BUFT
T
BUFTT
BUFTT
BUFTT
BUFTT
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFT
T
BUFTT
BUFTT
BUFTT
BUFT
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
1
A
w/ an Active High Enable16-Bit 3-State Buffer
XC4000 Family BUFE16 Macro
23rd February 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
T
I14
I15
I13
I[15:0]
I3
I2
I1
I0
I10
I4
I5
I6
I7
I8
I9
I11
I12
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
O15
O14
E
Rev:
Title:
Comments:
2 1
12
A
B
C
DD
C
B
A
Ver:Date:
Sheet Size: A
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family INV16 Macro
16-bit Inverter
22nd February 1993
A
1
O15
O14
O13
O12
O11
O10
O9
O8
O7
O6
O5
O4
O3
O2
O1
O0
O[15:0]
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
I[15:0]
INV
AND2
Sheet Size: D
A
B
D
8
12345678
7 6 5 4 3 2 1
D
C
B
A
C
Rev:
Ver:
Title:
Date:
Comments:
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
S0
OD1
D0M2_1
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
C
CE
CLR
D Q
FDCE
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
EXAMINE-CI
CY4_42
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
OR2
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
COUT0
COUT
CIN
B0
A1
B1
ADD
A0
CARRY MODE
(G1)
(G4)
(F2)
(F1)
(F3)
CY4
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
INC-FG-CI
CY4_18
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
XOR2
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
O
I4
I3
I2
I1
FMAP
C
CE
CLR
D Q
FDCE
S0
OD1
D0M2_1
INC-FG-1
CY4_19
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family CC16CLE Macro
16-Bit Cascadable,Loadable Binary
17th Feburary 1993
A
1
Counter w/ Clk En & Async Clr (using CY4)
Q1
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q15Q7
Q0
Q2
Q3
Q4
Q5
Q6
Q[15:0]
TQ0
D14
MD10
MD11
MD12
MD13
MD14
MD8
MD15
MD9
Q15
Q13
Q8
L
L
L
LMD15
Q4RLOC=R6C0.FFX
Q12
Q11
Q10
Q9
Q14
L
C14
C13
C12
C11
C10
C9
D13
D12
D11
D10
D15
C8
C7
L
L
L
Q0
L
L
L
L
L
L
C0
D7
D1
D2
D3
D4
D5
C1
C2
C3
C4
C5
C6
D0
MD1
MD3
MD0
D6
MD5
MD2
MD7
MD6
L
Q7
L
Q6
Q1
Q2
Q3
Q4
Q5
MD4
TQ1
TQ2
TQ3
TQ4
TQ5
TQ6
TQ7C6
C5
C0
C2
C1
C3
C4
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MD7
C7
C7
C8
C9
C10
C11
C12
C13
C14TQ15
TQ14
TQ13
TQ12
TQ11
TQ10
TQ9
TQ8
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
RLOC=R4C0.F
RLOC=R1C0.G
RLOC=R1C0.F
RLOC=R2C0.G
RLOC=R2C0.F
RLOC=R3C0.G
RLOC=R3C0.F
RLOC=R4C0.G
RLOC=R2C0
RLOC=R1C0
RLOC=R4C0
RLOC=R3C0RLOC=R7C0
RLOC=R8C0
RLOC=R5C0
RLOC=R6C0
RLOC=R0C0
RLOC=R5C0.G
RLOC=R5C0.F
RLOC=R6C0.G
RLOC=R6C0.F
RLOC=R7C0.G
RLOC=R7C0.F
RLOC=R8C0.G
RLOC=R8C0.F
Q0RLOC=R8C0.FFX
Q1RLOC=R8C0.FFY
Q2RLOC=R7C0.FFX
Q3RLOC=R7C0.FFY
Q5RLOC=R6C0.FFY
Q6RLOC=R5C0.FFX
Q7RLOC=R5C0.FFY
Q8RLOC=R4C0.FFX
Q9RLOC=R4C0.FFY
Q10RLOC=R3C0.FFX
Q11RLOC=R3C0.FFY
Q12RLOC=R2C0.FFX
Q13RLOC=R2C0.FFY
Q14RLOC=R1C0.FFX
Q15RLOC=R1C0.FFY
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
D9
D8
CEO
CLR
L_CE
D15
D8
D9
D13
D14
D12
D11
D10
D[15:0]
D2
D5
D7
D6
D4
D3
D1
D0
L
C
TC
CE
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
INV
VCC
GND
drawn by KSCopyright (c) 1993, Xilinx Inc.
D Flip-Flop w/ an inverted Clock
XC4000 Family FD_1 Macro
A
11st March 1993
CBC
QD
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
S0
OD1
D0M2_1S0
E
OD0
D1
M2_1E
S0
E
OD0
D1
M2_1E
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date: 1st December 1994
Bdrawn by KSCopyright (c) 1993, Xilinx Inc.
4-to-1 Multiplexer with Enable
1
XC4000 Family M4_1E Macro
S1
OM01
M23
D0
D1
D3
D2
E
S0
M23
M01
O
AND2B1
OR2
AND2
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
1
A
2-to-1 Multiplexer
O
M0
M1
D0
D1
S0
C
CE
CLR
D Q
FDCE
GND
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
D
C
Q
RLOC=R0C0
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
INV
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
BUFT
1
A
XC4000 Family BUFE Macro
3-State Buffer w/ Active High En
3rd March 1993
Copyright (c) 1993, Xilinx Inc.drawn by KS
RLOC=R0C0
O
E
I
T
Sheet Size: A
B
A
1
1234
234
B
A
Rev:
Ver:
Title:
Comments:
Date:
T
OBUFT
INV
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family OBUFE Macro
22nd February 1993
3-State Output Buffer with
1
A
Active High Enable
O
E
I
T
INV
Sheet Size: A
B
A
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23rd December 1992 1
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
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VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
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VCC
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23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
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VCC
D Flip-Flop
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23rd December 1992 1
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VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
ACopyright (c) 1993, Xilinx Inc.drawn by KS
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AND2B1
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
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VCC
D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
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23rd December 1992 1
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23rd December 1992 1
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D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
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AND2B1
OR2
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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23rd December 1992 1
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
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drawn by KSCopyright (c) 1993, Xilinx Inc.
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A
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D Flip-Flop
XC4000 Family FD Macro
23rd December 1992 1
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23rd December 1992 1
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23rd December 1992 1
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
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23rd December 1992 1
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
XC4000 Family M2_1 Macro
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
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14th December 1992
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14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
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Copyright (c) 1993, Xilinx Inc.drawn by KS
14th December 1992
XC4000 Family M2_1 Macro
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14th December 1992
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14th December 1992
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14th December 1992
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14th December 1992
XC4000 Family M2_1 Macro
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
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2-to-1 Multiplexer with Enable
drawn by KSCopyright (c) 1993, Xilinx Inc.
XC4000 Family M2_1E Macro
A
16th December 1992 1
D1
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E