컴퓨터구조-13장
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컴퓨터구조-13장TRANSCRIPT
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13. Multiprocessors
충남대학교 정보통신공학과박 종 원
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
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컴퓨터구조 1
Processor 0Processor 1
Processor 2Processor 3
Processor 4Processor 5
Processor 6Processor 7
Memory 0Memory 1
Memory 2Memory 3
Memory 4Memory 5
Memory 6Memory 7
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컴퓨터구조 1
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컴퓨터구조1
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컴퓨터구조 1
If a processor requests control of the bus and the arbiter finds its PI input equal to 1,it sets its PO output to 0.The processor whose arbiter has a PI=1 and PO=0, gets the control of the bus.
Processor 1 Processor 2 Processor 3 Processor 4
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컴퓨터구조 1
If processors 2 and 3 requests control of the busthe processor 2 whose arbiter has a PI=1 and PO=0, gets the control of the bus.The processor 3 takes control of the bus when the processor 2 completes the bus operation.If a higher priority processor want to use the bus it must wait until any lower priority processor finishes to use the bus.
Processor 1 Processor 2 Processor 3 Processor 4
1 1 1 0 0 0 0 0
0 1 1 0
1wired-OR
request
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컴퓨터구조 1
0요청
0요청
1
1
1
1 0 0 0 0 0
Daisy-chain 참고
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컴퓨터구조 1
1
01
0
0
0
1
1) 상위의 device 가 요청하지 않은 상태에서 자신도 요청하지 않은 경우
Daisy-chain 참고
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컴퓨터구조 1
1
100
1
01
10
0 1
2) 상위의 device 가 요청하지 않은 상태에서
자신이 요청한 경우 ( 처리 후 요청을 철회한 경우 )
Daisy-chain 참고
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컴퓨터구조 1
0
10
0
0
1
0
3) 상위의 device 가 요청한 상태에서
자신이 요청한 경우
Daisy-chain 참고
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컴퓨터구조 1Processor 1 Processor 2 Processor 3 Processor 4
PI PO0 0 높은 우선순위의 processor 가 Bus 요청0 1 이런 경우 없음10 높은 우선순위의 processor 가 Bus 요청하지 않았고 , 자신이 Bus 요청했음 자신이 Bus 사용권 가짐 Bus busy line = 11 1 높은 우선순위 요청 없고 자신도 요청하지 않았음
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컴퓨터구조 1
0 1 1 0
0 1
0 1 0 0
0 1 0 0
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컴퓨터구조 1
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컴퓨터구조 1
Write-throughCache 내용을 바꾸는즉시 MM 내용을 바꿈
Write-backCache 의 해당 block 을교체시 MM 내용을 바꿈
52 120 176
52 120 176
52 120 176
52 176
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Loop Unrolling in Superscalar
Integer instruction FP instruction Clock cycleLoop: LD F0,0(R1) 1
LD F6,-8(R1) 2LD F10,-16(R1) ADDD F4,F0,F2 3LD F14,-24(R1) ADDD F8,F6,F2 4LD F18,-32(R1) ADDD F12,F10,F2 5SD 0(R1),F4 ADDD F16,F14,F2 6SD -8(R1),F8 ADDD F20,F18,F2 7SD -16(R1),F12 8SD -24(R1),F16 9SUBI R1,R1,#40 10BNEZ R1,LOOP 11SD -32(R1),F20 12
2.4(12/5) clocks per iterationAssumptionLD to ADDD: 1 CycleADDD to SD: 2 Cycles
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Four different threads
SUN T1Intel Pentium DIBM Power5Clock cycle time
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SMT: Simultaneous Multithreading
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SMT extensions by roughly doubling the capacity of existing SS processors
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Potential Performance Advantages from SMT
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Pipe 누설 실험
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Pipe 진동 실험