© 2000 prentice hall inc. figure 7.1 the current mirror

© 2000 Prentice Hall Inc.

Figure 7.1 The current mirror.


Figure 7.2 Emitter follower with bias current source.


Figure 7.3 The offset voltage can be reduced by cascading a complementary (pnp) emitter follower.


Figure 7.4 Doubling the junction area of a BJT is equivalent to connecting two of the original BJTs in parallel.


Figure 7.5 Current mirror for Examples~7.1 and 7.2.


Figure 7.7 Output characteristic for the current mirror of Figure 7.5.


Figure 7.8 Dynamic output resistance of the current mirror of Figure 7.5.


Figure 7.9 Collector characteristic of Q2, illustrating the Early voltage.


Figure 7.10 The Wilson current source, which has a high output resistance.


Figure 7.11 The Widlar current source, which is useful for small currents.


Figure 7.12 Typical biasing circuit for a bipolar IC.


Figure 7.13 Answer for Exercise 7.2.


Figure 7.14 JFET as a current source.


Figure 7.15 NMOS current mirror.


Figure 7.16 NMOS Wilson current source.


Figure 7.17 Circuits for Exercise 7.4.


Figure 7.18 Current versus voltage for the circuits of Figure 7.17.


Figure 7.19 Dynamic resistance versus voltage for the circuits of Figure 7.17.


Figure 7.20 One solution for Exercise 7.7.


Figure 7.21 One solution for Exercise 7.8.


Figure 7.22 Basic BJT differentiial amplifier.


Figure 7.23a Basic BJT differential amplifier with waveforms.


Figure 7.23b Basic BJT differential amplifier with waveforms.


Figure 7.24 pnp emitter-coupled pair.


Figure 7.25 Collector currents versus differential input voltage.


Figure 7.26 Voltage transfer characteristic of the BJT differential amplifier.


Figure 7.27 Differential amplifier with emitter degeneration resistors.


Figure 7.28 Voltage transfer characteristic with emitter degeneration resistors. REF = 40(VT/IEE).


Figure 7.29 Either a balanced or single-ended output is available\break from the differential amplifier.


Figure 7.30 Emitter-coupled pair with current-mirror load.


Figure 7.31 Answers for Exercise 7.10.


Figure 7.32 Answers for Exercise 7.11.


Figure 7.33 Small-signal equivalent circuit for thedifferential amplifier of Figure 7.27. (REB is the output impedance of the current source IEE.)


Figure 7.34 Half-circuit for a differential input signal.


Figure 7.35 Small-signal equivalent circuit with a pure common-mode input signal.


Figure 7.36 Half-circuit for a pure common-mode input signal.


Figure 7.37 Emitter-coupled pair of Exercise 7.13.


Figure 7.38 Addition of emitter followers to increase input impedance.


Figure 7.39 First attempt in Example 7.4.


Figure 7.40 Differential amplifier of Example7.4 using the Wilson current source.


Figure 7.41 Differential amplifier of Example 7.4.


Figure 7.42a Waveforms for the differential amplifier of Example 7.4.


Figure 7.42b Waveforms for the differential amplifier of Example 7.4.


Figure 7.42c Waveforms for the differential amplifier of Example 7.4.


Figure 7.43 Source-coupled differential amplifier.


Figure 7.44 Drain currents versus normalized input voltage.


Figure 7.45 Differential output voltage versus normalized input voltage.


Figure 7.46 Small-signal equivalent circuit for the source-coupled amplifier of Figure 7.43.(Note: RSB is the output resistance of the bias current source I.)


Figure 7.47 Source-coupled differential pair of Example 7.5.


Figure 7.48 Differential and common-mode voltage gains versus frequency for the circuit of Example 7.5.


Figure 7.49 CMOS op amp.


Figure 7.50 Small-signal equivalent circuit for the output stage consisting of M7 and M2.


Figure 7.51 Small-signal equivalent circuit for the source-coupled input stage.


Figure 7.52 Test circuit for open-loop gain. The internal circuit for the op amp is shown in Figure 7.49.


Figure 7.53 Open-loop gain versus frequency for the CMOS op amp.


Figure 7.54 Unity-gain buffer amplifier of Exercise 7.16.


Figure 7.55 A BJT op amp.


Figure 7.56 Equivalent circuit for the first stage of Figure 7.52. REB represents the output impedance of current sinkQ8. Ri = rp3 + r p4 is the differential input impedance of the second stage.

© 2000 prentice hall inc. figure 7.1 the current mirror

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