何宾 2008.09

2008.09E - mail: [email protected]

XilinxHDLHDL IPIPIPIPIP VHDL- 5

VHDL: VHDLVHDLVHDLEDAPLDVHDL VHDLVHDLEDAVHDL-VHDL

VHDL-VHDL 1 2

VHDL-VHDL FPGA PLD

VHDL-VHDL PLDPLD

VHDL-VHDL

VHDL-VHDL PLDEDA PLDPLD

VHDL- PLDPLD

VHDL- B21

VHDL-

XST

VHDL- HDL[5-2]VHDLLibrary ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Use ieee.std_logic_arith.all;Entity mult_add is Port( clk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); b0,b1,b2,b3 : in std_logic_vector(7 downto 0); y : out std_logic_vector(15 downto 0));end multadd;

VHDL- HDLarchitecture behav of mult_add isbegin process(clk) begin if rising_edge(clk) then y

VHDL- n5.2.2.3

VHDL- n =

VHDL- 1n

VHDL-() 2 3

VHDL- PLDPLD

VHDL-() N

VHDL-VHDL

VHDL-VHDLlibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity multipliers_2 isgeneric(A_port_size : integer := 18; B_port_size : integer := 18); port(clk : in std_logic; A : in unsigned (A_port_size-1 downto 0); B : in unsigned (B_port_size-1 downto 0); MULT : out unsigned ( (A_port_size+B_port_size-1) downto 0)); attribute mult_style: string; attribute mult_style of multipliers_2: entity is "pipe_lut"; end multipliers_2;

VHDL-VHDL architecture beh of multipliers_2 is signal a_in, b_in : unsigned (A_port_size-1 downto 0); signal mult_res : unsigned ( (A_port_size+B_port_size-1) downto 0); signal pipe_1,pipe_2,pipe_3 : unsigned ((A_port_size+B_port_size-1) downto 0); begin mult_res

VHDL-VHDLprocess (clk)begin if (clk'event and clk='1') then a_in

VHDL- PLD PLDPLD

VHDL- Synchronization

VHDL- 5.1.1a ; ,

VHDL- 5.1.1a

VHDL- 5.1.1bRiRf

VHDL- : 1; 2

VHDL- 1 2

VHDL- 3 4

VHDL- 1

VHDL- 2 3

VHDL- 1

VHDL- FPGA 2

VHDL- 3 D 4

VHDL- setuphold

VHDL- FIFO > >b_clka_clkdata_datb_dat11b_dat2 >b_dat1a_datb_dat2

VHDL- Chain ArchitectureTree Architecture3-73-34

VHDL-ifcase ifcase ifcase if-elseif -else casecase

VHDL-ifcase ififif ifcase

VHDL- VHDL

VHDL- 3-103-10 y

VHDL- 3-11always

VHDL-Process(w,x,y,z,in1,in2) Begin if(w=0) then if(x and (not(y and z))) then out

VHDL- z=0if (!w) out

VHDL-emp = y and z; Process(w,x,y,z,in1,in2) Begin if(temp=0) then if(x and (not w)) then Out

VHDL-if 3-12ifelse Process(a,data) Begin If(a=1) then data_out

VHDL-if3-12if,elseProcess(a,data) Begin If(a=1) then data_out

VHDL-case 3-13processcaseothersVHDL Process(a,data_in1,data_in2)begin case a is when 00=> data_out data_out; end case;end process;

VHDL-case3-13processcaseothersVHDL Process(a,data_in1,data_in2)begin case a is when 00=> data_out data_outdata_out

VHDL- 1 2

VHDL- 3 FIFORAM

VHDL- 4 HDLFPGAPC

VHDL- 5

VHDL-IP FPGA EDAIPintellectual PropertyIP 1 2FPGA 3IP

VHDL-IP IPIntelligent PropertySOCIPASICFPGA FPGAIPIP

VHDL-IP IP3IP

VHDL-IP() EDARTLFPGAIP

VHDL-IP() EDAFPGARTLRTLIP

VHDL-IP() EDAFPGA IP

VHDL-IP IPRTLIPEDAIP 1IPRTL 2IP 3IP

VHDL-RTLIP EDARTLIPIPRTLIP EDAIPRTLEDAIPNDAnondisclosure agreements IPEDAIP

VHDL- -RTLIP AlteraXilinxFPGARTL

VHDL-IP EDALUT/CLBIPEDIFPLDIP EDAIPPLD

VHDL--IP EDALUT/CLBIPIPLUTCLBIPPLDI/O

VHDL- IP FPGAIPEDAIPIP IPIP/IPIPFIFOIPIP/ NDARTL

VHDL- IP

VHDL- IP(DCM) Digital Clock ManagerDCMXilinxDLLDelay Locked LoopDCMDLL DCMDCM Skew PCBDCM/

VHDL- IP-DCM

VHDL- IP- XilinxDLL4-111 CLKINDLLIBUFGBUFG CLKFBDLLCL K0CLK2XIBUFGBUFG RSTDLL CLK0CL KINCL K90CL KIN 90CL K180CL KIN 180

VHDL- -IP- CLK270CL KIN270 CLKDVDLLCLKINDLL1.522.53458 16 CLK2XCLKIN2 LOCKEDDLLDLLLOCKED

VHDL- IP-DCM DCM DLL DFSDigital Frequency Synthesizer DPSDigital Phase Shifter DSSDigital Spread Spectrum

VHDL--DLL DLLCLKINCLKFB,DLL

VHDL- DFS- DFSCLKFBCLKFX1801.5320 MHzCLKFX_ MULTIPLYCLKFX_ DIVIDE:CLKFX_MULTIPLY = 3CLKFX_DIVIDE = 1PCB100 MHzDCM 3300 MHzFPGA

VHDL- DCMI/O0901802701%50 ps DCMPHASE_SHIFTPS-255+255200 MHz+ 0.9 nsPS =0.9ns/ 5ns256 = 46PHASE_ SHIFTCLKINPHASE_SHIFTCLKIN

VHDL- XilinxEMIFPGAEMI ControlDSSDSSEMIFCC

VHDL- IP-RAM Xilinx16RAMROMFIFOXilinxFPGA16* 1

VHDL-IP-RAM Xilinx FPGARAMCLBRAMRAMSpartan 3ERAMCLB4-120

VHDL- IP-RAM

VHDL- IP-RAM RAMFPGAXilinx FPGARAMCLBISEIPRAMRAMRAMRAMROMRAMFIFO4-121RAMRAM

VHDL- IP-RAM RAM4-122CLKWEENRAMSSRADDRDIDO

VHDL- IP-RAM

VHDL- IP-RAM RAMRAMRAMRAMRAM1/2RAMread-during-writeRAM

VHDL- IP-RAM RAM4-123RAMRAMPseudo Dual Port RAMRAM RAMRAMRAMwrenrdenrden RAM

VHDL- IP-RAM

VHDL- -IP-RAM RAM4-124ABWEAWEB

VHDL- -IP-RAM RAM MiroBlazeDMARAMRAMDMARAMRAMDMA

VHDL- IP-RAM RAMRAM36*512RAMRAMABRAMAB1/2

VHDL- IP-RAM

VHDL- IP-ROM RAMROM.coeROMROM

VHDL- IP-FIFO FIFO4-125FIFORAMRAMRAMFIFOFULLEMPTYFULLFIFOEMPTYFIFO

VHDL- -IP-FIFO

1 2 3 4 5 6IFCASE

5

7IFCASE 8 9IP 10IP 11IP

5

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何宾 2008.09

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