3 d integration for soi pixel detector
DESCRIPTION
T-Micro. 3 D Integration for SOI Pixel Detector. Makoto Motoyoshi (T-Micro). Contents. 1. Motivation Device target 2. Technologies and issues SOI Pixel detector process flow Yield process issues and counter measurements 3. Cost down technique of 3D stacking - PowerPoint PPT PresentationTRANSCRIPT
M. MotoyoshiCopyright © T-Micro Co., Ltd. All rights reservedPIXEL2012 Sept.03,2012 @Inawashiro
3 D Integration for SOI Pixel Detector
Makoto Motoyoshi
(T-Micro)
T-Micro
M. MotoyoshiCopyright © T-Micro Co., Ltd. All rights reservedPIXEL2012 Sept.03,2012 @Inawashiro 2
Contents
1. Motivation Device target
2. Technologies and issues SOI Pixel detector
process flow
Yield
process issues and counter measurements
3. Cost down technique of 3D stacking
4. Summary
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Realize High Speed Parallel Processing Pixel Sensor with Memory
Target of our 3D technology
32 x 32 pixels
6M/4096(5859)pixel arrays
1024 pixel data (serial)5859 parallel dataADCDec
Pixel array(BSI type)
DecoderAD Converter
Memory Array
32 x 32 x 12 (12288k)n
1024x12 bit data (serial)5859 parallel data
(0,3)(0,2)(0,1)(0,0)
DSP
1. Motivation
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1. Motivation
TSV and μ-bump technology with the pitch less than 5μm
Target 3D Technology
- Via last process
- Interconnect density 104~105/cm2
- Area penalty ≤1 %
- Good manufacturability (high yield, reliability)
- Low process temperature
- Low cost
108
107
106
105
104
103
Nu
mb
er
of
TS
V (
cm
-2)
10%5%
1%
TSVarea ratio
TSV diameter =TSV pitch x 1/2
TSV pitch (um)
RC Delay
0 2 4 6 8 10 120
5
10
15
20
RC
De
lay
(fs
)101
100
10-1
10-2
10-3TS
V l
en
gth
, d
iam
ete
r (
m) length
diameter
M. Koyanagi et al., IEEE Trans. Electron Devices, VOL.53, NO.11, pp.2799-2808, 2006
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5
Stacked SOI Pixel detector
n--
p+
n+
Si sensor(high resistivity Substrate)
BOX(lower tier)
+ -+ -
+ -
+ -
+ -
+ -+ -
BOX(upper tier)
Bond Pad
Metal interconnectBump junction
buried p-well
Back gate electrode
Charged Particle
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(b) µ-bump forming
(c) Chip bonding
Si
Si
Upper tier
Lower tier
adhesive
Process flow (1)
Active Si~50 nmBOX:200 nm
(a) Start with FD-SOI device wafer
*FD: Fully Deplete d
< Lower Tier >
Si
BOX
< Upper Tier >
Si
BOX
M3M2
M1MOST
µ-bump
Si
µ-bump
Si
M4
MOS Tr
High R-Si
High R-Si
High R-Si Si
Si
Si
-face to face infrared alignment-temporary bonding-Adhesive injection-permanent bonding (<200 )℃
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SOI pixel detector Chip
10µm
Detector Array
In μ-bump
(After forming u-bump)
Upper tier
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Selection of Wafer/Chip bonding technology
Polymer adhesive bonding SiO2 fusion bonding Metal fusion bonding
Adhesive
Si
Si
SiO2
Si
Si
Si
Si
Metal μ-bump
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1. Motivation
Bumping (Pb/Sn, Au, In)Metal eutectic bonding
Cu/Sn bump
Si
Si
Selection of Wafer/Chip bonding technology (2)
Metal bump
Si
Si
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Yield model
Yield Model of LSI
Y= Y0 ・ Y1(D0, A, α) Y0 : Systematic yieldY1 : The fraction of chip sites without process related effects and circuit sensibilityA : Chip AreaD0 : Density of defectsα : Distribution parameter of defects
Defect source - dusts or other particles in the environment, solution, process chamber in the production equipment - pattern defects due to ununiformity of material - oxide defects caused by process damage - statistical factor etc.
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Yield model
Y1 = exp (-D0A)
Y2=1-exp(-D0A)
D0A
2
1-exp(-2D0A)2D0A
Y3=
Yn : The fraction of chip sites without process related effects and circuit sensibilityA : Chip areaD0 : Density of defects
F(D)
D02D0
F(D)
D02D0
F(D)
D02D0
1(1+SD0A)1/sY4=
F(D)
D02D0
S0
S=0.1S=1.0
S: shape parameter
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Y=exp(-D1A)
Y=1
( 1+D0
A )
Yie
ld
Chip Area
Initial manufacturing
Yield Prediction
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1. Motivation
S/D S/D S/D S/D S/D S/D
dusts or particles
S/D S/D S/D S/D S/D S/D
Oxide CVDCMPVia patterningForm metal interconnect
No failureNo failure or reliability problem failure
Yield and reliability
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1. Motivation
S/D S/D S/D S/D S/D S/D
dusts or particles
S/D S/D S/D S/D S/D S/D
Oxide CVDCMPVia patterningForm metal interconnect
No failureNo failure or reliability problem failure
Yield and reliability
We can only detect this failure from electrical testing.
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1. Motivation
S/D S/D S/D S/D S/D S/D
dusts or particles
S/D S/D S/D S/D S/D S/D
Oxide CVDCMPVia patterningForm metal interconnect
No failureNo failure or reliability problem failure
Upper Chip
Lower Chip
If the bonding method which needs microscopic smoothness and cleanliness, bonding yield will be affected by defect density of dusts and particles.So we have chosen the bump bonding with adhesive injection.
In case of bonding wafer/chip on wafer /chip surface with dust,
Yield and reliability
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Wafer or Chip Alignment Temporary Bonding Adhesive Injection
Wafer Bonding Method (Tohoku University/T-micro)
dustSi
Si
Si
Si
Si
Si
Bump size (~μm) >>dust or particle size (≤0.2μm)
Adhesive
1. Motivation
In μ-bumps do not have enough mechanical strength, so the combination use of adhesive is indispensable.
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SOI pixel detector Chip
Detector Array /Peripheral Circuits
After Si removal
Voids
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(e) Pad patterning and passivation
(d) Bulk-Si removal
Back gate adjust electrodePassivationBond Pad
Si
High R-Si
High R-Si
Process flow (2)
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Void
Void
Void
Void
Void problem
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(a) Simple test device
(b) Circuit test device
Peripheral circuitDetector array
Si-sub
interlayer
Passivation layer Top metalTop metal
Bump connection
adhesivevoid
Uniform pressure changenon-uniform pressure change
Top metal
voids
Uniform pressure change
Bump connection
adhesive
Upper tier
Lower tier
No void in pixel array
20
Mechanism of void formation (1)
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Scribe line Injection line
Chip area
Chip area
Chip area
Chip area
Adhesive flow speedPumping action > capillary action
21
Mechanism of void formation (2)
F1
F2
F3
F4
F5
F1, F3, F5 > F2, F4
Void
Void
Pumping action < capillary action
Injection line
Chip area
Chip area
Chip area
Chip area
F1, F3, F5 < F2, F4
F1
F2
F3
F4
F5
Void
Void
Void
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Chip area Adhesive flow rateF1
F2
F4
F1, F4 > F2, F3
Mechanism of void formation (3)
High density bump area
F3Void
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Void
Pixel detector chip after Si removal
Void
Void
(a) before improvement (b) after improvement
23
Optimize - bump layout - differential pressure of adhesive injection - process temperature (control the viscosity of adhesive) - wettability of adhesive
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upper left corner
left lower corner
upper right corner
right lower corner
after Si removal
Finished Chip
A pattern (5mm x 5mm) B pattern (5mmx 5mm )
Two types of pixel detector chip
24
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Cross sectional SEM image of pixel array
UT
LT
M1(LT)
M2(LT)
M3(LT)
M4 (LT)
M4(UT)
M3(UT)
M2(UT)
M1(UT)
BOX(LT)
Adhesive
Back gate Metal MOS Tr BOX(UT)
In bump
5μ m
UT: upper tierLT: lower tier
25
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Poor wettability
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2.0μm
Al5%Cu
In
Ti
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0.01
0. 1
1.0
In In/Cu
Bu
mp
Re
sis
tan
ce (
Ω)
2 x 2 um x 2440 bump daisy chain
In bump vs In/Cu bump
10000
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Summary-Technology selection chart
Wafer/chip bonding
Combining Adhesive injection
Overcome weak mechanical strength
Process issuesVoid
Chip shift
Stacked SOI Pixel Detector
SiO2 fusion bonding
metal fusion bonding
metal eutecticbonding
Bumping Polymer adhesivebonding
Cu/Sn Pb/Sn Au InCu
Manufacturability
Bumping
Low processtemp.150~200℃
In
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Prototype of 8” Self-Assembled Chip Bonder
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Simultaneously picked-up 500 chips (5mm×5mm)
Liquid array onan 8-inch wafer
A large number ofself-assembled chips
Hydrophilic bonding area
KGDs
KGDs
Chip release Self-assembly
Liquid on hydrophilicarea formed on the wafer
Self-assembled KGDs
Liquid
KGD
180mm
50mm
150mm
Self-Assembly Process with 8-inch Wafer
Multi-chip pick-up plate
Alignment accuracy: ~ 400 nm
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200 mm図4 試作製造装置で多数のチップを仮接着したウェーハの全体写真
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Conclusion
- 3D LSI Integration technology using minimum 5μm pitch bump is verified using SOI stacked pixel detector as circuit level test
device.
- In this technology, adhesive injection is found the key technology. Optimizing layout, process parameter and adhesive injection method, this process have completed without void.
- The dispersion of bump resistance is still high, the following optimization are still ongoing.
Improvement of wettability between bump and pad Introducing the new Cu/In IMC bonding
- In further development of wafer /chip bonding with few μm pitch bump , it might be necessary to optimize the gap between tiers and volume of bump metal.