r&d for a monolithic pixel sensor based on 150 nm soi cmos...

VCI2007 T. Tsuboyama, 21 Feb. 2007 1

R&D for a monolithic pixel sensor based on 150 nm SOI CMOS technology

11th Vienna Conference on Instrumentation 21 Feb. 2007

T. Tsuboyama (KEK)for the SOIPIX collaboration

VCI2007 T. Tsuboyama, 21 Feb. 2007

OutlineIntroduction2005 designs and preliminary results2006 designsEffect of radiation and back-gate voltage.Summary

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SOIPIX collaborationKEK: Y. Arai(*), M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, Y. UshirodaJAXA: H. IkedaNiigata Univ.: T. KawasakiOKI Elec. Ind. Co.: K. Fukuda, H. Hayashi, J. Ida, H. Komatsubara, M. OhnoSLAC: Hiro TajimaTokyo Institute of Technology: H. Ishino ,Y. Saegusa, T. TakahashiTsukuba Univ.: K. Hara, H. Miyake, A.MochizukiUniv. of Hawaii: Gary Varner, Elena Martin (* contact person)


ParticleDetector

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Pixel sensorsHybrid pixel sensors

Proved in LHC experiments.MEDIPIX: Extended applications to material and biology imaging.

Monolithic pixel sensorThe radiation detector and readout electronics are integrated in a single wafer.Free from the difficulties in the bump-bonding technology.Thinning could reduce material significantly.

MAPS: Monolithic Active Pixel Sensor Similar to commercial CMOS camera.Epitaxial layer is used as radiation detector.

SOI: Silicon on insulator Pioneering work has been done by SUCIMA project.Independent R&D started in 2005 at KEK

MAPS

SUCIMA SOI pixel

Pixel

Sensor

ASIC

bumpbonding

Hybrid


SOI CMOS technologyStructure:

Low-resistivity silicon layer (for MOSFET)Buried oxide layer (BOX)Silicon substrate (support wafer)

MOS FETs are isolated from the substrate and from each other.

Low stray capacitance: Faster operationNo parasitic transistors: Latch-up free.Insensitive to charge induced in the substrate: Rate of “single event” effect is significantly reduced.

SOI wafer and process is becoming a standard technology in the semiconductor industry.

Si Substrate

Gate

MOS


SOI CMOS technologyStructure:

Low-resistivity silicon layer (for MOSFET)Buried oxide layer (BOX)Silicon substrate (support wafer)

MOS FETs are isolated from the substrate and from each other.

Low stray capacitance: Faster operationNo parasitic transistors: Latch-up free.Insensitive to charge induced in the substrate: Rate of “single event” effect is significantly reduced.

SOI wafer and process is becoming a standard technology in the semiconductor industry.

Si Substrate

Gate

MOS

BOX


1st metal

2nd metal

3rd metal

MOSFETBuried oxide

Gate

OKI 150 nm SOI CMOS process

http://www.okisemi.com/english/soi.htm

Process0.15µm Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers, MIM capacitor

SOI wafer (SOITEC)

Diameter: 150 mmφ, Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thick Buried Oxide: 200 nm thickHandle wafer: Cz>1k Ω-cm, 650 µm thick

BacksideThinned to 350 µm, plated with Al (200 nm) after the semiconductor process.

Photo of 200-nm SOI

1 µm


Substrate contact

7

1st metal layer

Box

Implant region

Plug

SOI wafer

Sensor structure is made below BOX. Remove the BOX layer where implant is necessary.Inject ions to form p+ or n+ regions.Fill back the aperture with SiO2.Make a via hole.Fill the hole with contact plug.Bias can be applied to substrate and thicker depletion region can be obtained.This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. MeritsThinning can be applied.Standard and up-to-date SOI CMOS technology can be used.


Substrate contact

7

1st metal layer

Box

Implant region

Plug

SOI wafer

SiO2




Substrate contact

7

1st metal layer

Box

Implant region

Plug

SOI wafer

SiO2

SiO2




List of 2005 TEG

Name

AMPTEG Preamp, Time over threshold, comparator, active feed back etc.

RADTEG Pixel, transistor, ring oscillator

PIXTEG 32x32 pixel array with readout

STRIPTEG Short strip sensor

HAWAIITEG Hard X-ray compton polarimeter


Strip TEGDC coupled strips without active circuit is designed to measure basic characteristics of the sensor part.The 2.5 x 2.5 mm2 chip is divided into eight regions with different strip width.Breakdown voltage: ~50V.

Far less than the expected full depletion voltage (200 V).An infrared camera revealed the breakdown takes place at guard ring.Breakdown voltage could be improved by guard ring design.

The charge collection efficiency is not saturated at the breakdown voltage.


Laser

Light injection window

Laser scanFocused IR Laser (λ=980 nm) is injected from the top surface.Beam spot size ~ 10 um. There are windows for light injection.

Reasonable charge collection, separation and share between strips are confirmed.When laser spot hits the readout metal traces, the observed charge decreases.


Pixel TEGPurpose: demonstrate the potentiality of SOI as a pixel radiation sensor.32x32 cells of 20x20 µm2 pixel matrix.In each pixel, four octagonal implants (4x4 µm2) collects charge from the substrate.Breakdown voltage ~100V.Operation ~ 10 V to reduce back-gate effect.


Readout circuit.

Each channel is equipped with a circuit consists of 7 FETs.Doubly correlated sampling, similar to readout circuit for MAPS.

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Reset

Integrate charge

Readout

Sample/Hold


Evaluation with laser light“KEK06” image by a 670 nm laser light.

Graph: Readout channel is changed every 12 µsec then reset is given and go to the next channel.The ramp up speed depends on the light intensity. Fully illuminated cells saturate in 3 µsec. The slope is consistent with the light intensity and the calculated detector capacitance.


Observation ofβray signalThe pixel chip is irradiated with a 90Sr βray source.Output voltage of one channel is observed with oscilloscope.Observed voltage jump corresponding to a particle hit.The voltage step is consistent with charge from a MIP.=dE/dx(MIP) x depletion depth (44 um) x circuit response.

90Sr sourcePixel sensor


17 designs were submitted Dec. 20062006 TEG designs

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List of submitted designs

16

CHIP Name Size (mm2) Category Designers

VARPIXEL 2.4 x 2.4 Measurement H. Miyake (Osaka Univ. --> Tsukuba Univ.)

TOPPIXN 2.4 x 2.4 Pixel Y. Arai (KEK)

OKI0612 2.4 x 2.4 Measure H. Takahashi, K. Shimazoe, Fuiwara (Tokyo Univ.)

Achip 2.4 x 2.4 Pixle P. Denes (LBL)

OKI_TOP 2.4 x 2.4 Pixel G. Deptuch (FNAL (BNL))

ATEG 2.4 x 2.4 Circuit H. Ikeda (JAXA/ISAS)

BTEG 2.4 x 2.4 Circuit H. Ikeda (JAXA/ISAS)

CTEG 2.4 x 2.4 Circuit H. Ikeda (JAXA/ISAS)

isas_set0612 2.4 x 2.4 Measurement D. Kobayashi (JAXA/ISAS)

RADFET1 2.4 x 2.4 Measurement T. Tsuboyama (KEK)

HawaiiNSUBSTRATE 5.0 x 5.0 Pixel E. Martin G. Varner (Univ. of Hawaii)

detectorPOLY 5.0 x 5.0 Measurement T. Tsuboyama (KEK)

TOP_PIXELSTRIP 5.0 x 5.0 Strip Y. Ikegami (KEK)

TOP_8PREAMP 5.0 x 5.0 Circuit Y. Arai, Y. Ikegami (KEK)

TOPTEG2 5.0 x 5.0 Measurement Y. Arai (KEK)

TOPINTPIX 5.0 x 5.0 Pixel Y. Arai (KEK)

TOPCOUNT 10.2 x 10.2 Pixel Y. Arai (KEK)


Count-pixel Array of 128x128 pixels Pixel size: 50x50 µm2.Chip size: 10x10 mm2.Active area: 6.4x6.4 mm2.

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Y out

ResetSelectCsr X

X out Write

Data

CSR

16-bitCounter

16

9

+Vdet

Test in

Vth-H

Vth-L

DDL

Count-pixel

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Inspired by MEDIPIX2 readout chip.Target: X ray imaging.

Each pixel is equipped with a shaping amplifier with leak current compensation.a window comparator.a 16-bit counter

Count the number of hits entering the pixel.The counter is read out after an arbitrary integration period.Each pixel consists of ~600 FETs. Total 10 Mega FETs in a chip.


Strip-pixelIn ILC and B factory vertex detectors, reduction of material thickness per silicon layer is preferable.At large radius, the occupancy is not an issue.Thinned monolithic sensor is a solution.Adding signal from several pixels, a pseudo strip sensor can be made.As signal from a pixel is smaller than that from fully-depleted sensors, amplifier is integrated to each pixel.

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Pixel+amp

Pixel+amp

Pixel+amp sum buffer

Pixel+amp

Pixel+amp


Pixel+amp

Pixel+amp


x0

x1

x2

sumbuffer

y0

sumbuffer

y1

sumbuffer

y2


Radiation damage and back-gate effect

Radiation damage in CMOS FET: Positive charge trapped in the oxide layer results in the threshold shift of the FET.150-nm technology CMOS FETs are usually radiation hard.The gate-oxide is enough thin.

SOI CMOS: BOX layer below FETs affects the threshold voltage.Back-gate effect: the electric potential of the substrate causes threshold shift.

Substrate

BOX

MOSFETSiO2

Gate2.5 nm

200 nm


Measurement with RADTEGThe Id-Vg curves:Before irradiationAfter irradiation of 2x1013 proton/cm2

Substrate voltage is varied -30 to 0 V.

Threshold shift due to irradiation can be cured with the substrate voltage.Comparison with TCAD simulation.

NMOS_LowVt_L/W=0.15/300

-2.00E-04

0.00E+00

2.00E-04

4.00E-04

6.00E-04

8.00E-04

1.00E-03

0 0.2 0.4 0.6

Vgs(V)

Id(A)

float

pre-irrad_backgate=0

backgate=-30

backgate=-20

backgate=-10

Vg (V)

NMOS_LowVt,L/W=0.15/3001.0

0.8

0.6

0.4

0.2

0.0

Id (m

A)


TCAD simulationReduce risks, time and costs of silicon process.

Silvaco: ATHENA/ATLAS (2-dimensional)Enexss (Japan made, 3-dimensional)

Proceeding with careful comparison of two system.


Reduction of back gate effect

BOX

Bulk: n- (~700 Ω cm, 6 x 1012 cm-3)

Bias ring: (5 µm wide P+, 1 x 1020 cm-3)

distance (80, 5, 2 µm)

Backbias (0-100 V)

350µm

200 nm

Studied with Enexss TCADBack gate effect can be reduced by guard ring in the substrate.The threshold voltage of FETs is calculated with a guard ring at distance of 2, 5 and 80 µm.At 2 µm, the threshold shift can be suppressed to 0.1 V at bias voltage of 100 V.Such structure is implemented in the 2006 designs.

Preliminary

FET


SummaryR&D activity of SOI pixel sensor started in 2005.Evaluation of 2005 design TEGs.

Observed signal from sensors as expected.Effects of charge accumulation in BOX and potential of support wafer.Behavior is understood quantitative with TCAD.

Example from 2006 TEG chips.Schedule of 2007: Evaluation of 2006 chips.Study of thinning.Autumn: Submission of 2007 designs.


KEK detector technology project (2005-)Several detector R&D groups are organized independent of the physics projects

Result should be applicable not only for particle physics but also various fields

SubgroupsNovel photo sensor /MPPCGEM/MPGDASICSOI pixelLiq, Xe calorimeter

http://rd.kek.jp/

http://rd.kek.jp

http://rd.kek.jp

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