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Status of SOI Pixel

Mar. 18, 2009@SuperBell PXD Mtg.

Yasuo Arai (KEK)yasuo.arai@kek.jp

http://rd.kek.jp/project/soi/

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Recent Progress

• Second 0.2um SOI MPW run was submitted on

February.

'SVD Amp/Memory' by Piotr Kapusta

'Vertical Integration Test' by LBNL/KEK

• LBNL Fine Analog SOI Pixel Result

• Second 0.2um SOI MPW run was submitted on

February.

'SVD Amp/Memory' by Piotr Kapusta

'Vertical Integration Test' by LBNL/KEK

• LBNL Fine Analog SOI Pixel Result

Feb. 2009 Submissin

preamp: output range +- 0.6V, input +-10MIPshaper: peaking time ~20nspipeline: differential analog memory controlled by shift registerfifo: separate analog memory with digital pointers controlclk: 40MHz clockpower supply: 0, -2.2V

preamp: output range +- 0.6V, input +-10MIPshaper: peaking time ~20nspipeline: differential analog memory controlled by shift registerfifo: separate analog memory with digital pointers controlclk: 40MHz clockpower supply: 0, -2.2V

Piotr Kapusta (Institute of Nuclear Physics, Krakow)

R&D of Amp/Memory chip for SVD with SOI technology

SOI SVD ampfor Super Belle2.4 x 2.4 mm2

SOI SVD ampfor Super Belle2.4 x 2.4 mm2

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LDRD-SOI-1 LDRD-SOI-1 Analog Pixels: Resolution Analog Pixels: Resolution

Determine analog pixel spatial resolution by scan with pulsed1060 nm laser focused on ~5m spot;

Change laser power to simulate different cluster S/N conditions;

Reconstruct position using charge center-of-gravity; SOI analog 10 m pixels demonstrate ~ 1 m resolution

m.i.p.

MB et al.to appear on NIM

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•Higher Functionality in each pixel.

•Increase of material budget is minimum.

•Higher Functionality in each pixel.

•Increase of material budget is minimum.

ZyCube + OKI + KEK/LBNLZyCube + OKI + KEK/LBNLVertical IntegrationVertical Integration

Use ZyCube -bump bonding (~5 um pitch) technique.Use ZyCube -bump bonding (~5 um pitch) technique.

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Vertical IntegrationVertical Integration

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Lower Chip Upper Chip

Vertical IntegrationVertical Integration

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Summary

• 2nd SOI MPW run was submitted last month

• First test circuit for the SupeBelle SVD amp/memory chip was submitted.

• Position resolution of 1 um is demonstrated by LBNL.

• We are also developing vertical integration technology which increase the functionality of the pixel.

• 2nd SOI MPW run was submitted last month

• First test circuit for the SupeBelle SVD amp/memory chip was submitted.

• Position resolution of 1 um is demonstrated by LBNL.

• We are also developing vertical integration technology which increase the functionality of the pixel.

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