of 15. unit i 8085 architectu re

Unit I

8085 Architecture

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8086 Architecture


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8085 PIN AND SIGNAL


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8086 PIN AND SIGNAL

The 8086 can operate in two modes these are the minimum mode and maximum mode .For minimum

mode, a unique processor system with a single 8086 and for Maximum mode a multi processor system

with more than one 8086.

MN/MX- is an input pin used to select one of this mode.

when MN/MX is high the 8086 operates in minimum mode .In this mode the 8086 is configured to

support small single processor system using a few devices that the system bus .

when MN/MX is low 8086 is configured to support multiprocessor system.

The AD0-AD15 lines are a 16bit multiplexed addressed or data bus. During the 1st clock cycle AD0-

AD15 are the low order 16Bit adders. The 8086 has a total of 20 address line ,the upper 4 lines are

multiplexed with the state signal that is A16/S3 , A17/S4 , A18/S5 , A19 /S6.

During the first clock period of a best cycle the entire 20bit address is available on these line. During

all other clock cycles for memory and i/o operations AD15-AD0 contain the 16 bit data and

S3,S4,S5,S6 become the status line .S3 and S4 are decoded as follows

A17/S4 A16/S3 Function 0 0 Extra Segment

0 1 Stack Segment

1 0 code or No segment

1 1 Data Segment

There for the 1st clock cycle of an instruction execution the A17/S4 And A16/S3 pins Specify which

Segment register generate the segment portions of the 8086 address

BHE/S7 is used as best high enable during the 1st click cycle of an instruction execution .the BHE

can be used in conjunction with AD0 to select the memory

RD is low when the data is read from memory or I/O location .

TEST is an input pin and is only used by the wait instruction .the 8086 enter a wait state after

execution of the wait instruction until a low is Sean on the test pin.

INTR is a maskable interrupt input.

NIM is the non maskable interrupt input.

RESET is the system set reset input signal it terminates all the activities it clear PSW,IP,DS,SS,ES

and the instruction Queue.

DT/R(Data Transmit or receive ):is an o/p signal required in system that uses the data bus transceiver


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ALE is an address latch enable . Is an o/p signal provided by the 8086 and can be used to

demultiplexed AD0 to AD15 in to A10 toA15 and D0 to D15.

M/IO is an 8086 output signal to distinguish a memory access and i/o access.

WR is used by the 8086 for performing write memory or write i/o operation .

INTA(interrupt acknowledgement signal )

INTA is the interrupt acknowledgment signal

HOLD and HOLDA a high on the HOLD pin indicates that another master is required to take over the S/M bus

CLK clock provides the basic timing signals for the 8086 and bus controls.

8085 Timing Diagram

Timing diagram for Opcode fetch

The process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4

and is the 1st machine cycle (M1) of every instruction.

Fetch a byte 41H stored at memory location 2105H. For fetching a byte, the microprocessor

must find out the memory location where it is stored. Then provide condition (control) for data flow

from memory to the microprocessor. The µP fetches opcode of the instruction from the memory as per

the sequence below

A low IO/M means microprocessor wants to communicate with memory.

The µP sends a high on status signal S1 and S0 indicating fetch operation.

The µP sends 16-bit address. AD bus has address in 1st clock of the 1st machine cycle, T1.

AD7 to AD0 address is latched in the external latch when ALE = 1. AD bus now can carry data. In T2,

the RD control signal becomes low to enable the memory for read operation.

The memory places opcode on the AD bus. The data is placed in the data register (DR) and then it is

transferred to IR. During T3 the RD signal becomes high and memory is disabled.

During T4 the opcode is sent for decoding and decoded in T4. The execution is also completed

in T4 if the instruction is single byte. More machine cycles are essential for 2- or 3-byte instructions.

The 1st machine cycle M1 is meant for fetching the opcode. The machine cycles M2 and M3 are

required either to read/ write data or address from the memory or I/O devices.

Opcode fetch MOV B,05H.

The MVI B,05H instruction requires 2-machine cycles (M1 and M2). M1 requires 4-states and

M2 requires 3-states, total of 7-states as shown in Fig. 5.3 (d). Status signals IO/M, S1 and S0

specifies the 1st machine cycle as the op-code fetch. In T1-state, the high order address {10H} is

placed on the bus A15 ⇔ A8 and low-order address {00H} on the bus AD7 - AD0 and ALE = 1. In T2

-state, the RD line goes low, and the data 06H from memory location 1000H are placed on the data

bus. The fetch cycle becomes complete in T3-state. The instruction is decoded in the T4-state.

During T4-state, the contents of the bus are unknown. With the change in the status signal, IO/M = 0,

S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the memory read. The address is 1001H and


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the data byte [05H] is fetched via the data bus. Both M1 and M2 perform memory read operation, but

the M1

is called op-code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode fetch

cycle. Execution time for MBI B,05H i.e., memory read machine cycle and instruction cycle is

MVI B,05H Opcode Opcode Fetch 4

Immediate Data Read Immediate Data 3

Clock frequency of 8085 = 3.125 MHz

Time ( T ) for one clock = 1/3.125 MHz = 0.32 µS

Time for Memory Read = 3T = 3*0.320 µS = 0.96 µS

Total Execution time for Instruction = 7T = 7*0.320 µS = 2.24 µS


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of 15. unit i 8085 architectu re

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