BTSE

LinkInterface

SN LinkInterface

BSCControl

LMTOMC

BSC

SGSN

BTSETRAU

PCU

Fig. 1 BSC architecture (MN1780EU09MN_0001 BSC Architecture, 4)

BTSE

BTSE

TRAULink

InterfaceLink

Interface

SN-1BSC

SGSNLink

InterfaceLink

Interface

.

.

.

.

.

.

SN-0

Abis via PCMB

Asubvia PCMS

Gbvia PCMG

PCM30/24PCM30/24

Fig. 2 Asub, Abis and Gb interfaces (MN1780EU09MN_0001 BSC Architecture, 5)

TRAU

BSC

SGSN

.

.

.

.

.

.

Asub

Abis

LinkInterface

LinkInterface

SN-1

LinkInterface

LinkInterface

SN-0

3 2 1 0 3 2 1 0

4x16 kbit/sTraffic Channels

4x16 kbit/sTraffic Channels

Gb

Permanent VirtualConnection PVCin Frame Relay

(„64 kbit/s channelized“)

3 2 1 0

4x16 kbit/sPacket Data

Channels

Packet Control Unit

Fig. 3 BSC traffic channel switching (MN1780EU09MN_0001 BSC Architecture, 6)

BTSE

BSC TRAU MSC

LAPDLAPD

4x16 kbit/s TCH

CCSS 764 kbit/s

CCSS 764 kbit/s

1x16 kbit/s TCH

Abis Asub A

SGSNGb

BSS GPRS Protocol(over Frame Relay)

PCU

Fig. 4 SBS external and internal signaling (MN1780EU09MN_0001 BSC Architecture, 7)

BTSE TRAU

PCMB PCMS

Abis AsubPCMA

A

MSC

SGSN

PCMGGb

BSSGP

BSC

LPDLM&LPDLR LPDLS CCSS7

PCUUm

Fig. 5 Interfaces and signaling (MN1780EU09MN_0001 BSC Architecture, 8)

BTSE

BSC TRAU MSC

LAPDLAPD

4x16 kbit/s TCH

CCSS 764 kbit/s

CCSS 764 kbit/s

1x16 kbit/s TCH

Abis Asub A

Fig. 6 CCSS#7signaling (MN1780EU09MN_0001 BSC Architecture, 9)

BTSE

BSC TRAU MSC

LAPD

CCSS 764 kbit/s

CCSS 764 kbit/s

Abis Asub A

Not used

LAPD

Fig. 7 CCSS7 and LAPD signaling (MN1780EU09MN_0001 BSC Architecture, 10)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 8 B

SC

inte

rnal

arc

hite

ctur

e (M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 1

3)

BTSE

BTSE

LPDLM/R

TRAU

SGSNLineTermination

LineTermination

LineTermination

LineTermination

LAPD

CCS7

SwitchingNetwork

TelephonyProcessor

Peripheral Processors

LPDLS

CCS7

BSC

BSSGPPCU

BSSGP

BSSGP

Fig. 9 Switching network (MN1780EU09MN_0001 BSC Architecture, 15)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGPO

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 10

Per

iphe

ral p

roce

ssor

for

CC

SS

7 (M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 1

7)

Line Termination

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 11

Per

iphe

ral p

roce

ssor

for

LAP

D (

MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

18)

Line Termination

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeriphalProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 12

Tel

epho

ny p

roce

ssor

(T

DP

C, M

EM

T)

(MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

19)

Line Termination

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 13

Adm

inis

trat

ive

proc

esso

r (M

PC

C, U

BE

X)

(MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

21)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 14

Line

term

inat

ion

QT

LP (

MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

22)

QTLP

TRAU 1

TRAU 3

TRAU 2

BTSE 2

BTSE 1

BTSE 3

BTSE 4

Port 0

Port 1

Port 2

Port 3

A

A

A

A

B

B

B

B

Fig. 15 Mixed configuration of QTLP (ports 0 ... 2: transparent mode, port 3: selection mode) (MN1780EU09MN_0001 BSC Architecture, 23)

DK 40

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

DK 40

to OMC

to LMT

. . . PeripheralProcessors

Hard Disk

AdministrativeProcessor

UBEX

MPCC

Hard Disk

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 16

Har

d D

isk

(MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

24)

TRACE_CTR

TRACE_IMSI

SWH_DIR/RSUDB/0

SWH_DIR/RSUSWLH/2

SWH_DIR/RSUSWLH/1

SWH_DIR/RSUSWLH/0

REMINV

READY_MEAS

READY_CTR

BSC Event Log Files

Perform. Measurem. (active)

CTR Measurements (for upload)

Cell Traffic Records

IMSI Traces

And more . . .

BSC database

Remote Inventory Files

BSC software

BTSM software

TRAU software

Perform. Measurem. (for upload)

MEASURE_DIR

LOG

. . .

. . .

Fig. 17 System directories on Hard Disk (MN1780EU09MN_0001 BSC Architecture, 25)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processor

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 18

O&

M in

terf

ace

on IX

LT (

MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

26)

MSC

BTSE

BSC

LMT

IXLT

X.21/V.11

TRAU

SBS

Fig. 19 Connection BSC - LMT (MN1780EU09MN_0001 BSC Architecture, 27)

BTSE

BSC

IXLTTRAU

MSC

SIEMENSNIXDORF SIEMENS

NIXDORF SIEMENSNIXDORF

PSDNX.25 Line

nailed-upconnection

OMC-B

SBSNo transcoding

64 kbit/s

64 kbit/s

64 kbit/s

Fig. 20 Connection BSC - OMC (MN1780EU09MN_0001 BSC Architecture, 28)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPLD

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . . PeripheralProcessors

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 21

Clo

ck P

LLH

(M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 2

9)

SGSN

BSC

PCU

PCU tasks

• Management of GPRS radio resources• Protocol conversion (packet data interworking)• Tasks comparable to “classical” BSC• Remote (until now BTS tasks): PC, TA,...

Gb:standard interface

BTSE

Abis:proprietary

i/fi/f

Fig. 22 PCU functions (MN1780EU09MN_0001 BSC Architecture, 30)

BSC

PCU

PPCUPeripheral Packet

Control Unit

ProvidingService

PPCU

ColdStandby

PCU

PPCU

ProvidingService

PPCU

ColdStandby

max. 2 PCUs

cell 1

cell 2

cell 3

cell n· · ·

cell n+1

cell n+2

cell n+1

cell n+x· · ·

Fig. 23 PCU implementation with PPCU (MN1780EU09MN_0001 BSC Architecture, 31)

Cell A

Cell B

Cell C

Cell D

Cell E

Cell F

PPXU-0 PPXU-1 PPXU-2

• GPRS traffic is automatically distributed among (working) PPXU „well balanced“• in case of failure, packet traffic is automatically redistributed among the remaining PPXU (load sharing)

To SGSN

Fig. 24 Load sharing between PPXU (MN1780EU09MN_0001 BSC Architecture, 31)

Line TerminationQTLP

Line Termination

Line TerminationSwitchingNetwork

SNAP

Clock

PLLHLine Termination

Line Termination

Line Termination

BSSGP

PPXX

BSSGP

PPXX

BSSGP

PPXX

LAP D

PPXX

CCS 7

PPXX

MEMT TDPC

Telephony Processors

O&MInterface

IXLT

AdministrativeProcessor

UBEX

MPCC

to OMC

to LMT

. . .

TelephonySystem Bus

AdministrativeSystem Bus

AdministrativeExtended Bus

AdministrativeExtended Bus

QTLP

QTLP

QTLP

QTLP

QTLP

Fig

. 25

Bus

sys

tem

s (M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 3

2)

Lamp Panel

QTLP8

QTLP7

QTLP6

PPLD14

PPLD13

PPLD12

PPLD11

PPLD10

PPLD9

QTLP5

QTLP4

QTLP3

PPLD8

PPLD7

PPLD6

PPLD5

PPLD4

PPLD3

QTLP2

QTLPS1

PWRS1

PWRS0

PLLH0

QTLP1

PPCC1

PPLD1

PLLH1

QTLP0

PWRS1

PWRS0

QTLPS0

PPCC0

PPLD2

PPLD0

DK400

IXLT0

UBEX0

SN160

TDPC0

MEMT0

MPCC0

MPCC1

MEMT1

TDPC1

SN161

UBEX1

IXLT1

DK401

Expansion

Fuse and AlarmPanel

Base

Fig

. 26

BS

C r

ack

(BS

C "

clas

sic"

, with

out P

CU

) (M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 3

5)

Lamp Panel

QTLP8

QTLP7

QTLP6

PPCU0

PPCU1

PPCU3

QTLP5

QTLP4

QTLP3

PPCU2

PPLD6

PPLD5

PPLD4

PPLD3

QTLP2

QTLPS1

PWRS1

PWRS0

PLLH0

QTLP1

PPCC1

PPLD1

PLLH1

QTLP0

PWRS1

PWRS0

QTLPS0

PPCC0

PPLD2

PPLD0

DK400

IXLT0

UBEX0

SN160

TDPC0

MEMT0

MPCC0

MPCC1

MEMT1

TDPC1

SN161

UBEX1

IXLT1

DK401

Expansion

Fuse and AlarmPanel

Base

Fig

. 27

BS

C r

ack

(BS

C "

clas

sic"

, ful

ly e

quip

ped

with

PP

CU

) (M

N17

80E

U09

MN

_000

1 B

SC

Arc

hite

ctur

e, 3

6)

Lamp Panel

QTLP8

QTLP7

QTLP6

PPXX7

PPXX6

PPXX5

QTLP5

QTLP4

QTLP3

PPXX4

PPXX3

PPXX2

QTLP2

QTLPS1

EPWR1

EPWR0

PLLH0

QTLP1

PPXX0

PLLH1

QTLP0

PWRS1

PWRS0

QTLPS0

PPXX1

DK400

IXLT0

UBEX0

SNAP0

TDPC0

MEMT0

MPCC0

MPCC1

MEMT1

TDPC1

SNAP1

UBEX1

IXLT1

Expansion

Fuse and AlarmPanel

Base

Fig

. 28

BS

C r

ack

(BS

C H

igh

Cap

acity

1st

Ste

p) (

MN

1780

EU

09M

N_0

001

BS

C A

rchi

tect

ure,

37)

PWRS

0

PLLH

0

QTLP

1

QTLP

0

QTLP

S

PPCC

1

PPCC

0

PPLD

2

PPLD

1

PPLD

0

PLLH

1

PWRS

1

DK40

1

IXLT

1

UBEX

1

SN16

1

TDPC

1

MEMT

1

MPCC

1

MPCC

0

MEMT

0

TDPC

0

SN16

0

UBEX

0

IXLT

0

DK40

0

Fig. 29 DC power distribution in the base subrack (MN1780EU09MN_0001 BSC Architecture, 40)

PWRS

0

PLLH

0

QTLP

1

QTLP

0

QTLP

S

PPXX

1

PPXX

0

PLLH

1

PWRS

1

IXLT

1

UBEX

1

SNAP

1

TDPC

1

MEMT

1

MPCC

1

MPCC

0

MEMT

0

TDPC

0

SNAP

0

UBEX

0

IXLT

0

DK40

0

Fig. 30 DC power distribution in the base subrack (BSC High-Capacity 1st Step) (MN1780EU09MN_0001 BSC Architecture, 41)

QTLP

5

QTLP

4

QTLP

3

QTLP

2

QTLP

S

PPLD

8

PPLD

7

PPLD

6

PPLD

5

PPLD

4

PPLD

3

EPWR

1

EPWR

0

QTLP

8

QTLP

7

QTLP

6

PPLD

14

PPLD

13

PPLD

12

PPLD

11

PPLD

10

PPLD

9

Fig. 31 DC power distribution in the expansion subrack (no PCU, BSC "classic") (MN1780EU09MN_0001 BSC Architecture, 42)

QTLP

5

QTLP

4

QTLP

3

QTLP

2

QTLP

S

PPCU

8 7

PPLD

6

PPLD

5

PPLD

4

PPLD

3

EPWR

1

EPWR

0

QTLP

8

QTLP

7

QTLP

6 14 13

PPCU

12 11 10

PPCU

9

PPCU

15

Fig. 32 DC power distribution in the expansion subrack (2 PCU, BSC "classic") (MN1780EU09MN_0001 BSC Architecture, 43)

QTLP

5

QTLP

4

QTLP

3

QTLP

2

QTLP

S

PPXX

8 7

PPXX

6 5

PPXX

4 3

EPWR

1

EPWR

0

QTLP

8

QTLP

7

QTLP

6 14

PPXX

13 12

PPXX

11 10

PPXX

915

Fig. 33 DC power distribution in the expansion subrack (fully equipped with PCU, BSC HC 1st Step) (MN1780EU09MN_0001 BSC Architecture, 43)