Analog Integrated Circuits and Signal Processing, 27, 717, 2001C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands.

A New CMOS Buffer Amplifier Design Used in Low Voltage MEMS Interface Circuits

YAJUN HA,1, M. F. LI1 AND AI QUN LIU21Department of Electrical Engineering, National University of Singapore, Singapore 119260

2Institute of Materials Research and Engineering, 3 Research Link, Singapore 117602E-mail: yjha@imec.be; elelimf@nus.edu.sg

Received December 8, 1999; Accepted July 5, 2000

Abstract. To achieve low voltage high driving capability with quiescent current control, a class-AB CMOS bufferamplifier using improved quasi-complementary output stage and error amplifiers with adaptive loads is developed.Improved quasi-complementary output stage enables it more suitable for low voltage applications, while adaptiveload in error amplifier is used to increase the driving capability and reduce the sensitivity of the quiescent currentto fabrication process variation. The circuit has been fabricated in 0.8 m CMOS process. With 300 load in a1.5 V supply, its output swing is 2.42 V. The mean value of quiescent current for eight samples is 204 A, withthe worst deviation of 17%.

Key Words: CMOS buffer amplifier, MEMS, low voltage

Introduction

Buffer amplifier is an important building block inMEMS interface circuit design. It couples the pro-cessed signals from previous on-chip stages with highoutput impedance to off-chip loads as shown in Fig. 1.The buffer amplifier comprises two stages in our de-sign, namely input and output stages. The conceptualstructure of a buffer is shown in Fig. 2, where outputstage is further divided into two parts, the driver stage,and the output transistors MO1 and MO2. The inputstage of the buffer amplifier is realized by an opera-tional transconductance amplifier (OTA). The outputbuffers able to drive low impedance off-chip loads tovoltage near the power supply while achieving good lin-earity, low quiescent power dissipation and controlledbias have been extensively investigated in recent years.Buffers with class-AB configuration employing quasi-complementary output stage (as shown in Fig. 3(a))[1,2] is well-suited for meeting these demands, and hasbeen widely used. However, two of its inherent draw-backs make it less attractive when driving a heavy loadwith low voltage supply.

First, the open loop gain of the error amplifiers A andB in Fig. 3(a) cannot be too high, generally not more

Yajun Ha is now a Ph.D. candidate in IMEC, Belgium.

than 10 [2,3]. Otherwise, the quiescent current of theoutput buffer may has a large variation from the designtarget value due to random input offset voltage of theerror amplifier. This low open loop gain of error ampli-fier limits the driving capability of the buffer amplifier.

Second, almost all the previous error amplifiers aredesigned to work with power supply voltage of 5 V orhigher [27]. Under low power supply of 3 V or 1.5 V,when the common mode voltage Vo changes to one railof the power supply, one of the error amplifiers maynot work properly. Consequently, one of two outputtransistors will lose control of its gate voltage.

A new buffer amplifier (See Fig. 3(b)) is proposedin this work. To solve the first problem, the error ampli-fiers A and B use an adaptive load scheme introducedin [8] with further improvement. The adaptive load inerror amplifier is used to obtain an adaptive gain. In thequiescent state, the open loop gains of the error ampli-fiers A and B are very low to achieve stable quiescentcurrent. While in the driving state, the open loop gainsof the error amplifiers will be changed to very high so asto get an improved driving capability. To solve the sec-ond problem, the proposed new quasi-complementaryoutput stage uses two differential-output error ampli-fiers (as shown in Fig. 3b). Amplifier A uses p-MOSinput transistor pair while amplifier B uses n-MOS in-put transistor pair. When Vo in Fig. 3(b) changes to

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Analog SignalProcessing

Buffer

load

Input Output

On-chip Off-chip

Fig. 1. Buffer amplifier in analog signal processing system.

Input Stage Driver Stage

VDD

VSS

Output Stage MO1

MO2

Fig. 2. Structure of buffer amplifier.

VDD

VSS

Vin

MO1

MO2

Vo-

+

-

+B

+

-A

(a)

VDD

VSS

-

+Vin

MO1

MO2

Vo

-

+-+

A1

B1

B

+

-+-B2

A2

A

(b)

Fig. 3. Configuration of buffer with quasi-complementary output stage (a) traditional version, (b) improved version.

one rail of the power supply, one error amplifier willlose control while the other error amplifier will workproperly to control the gates of two output transistors.

The proposed buffer amplifier has been successfullyrealized and used in the interface circuit for an opticalMEMS accelerometer [9].

In the next section, detailed circuit description of thebuffer amplifier is given. Simulation and chip measure-ment results are summarized and discussed in Section 3.

Circuit Description

A. Adaptive Load

Adaptive load was first introduced in [8]. Adaptive loadis a resistive load which can be changed, under certainconditions, from one value of resistance to another. Inthis work, we use an improved adaptive load in thedesign of error amplifier in Fig. 3(b).

A New CMOS Buffer Amplifier Design 9

0

G

Vo

Fig. 4. Expected characteristics of gains of error amplifiers A and B.

As discussed in Section 1, in the quasi complemen-tary output stage, the gains (G) of the error amplifiersA and B influence two sides of circuit performance. Onthe one hand, gains of error amplifiers decide the driv-ing capability of the output stage. The higher the gainof error amplifier, the smaller the output resistance ofoutput node, and larger driving capability at the outputnode. On the other hand, G influence the fluctuation ofquiescent current of the buffer (the higher the gain oferror amplifier, the easier the quiescent current deviatesfrom its designed target value, due to random offset oferror amplifiers).

To obtain the high driving capability and steady qui-escent current at the same time, the gains G of error

Fig. 5. Simplified schematic of error amplifier A in the improved quasi-complementary output stage as shown in Fig. 3(b).

amplifiers A and B should behave as shown in Fig. 4. Gis low in the region near the quiescent operating point(output voltage Vo = 0), and becomes high when Vo isfar from quiescent point.

Fortunately, characteristics of G as shown in Fig. 4can be implemented using adaptive load concept, inFig. 5, by triggering low conductance loads (currentsource I1 and I2) or high conductance loads (diode-connected transistors MA12 and MA20). In the regionnear the quiescent operation point, the adaptiveswitches MA13 and MA21 turn on, high conductanceloads (MA12 and MA20) are used to achieve low G. Inthe region far away from quiescent point, MA13 andMA21 turn off, low conductance loads (I1 and I2) areused to achieve a high G.

The implementation of such adaptive switches andthus adaptive loads used in error amplifier will be de-scribed in the following subsection.

B. Error Amplifier with Adaptive Load

In Fig. 5, MA12/MA13 and MA21/MA20 are used asadaptive load. The primary feature of the new adaptiveload is to use variable bias for the two switches MA13

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Fig. 6. Complete schematic of error amplifier A in improved quasi-complementary output stage.

and MA21 to avoid the troublesome determination of in [8]. The variable biases Vb1 and Vb2 enable switchesMA13 and MA21 turn on in quiescent state, while turnoff in driving mode.

Fig. 6 gives the implementation circuit of the Vb1 andVb2. The work principle is as follows. Under quiescentconditions, the conductances at nodes A2 (B2) is verylarge, because switch MA13 (MA21) is on, and MA12(MA20) is connected as a diode. Therefore, the gain ofthe error amplifier is low and sensitivity at nodes A2and B2 is reduced, thus a stable quiescent current isobtained.

In driving mode, when (Vin+Vin) increases, nodeA2 and drain voltage of MA15 are pulled down, largecurrents go through MA13, MA12, MA16, MA17 andMA18. Before MA13 turns off, source-to-gate voltageof MA12 becomes larger with the increase of its draincurrent. Correspondingly, the source voltage of MA13decreases. On the other hand, gate voltage of MA13 willincrease, because of the increasing gate-to-source volt-age of MA18 created by the increasing currents of MA16and MA17. The different changing direction for the gatevoltage and source voltage of MA13 eventually turns offMA13 and causes the overall resistance of the adaptiveload to increase, therefore, leads to an improved driv-ing capability. Similar analysis can be done in drivingmode when (Vin+ Vin) decreases.

Amplifier B in Fig. 3(b) is derived from amplifier Aby replacing all n-MOS transistors by p-MOS transis-tors and vice versa, and swapping the polarities of thesupply rails.

C. Amplifier Using the Proposed Output Stage

To test the performance and functionality of the pro-posed output buffer stage, it was incorporated into atwo-stage opamp. Complete circuit schematic of theproposed buffer amplifier is given in Fig. 7. The de-signed opamp follows the structure of Fig. 3(b). It con-sists of a constant transconductance rail-to-rail inputstage [10] (M1M40), and the proposed class AB out-put stage. Class AB output stage is comprised by erroramplifiers A (MA1MA21) and B (MB1MB14), as wellas two output transistors MO1 and MO2.

Simulation and Chip Measurement Results

Fig. 8 and Fig. 9 show the output transistor drain cur-rents of MO1 and MO2 versus output voltage Vo whenA2 and B1 in Fig. 3(b) are disconnected or connectedfrom the gates of output transistors. In Fig. 8, outputtransistors drain currents are measured when node A2and B1 in Fig. 3(b) are disconnected. When Vo > 0.4 V,amplifier A in Fig. 3(b) does not work properly. Thedrain current of MO2 loses proper control and becomesvery large. When Vo < 0.75 V, amplifier B does notwork properly. The drain current of MO1 loses propercontrol and becomes very large. Such facts are reflectedin Fig. 8. In Fig. 9, drain currents of the output transis-tor are measured when nodes A2 and B1 are connectedas in Fig. 3(b). The drain current of MO1 or MO2 are

A New CMOS Buffer Amplifier Design 11

12 Ha, Li and Liu

Fig. 8. Simulation of drain current of output transistors when nodes A2 and B1 in Fig. 3(b) are disconnected (VDD = 1.5 V).

Fig. 9. Simulation of drain currents of output transistors in Fig. 3 (b) (VDD = 1.5 V).

controlled properly in the whole output range, as ex-pected in our design.

Fig. 10 shows the die photo of two fabricated bufferamplifiers. Fig. 11 shows the measured DC transfercharacteristics when the buffer is connected in an unity-gain configuration under different loads. With 300

load in a 1.5 V supply, the output swing of the bufferamplifier is +1.16 V to 1.26 V. The mean value ofquiescent current for eight samples is 204 A, with theworst deviation of 17%. The amplifier has a DC gain of74 dB, and unity gain-bandwidth of 1 MHz (as shownin Fig. 13) with phase margin of 62.

A New CMOS Buffer Amplifier Design 13

Fig. 10. Die photo of two buffer amplifiers.

Fig. 11. Measured DC transfer function for the buffer amplifier connected as an unity-gain follower with 100 , 300 , and 700 loadsrespectively.

14 Ha, Li and Liu

Fig. 12. Measured large signal response of proposed buffer amplifier with a 2Vpp/100 kHz step. The buffer amplifier is connected as an unity-gainfollower. (Lower curveinput signal, upper curveoutput signal).

Fig. 13. AC response of the buffer amplifier.

.

A New CMOS Buffer Amplifier Design 15

Fig. 14. Magnitude spectrum of the proposed buffer amplifier when connected in an unity-gain follower with 1 kHz sine wave input.

Large signal transient response of the proposedbuffer amplifier with a 2Vpp/50 kHz step input is shownin Fig. 12 while the measured magnitude spectrum ofthe proposed buffer amplifier when connected in anunity-gain follower with 1 kHz sine wave input is plot-ted in Fig. 14. Performance of the buffer amplifier issummarized in Table 1.

Table 1. Performance summary of the proposed buffer amplifier(Vsupply = 1.5 V, RL = 300 , CL = 33 pf )

Parameters Measured Results

Avol 74 dBFu 1 MHzPhase Margin 62PSRR + (DC) 87 dB

(1 kHz) 80 dBPSRR (DC) 92 dB

(1 kHz) 81 dBTHD @ 1 kHz, 2Vpp, 300 load 54 dBSlew Rate positive 0.6 V/s,

negative 0.9 V/sVoffset 2.52 mVQuiescent Power Dissipation 1.43 mWOutput Swing 2.42 VInput Noise Density @ 1 kHz 95 nV/

Hz

Conclusion

In this paper, a low-voltage high driving capabilityCMOS buffer with quiescent current control is devel-oped. By applying adaptive loads and improved erroramplifiers, the buffer amplifier achieves both excel-lent load driving capability and stable quiescent cur-rent. Improved quasi-complementary output stage en-ables the proposed buffer to work at power supplybelow 1 V.

Acknowledgment

The authors would like to thank Dr. Lian Yong andMs. Zhang Xiwen for assistance in this work. Thiswork is supported by the Singapore National Scienceand Technology Board Research Grant NSTB/17/2/3.Yajun Ha would like to thank IMEC, Belgium forkindly supporting him to present partial results of thiswork in ICECS99, Cyprus.

References

1. Gray, P. R. and Meyer, R. G., Analysis and Design of AnalogIntegrated Circuits, John Wiley & Sons, Inc, 1993.

16 Ha, Li and Liu

2. Ahuja, B. K., Gray, P. R., Baxter, W. M. and Uehara, G. T.,A programmable CMOS dual channel interface processor fortelecommunications applications. IEEE J. Solid-State Circuits19, pp. 892899, December 1984.

3. Kih, J., Chang, B., Jeong, D. K. and Kim, W., Class-AB large-swing CMOS buffer amplifier with controlled bias current.IEEE J. Solid-State Circuits 28, pp. 13501353, December 1993.

4. Brehmer, K. E. and Weiser, J. B., Large swing CMOS poweramplifier. IEEE J. Solid-State Circuits 29, pp. 624629, De-cember 1983.

5. Fisher, J. A., A high-performance CMOS power amplifier.IEEE J. Solid-State Circuits 20, pp. 12001205, December 1985.

6. Nagaraj, K., Large-swing CMOS buffer amplifier. IEEE J.Solid-State Circuits 24, pp. 181183, February 1989.

7. Mistlberger, F. and Koch, R., Class-AB high-swing CMOSpower amplifier. IEEE J. Solid-State Circuits 27, pp. 10891092, July 1992.

8. You, F., Embabi, S. H. K. and Sinencio, E. S., Low-voltage classAB buffers with quiescent current control. IEEE J. Solid-StateCircuits 33, pp. 915919, June 1998.

9. Chollet, F., Tang, X. S., Liu, A. Q., Ha, Y. and Li, M. F., Mi-cromachined shutter and low-voltage electronics for optical dis-placement/acceleration sensing, in Proceedings of the 10th Int.Conf. on Solid-State Sensors and Actuators, 1999.

10. Hogervorst, R. and Huijsing, J. H., Design of Low-Voltage, Low-Power Operational Amplifier Cells, Kluwer Academic Publish-ers, 1996.

11. Ha, Y., Li, M. F. and Liu, A. Q., Low voltage high drivingcapability CMOS buffer used in MEMS interface circuits, inProceedings of the 6th Int. Conf. on Electronics, Circuits andSystems, 1999.

Yajun Ha received the Bachelor of Engineeringdegree from the Department of Information and Elec-tronics at the Zhejiang University, China, in 1996. From1996 to 1997, he was a research engineer with theShanghai Aerospace Bureau. In 1999, he received theMaster of Engineering degree in electrical engineeringfrom the National University of Singapore. He is cur-rently working toward the Ph.D. degree at theKatholieke University of Leuven (K. U. Leuven),Belgium, and supported by the Inter-university Mi-croelectronics Center (IMEC), Belgium. His researchinterests include analog VLSI circuit design, recon-

figurable systems, VLSI systems design, and designautomation.

Associate Professor A. Q. Liu received his Ph.D. inApplied Mechanics from National University ofSingapore (NUS) in 1994. His M.S. degree was in Ap-plied Physics, and B. Eng. Degree was in Mechani-cal Engineering from Xian Jiaotong University. Hestarted to explore MEMS technology in 1995 whenhe had worked in the DSO National Laboratory. In1997, he joined Institute of Materials Research & En-gineering (IMRE), National University of Singapore,as a senior research fellow, to establish and drive theMEMS program, and build up MEMS core technol-ogy. Currently, he is an associate professor of Divi-sion of Microelectronics, School of Electrical & Elec-tronic Engineering, Nanyang Technological University(NTU). His research interest is optical and RF MEMStechnology in infocomm applications. He has imple-mented MEMS technology in a number of devices re-lated to positive optical network (PON) systems, suchas OXCs and add/drop multiplexers. Integration fab-rication process, RF devices and electronic interfacecircuitry are also his major contribution areas.

Li Ming-Fu graduated from the Department ofPhysics, Fudan University, Shanghai, China in 1960.After graduation he joined the Department of AppliedPhysics, University of Science and Technology ofChina (USTC) as a teaching assistant and lecturer. In1978, he joined the graduate school faculty, ChineseAcademy of Sciences, Beijing, first as an associate pro-fessor and, in 1986, a professor. He has also served asadjunct professor at the Institute of Semiconductors,Chinese Academy of Sciences, Fudan University, andUSTC, Hefei.

He was a visiting scholar at Case Western ReserveUniversity, Cleveland, OH, in 1979, University ofIllinois at Urbana-Champain from 1979 to 1981, andwas a visiting scientist at University of California at

A New CMOS Buffer Amplifier Design 17

Berkeley and Lawrence Berkeley National Laborato-ries from 1986 to 1987, 1990 to 1991, and 1993. Hejoined the Department of Electrical Engineering, Na-tional University of Singapore, as an associate profes-sor in 1991, and a professor in 1996. His current re-search interests are in the areas of reliability physicsin deep sub-micron CMOS devices, analog IC design,

and wide energy gap group III nitride. He has pub-lished over 140 research papers and two books, includ-ing Modern Semiconductor Quantum Physics (WorldScientific, 1994). He has served on several internationalprogram committees and advisory committees in inter-national semiconductor conferences in China, Japan,Canada, Germany, and Singapore.