03 numeric basics (1)_help

Digital Design:An Embedded Systems Approach Using VerilogChapter 3Numeric BasicsPortions of this work are from the book, Digital Design: An Embedded Systems Approach Using Verilog, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

Digital Design Chapter 3 Numeric Basics

Verilog

Digital Design Chapter 3 Numeric Basics*Numeric BasicsRepresenting and processing numeric data is a common requirementunsigned integerssigned integersfixed-point real numbersfloating-point real numberscomplex numbers


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned IntegersNon-negative numbers (including 0)Represent real-world datae.g., temperature, position, time, Also used in controlling operation of a digital systeme.g., counting iterations, table indicesCoded using unsigned binary (base 2) representationanalogous to decimal representation


Verilog

Digital Design Chapter 3 Numeric Basics*Binary RepresentationDecimal: base 1012410 = 1102 + 2101 + 4100Binary: base 212410 = 126+125+124+123+122+021+020 = 11111002In general, a number x is represented using n bits as xn1, xn2, , x0, where


Verilog

Digital Design Chapter 3 Numeric Basics*Binary RepresentationUnsigned binary is a code for numbersn bits: represent numbers from 0 to 2n 10: 000000; 2n 1: 111111To represent x: 0 x N 1, need log2N bitsComputers use8-bit bytes: 0, , 25532-bit words: 0, , ~4 billionDigital circuits can use what ever size is appropriate


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned Integers in VerilogUse vectors as the representationCan apply arithmetic operationsmodule multiplexer_6bit_4_to_1 ( output reg [5:0] z, input [5:0] a0, a1, a2, a3, input [1:0] sel ); always @* case (sel) 2'b00: z = a0; 2'b01: z = a1; 2'b10: z = a2; 2'b11: z = a3; endcaseendmodule


Verilog

Digital Design Chapter 3 Numeric Basics*Octal and HexadecimalShort-hand notations for vectors of bitsOctal (base 8)Each group of 3 bits represented by a digit0: 000, 1:001, 2: 010, , 7: 1112538 = 010 101 0112110010112 11 001 0112 = 3138Hex (base 16) Each group of 4 bits represented by a digit0: 0000, , 9: 1001, A: 1010, , F: 11113CE16 = 0011 1100 11102110010112 1100 10112 = CB16


Verilog

Digital Design Chapter 3 Numeric Basics*Extending Unsigned NumbersTo extend an n-bit number to m bitsAdd leading 0 bitse.g., 7210 = 1001000 = 000001001000

wire [3:0] x; wire [7:0] y;

assign y = {4'b0000, x};assign y = {4'b0, x};assign y = x;


Verilog

Digital Design Chapter 3 Numeric Basics*Truncating Unsigned NumbersTo truncate from m bits to n bitsDiscard leftmost bitsValue is preserved if discarded bits are 0Result is x mod 2nassign x = y[3:0];


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned AdditionPerformed in the same way as decimaloverflowcarry bits


Verilog

Digital Design Chapter 3 Numeric Basics*Addition CircuitsHalf adderfor least-significant bitsFull adderfor remaining bits

xiyicisici+10000000110010100110110010101011100111111


Verilog

Digital Design Chapter 3 Numeric Basics*Ripple-Carry AdderFull adder for each bit, c0 = 0overflowWorst-case delayfrom x0, y0 to sncarry must ripple through intervening stages, affecting sum bits


Verilog

Digital Design Chapter 3 Numeric Basics*Improving Adder PerformanceCarry kill:Carry propagate:Carry generate:Adder equations

xiyicisici+10000000110010100110110010101011101111111


Verilog

Digital Design Chapter 3 Numeric Basics*Fast-Carry-Chain AdderAlso called Manchester adderXilinx FPGAs include this structure


Verilog

Digital Design Chapter 3 Numeric Basics*Carry Lookahead


Verilog

Digital Design Chapter 3 Numeric Basics*Carry-Lookahead AdderAvoids chained carry circuitUse multilevel lookahead for wider numbers


Verilog

Digital Design Chapter 3 Numeric Basics*Other Optimized AddersOther adders are based on other reformulations of adder equationsChoice of adder depends on constraintse.g., ripple-carry has low area, so is ok for low performance circuitse.g., Manchester adder ok in FPGAs that include carry-chain circuits


Verilog

Digital Design Chapter 3 Numeric Basics*Adders in VerilogUse arithmetic + operatorwire [7:0] a, b, s; ... assign s = a + b;wire [8:0] tmp_result; wire c; ... assign tmp_result = {1'b0, a} + {1'b0, b}; assign c = tmp_result[8]; assign s = tmp_result[7:0];assign {c, s} = {1'b0, a} + {1'b0, b};assign {c, s} = a + b;


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned SubtractionAs in decimalborrow bits


Verilog

Digital Design Chapter 3 Numeric Basics*Subtraction CircuitsFor least-significant bitsFor remaining bits

xiyibisibi+10000000111010110110110010101001101011111


Verilog

Digital Design Chapter 3 Numeric Basics*Adder/Subtracter CircuitsMany systems add and subtractTrick: use complemented borrowsAdditionSubtractionSame hardware can perform bothFor subtraction: complement y, set


Verilog

Digital Design Chapter 3 Numeric Basics*Adder/Subtracter CircuitsAdder can be any of those we have seendepends on constraints


Verilog

Digital Design Chapter 3 Numeric Basics*Subtraction in Verilogmodule adder_subtracter ( output [11:0] s, output ovf_unf, input [11:0] x, y, input mode ); assign {ovf_unf, s} = !mode ? (x + y) : (x - y);endmodule


Verilog

Digital Design Chapter 3 Numeric Basics*Increment and DecrementAdding 1: set y = 0 and c0 = 1These are equations for a half adderSimilarly for decrementing: subtracting 1


Verilog

Digital Design Chapter 3 Numeric Basics*Increment/Decrement in VerilogJust add or subtract 1wire [15:0] x, s; ...

assign s = x + 1; // increment x

assign s = x - 1; // decrement xNote: 1 (integer), not 1'b1 (bit)Automatically resized


Verilog

Digital Design Chapter 3 Numeric Basics*Equality ComparisonXNOR gate: equality of two bitsApply bitwise to two unsigned numbersassign eq = x == y;In Verilog, x == y gives a bit result1'b0 for false, 1'b1 for true


Verilog

Digital Design Chapter 3 Numeric Basics*Inequality ComparisonMagnitude comparator for x > y


Verilog

Digital Design Chapter 3 Numeric Basics*Comparison Example in VerilogThermostat with target termperatureHeater or cooler on when actual temperature is more than 5 from targetmodule thermostat ( output heater_on, cooler_on, input [7:0] target, actual ); assign heater_on = actual < target - 5; assign cooler_on = actual > target + 5;endmodule


Verilog

Digital Design Chapter 3 Numeric Basics*Scaling by Power of 2This is x shifted left k places, with k bits of 0 added on the rightlogical shift left by k placese.g., 000101102 23 = 000101100002Truncate if result must fit in n bitsoverflow if any truncated bit is not 0


Verilog

Digital Design Chapter 3 Numeric Basics*Scaling by Power of 2This is x shifted right k places, with k bits truncated on the rightlogical shift right by k placese.g., 011101102 / 23 = 011102Fill on the left with k bits of 0 if result must fit in n bits


Verilog

Digital Design Chapter 3 Numeric Basics*Scaling in VerilogShift-left () operationsresult is same size as operandassign y = s > 2;s = 000100112 = 1910y = 0001002 = 410


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned Multiplicationyi x 2i is called a partial productif yi = 0, then yi x 2i = 0if yi = 1, then yi x 2i is x shifted left by iCombinational array multiplierAND gates form partial productsadders form full product


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned MultiplicationAdders can be any of those we have seenOptimized multipliers combine parts of adjacent adders


Verilog

Digital Design Chapter 3 Numeric Basics*Product SizeGreatest result for n-bit operands:Requires 22n bits to avoid overflowAdding n-bit and m-bit operandsrequires n + m bitswire [ 7:0] x; wire [13:0] y; wire [21:0] p; ... assign p = {14'b0, x} * {8'b0, y};assign p = x * y; // implicit resizing


Verilog

Digital Design Chapter 3 Numeric Basics*Other Unsigned OperationsDivision, remainderMore complicated than multiplicationLarge circuit area, powerComplicated operations are often performed sequentiallyin a sequence of steps, one per clock cyclecost/performance/power trade-off


Verilog

Digital Design Chapter 3 Numeric Basics*Gray CodesImportant for position encodersOnly one bit changes at a timeSee book for n-bit Gray code

SegmentCodeSegmentCode00000811001000191101200111011113001011111040110121010501111310116010114100170100151000


Verilog

Digital Design Chapter 3 Numeric Basics*Signed IntegersPositive and negative numbers (and 0)n-bit signed magnitude code1 bit for sign: 0 +, 1 n 1 bits for magnitudeSigned-magnitude rarely used for integers nowcircuits are too complexUse 2s-complement binary code


Verilog

Digital Design Chapter 3 Numeric Basics*2s-Complement RepresentationMost-negative number10000 = 2n1Most-positive number01111 = +2n1 1xn1 = 1 negative, xn1 = 0 non-negativeSince


Verilog

Digital Design Chapter 3 Numeric Basics*2s-Complement Examples00110101= 125 + 124 + 122 + 120 = 5310110101= 127 + 125 + 124 + 122 + 120 = 128 + 53 = 7500000000 = 011111111 = 110000000 = 12801111111 = +127


Verilog

Digital Design Chapter 3 Numeric Basics*Signed Integers in VerilogUse signed vectorswire signed [ 7:0] a;reg signed [13:0] b;Can convert between signed and unsigned interpretationswire [11:0] s1; wire signed [11:0] s2; ...assign s2 = $signed(s1); // s1 is known to be // less than 2**11 ... assign s1= $unsigned(s2); // s2 is known to be nonnegative


Verilog

Digital Design Chapter 3 Numeric Basics*Octal and Hex Signed IntegersDont think of signed octal or hexJust treat octal or hex as shorthand for a vector of bitsE.g., 84410 is 001101001100In hex: 0011 0100 1100 34CE.g., 4210 is 1111010110In octal: 1 111 010 110 1726 (10 bits)


Verilog

Digital Design Chapter 3 Numeric Basics*Resizing Signed IntegersTo extend a non-negative numberAdd leading 0 bitse.g., 5310 = 00110101 = 000000110101To truncate a non-negative numberDiscard leftmost bits, provideddiscarded bits are all 0sign bit of result is 0E.g., 4110 is 00101001Truncating to 6 bits: 101001 error!


Verilog

Digital Design Chapter 3 Numeric Basics*Resizing Signed IntegersTo extend a negative numberAdd leading 1 bitsSee textbook for proofe.g., 7510 = 10110101 = 111110110101To truncate a negative numberDiscard leftmost bits, provideddiscarded bits are all 1sign bit of result is 1


Verilog

Digital Design Chapter 3 Numeric Basics*Resizing Signed IntegersIn general, for 2s-complement integersExtend by replicating sign bitsign extensionTruncate by discarding leading bitsDiscarded bits must all be the same, and the same as the sign bit of the resultwire signed [ 7:0] x; wire signed [15:0] y; ...assign y = {{8{x[7]}}, x};assign y = x; ...assign x = y;


Verilog

Digital Design Chapter 3 Numeric Basics*Signed NegationComplement and add 1Note thatE.g., 43 is 00101011 so 43 is 11010100 + 1 = 11010101


Verilog

Digital Design Chapter 3 Numeric Basics*Signed NegationWhat about negating 2n1?100000 011111 + 1 = 100000Result is 2n1!Recall range of n-bit numbers is not symmetricEither check for overflow, extend by one bit, or ensure this case cant ariseIn Verilog: use operatorE.g., assign y = x;


Verilog

Digital Design Chapter 3 Numeric Basics*Signed AdditionPerform addition as for unsignedOverflow if cn1 differs from cnSee textbook for case analysisCan use the same circuit for signed and unsigned additionyields cn1


Verilog

Digital Design Chapter 3 Numeric Basics*Signed Addition Examplesno overflowpositive overflownegative overflowno overflowno overflowno overflow


Verilog

Digital Design Chapter 3 Numeric Basics*Signed Addition in VerilogResult of + is same size as operandswire signed [11:0] v1, v2; wire signed [12:0] sum; ...assign sum = {v1[11], v1} + {v2[11], v2}; ... assign sum = v1 + v2; // implicit sign extensionTo check overflow, compare signswire signed [7:0] x, y, z; wire ovf; ...assign z = x + y; assign ovf = ~x[7] & ~y[7] & z[7] | x[7] & y[7] & ~z[7];


Verilog

Digital Design Chapter 3 Numeric Basics*Signed SubtractionUse a 2s-complement adderComplement y and set c0 = 1


Verilog

Digital Design Chapter 3 Numeric Basics*Other Signed OperationsIncrement, decrementsame as unsignedComparison=, same as unsigned>, compare sign bits usingMultiplicationComplicated by the need to sign extend partial productsRefer to Further Reading


Verilog

Digital Design Chapter 3 Numeric Basics*Scaling Signed IntegersMultiplying by 2klogical left shift (as for unsigned)truncate result using 2s-complement rulesDividing by 2karithmetic right shiftdiscard k bits from the right, and replicate sign bit k times on the lefte.g., s = "11110011" -- 13 shift_right(s, 2) = "11111100" -- 13 / 22


Verilog

Digital Design Chapter 3 Numeric Basics*Fixed-Point NumbersMany applications use non-integersespecially signal-processing appsFixed-point numbersallow for fractional partsrepresented as integers that are implicitly scaled by a power of 2can be unsigned or signed


Verilog

Digital Design Chapter 3 Numeric Basics*Positional NotationIn decimalIn binaryRepresent as a bit vector: 10101binary point is implicit


Verilog

Digital Design Chapter 3 Numeric Basics*Unsigned Fixed-Pointn-bit unsigned fixed-pointm bits before and f bits after binary pointRange: 0 to 2m 2fPrecision: 2fm may be 0, giving fractions onlye.g., m= 2: 0.0001001101


Verilog

Digital Design Chapter 3 Numeric Basics*Signed Fixed-Pointn-bit signed 2s-complement fixed-pointm bits before and f bits after binary pointRange: 2m1 to 2m1 2fPrecision: 2fE.g., 111101, signed fixed-point, m = 211.11012 = 2 + 1 + 0.5 + 0.25 + 0.0625 = 0.187510


Verilog

Digital Design Chapter 3 Numeric Basics*Choosing Range and PrecisionChoice depends on applicationNeed to understand the numerical behavior of computations performedsome operations can magnify quantization errorsIn DSPfixed-point range affects dynamic rangeprecision affects signal-to-noise ratioPerform simulations to evaluate effects


Verilog

Digital Design Chapter 3 Numeric Basics*Fixed-Point in VerilogUse vectors with implied scalingIndex range matches powers of weightsAssume binary point between indices 0 and 1module fixed_converter ( input [5:-7] in, output signed [7:-7] out ); assign out = {2'b0, in};endmodule


Verilog

Digital Design Chapter 3 Numeric Basics*Fixed-Point OperationsJust use integer hardwaree.g., addition:Ensure binary points are aligned


Verilog

Digital Design Chapter 3 Numeric Basics*Floating-Point NumbersSimilar to scientific notation for decimale.g., 6.022141991023, 1.602176531019Allow for larger range, with same relative precision throughout the range6.022141991023mantissaradixexponent


Verilog

Digital Design Chapter 3 Numeric Basics*IEEE Floating-Point Formats: sign bit (0 non-negative, 1 negative)Normalize: 1.0 |M| < 2.0M always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit)Exponent: excess representation: E + 2e11sexponentmantissae bitsm bits


Verilog

Digital Design Chapter 3 Numeric Basics*Floating-Point RangeExponents 000...0 and 111...1 reservedSmallest valueexponent: 000...01 E = 2e1 + 2mantissa: 0000...00 M = 1.0Largest valueexponent: 111...10 E = 2e1 1mantissa: 111...11 M 2.0Range:


Verilog

Digital Design Chapter 3 Numeric Basics*Floating-Point PrecisionRelative precision approximately 2mall mantissa bits are significantm bits of precisionm log102 m 0.3 decimal digits


Verilog

Digital Design Chapter 3 Numeric Basics*Example FormatsIEEE single precision, 32 bitse = 8, m = 23range 1.2 1038 to 1.7 1038precision 7 decimal digitsApplication-specific, 22 bitse = 5, m = 16range 6.1 105 to 6.6 104precision 5 decimal digits


Verilog

Digital Design Chapter 3 Numeric Basics*Denormal NumbersExponent = 000...0 hidden bit is 0Smaller than normal numbersallow for gradual underflow, with diminishing precisionMantissa = 000...0


Verilog

Digital Design Chapter 3 Numeric Basics*Infinities and NaNsExponent = 111...1, mantissa = 000...0InfinityCan be used in subsequent calculations, avoiding need for overflow checkExponent = 111...1, mantissa 000...0Not-a-Number (NaN)Indicates illegal or undefined resulte.g., 0.0 / 0.0Can be used in subsequent calculations


Verilog

Digital Design Chapter 3 Numeric Basics*Floating-Point OperationsConsiderably more complicated than integer operationsE.g., additionunpack, align binary points, adjust exponentsadd mantissas, check for exceptionsround and normalize result, adjust exponentCombinational circuits not feasiblePipelined sequential circuits


Verilog

Digital Design Chapter 3 Numeric Basics*SummaryUnsigned:Signed:Octal and Hex short-handOperations: resize, arithmetic, compareArithmetic circuits trade off speed/area/powerFixed- and floating-point non-integersGray codes for position encoding


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03 numeric basics (1)_help

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