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COMP541COMP541

State MachinesState Machines

Montek SinghMontek Singh

Feb 8, 2012Feb 8, 2012

Today’s TopicsToday’s Topics State MachinesState Machines

How to design machines that go through a How to design machines that go through a sequencesequence of eventsof events““sequential machines”sequential machines”

Basically close the feedback loop in this picture:Basically close the feedback loop in this picture:

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Synchronous Sequential LogicSynchronous Sequential Logic

Flip-flops/registers contain the system’s Flip-flops/registers contain the system’s statestate state changes only at clock edgestate changes only at clock edge

so system is so system is synchronized synchronized to the clockto the clock all flip-flops receive the same clock signal (important!)all flip-flops receive the same clock signal (important!) every cyclic path must contain a flip-flopevery cyclic path must contain a flip-flop

Two common typesTwo common types Two common synchronous sequential circuits:Two common synchronous sequential circuits:

Finite State Machines (FSMs)Finite State Machines (FSMs)

PipelinesPipelines

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Finite State Machine (FSM)Finite State Machine (FSM) Consists of:Consists of:

State register thatState register thatholds the current stateholds the current stateupdates it to the “next updates it to the “next

state” at clock edgestate” at clock edge

Combinational logic (CL) Combinational logic (CL) thatthatcomputes the next statecomputes the next state

– using current state and using current state and inputsinputs

computes the outputscomputes the outputs– using current state (and using current state (and

maybe inputs)maybe inputs)

NextState

CurrentState

S’ S

CLK

CL

Next StateLogic

NextState

CL

OutputLogic

Outputs

More and Mealy FSMsMore and Mealy FSMs Two types of finite state machines differ in the Two types of finite state machines differ in the

output logic:output logic: Moore FSMMoore FSM::

outputs depend only on the current stateoutputs depend only on the current state Mealy FSMMealy FSM::

outputs depend on the current state outputs depend on the current state and the inputsand the inputs can convert from one form to the othercan convert from one form to the other

Mealy is more generalMealy is more general

In Both:In Both: Next state is determined by current state and inputsNext state is determined by current state and inputs

Moore and Mealy FSMsMoore and Mealy FSMs

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CLKM Nk knext

statelogic

outputlogic

Moore FSM

CLKM Nk knext

statelogic

outputlogic

inputs

inputs

outputs

outputsstate

statenextstate

nextstate

Mealy FSM

FSM ExampleFSM Example Traffic light controllerTraffic light controller

Traffic sensors: TTraffic sensors: TAA, T, TBB (TRUE when there’s traffic) (TRUE when there’s traffic)

Lights: LLights: LAA, L, LBB

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bravado

Blvd.

Dorms

Fields

DiningHall

Labs

FSM Black BoxFSM Black Box Inputs:Inputs:

CLK, Reset, TCLK, Reset, TAA, T, TBB

Outputs: LOutputs: LAA, L, LBB

TA

TB

LA

LB

CLK

Reset

TrafficLight

Controller

Design Simple FSMDesign Simple FSM When When resetreset, L, LAA is green is green

and Land LBB is red is red

As long as traffic on As long as traffic on Academic (TAcademic (TAA high), keep high), keep LLAA green green

When TWhen TAA goes low, goes low, sequence to traffic on sequence to traffic on BravadoBravado

Follow same algorithm for Follow same algorithm for BravadoBravado

Let’s say clock period is 5 Let’s say clock period is 5 sec (time for yellow light)sec (time for yellow light)

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TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bravado

Blvd.

Dorms

Fields

DiningHall

Labs

StatesStates What sequence do the traffic lights follow?What sequence do the traffic lights follow?

Reset Reset State 0, L State 0, LAA is green and L is green and LBB is red is red Next (on board)?Next (on board)?

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TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bra

vado

Blvd

.

Dorms

Fields

DiningHall

Labs

State Transition DiagramState Transition Diagram

• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

Reset

TA

LA

TA

LB

TB

TB

LA

LB

Academic Ave.

Bra

vado

Blvd

.

Dorms

Fields

DiningHall

Labs

State Transition TableState Transition Table

Current State Inputs

Next State

S TA TB S'

S0 0 X S1

S0 1 X S0

S1 X X S2

S2 X 0 S3

S2 X 1 S2

S3 X X S0

FSM Encoded State Transition FSM Encoded State Transition TableTable

State Encoding

S0 00

S1 01

S2 10

S3 11

Current State Inputs Next State

S1 S0 TA TB S'1 S'00 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

FSM Output TableFSM Output Table

Current State Outputs

S1 S0 LA1 LA0 LB1 LB0

0 0 0 0 1 0

0 1 0 1 1 0

1 0 1 0 0 0

1 1 1 0 0 1

Output Encoding

green 00

yellow 01

red 10

LA1 = S1

LA0 = S1S0

LB1 = S1

LB0 = S1S0

FSM Schematic: State RegisterFSM Schematic: State Register

S1

S0

S'1

S'0

CLK

state register

Reset

r

Next State LogicNext State Logic

S1

S0

S'1

S'0

CLK

next state logic state register

Reset

TA

TB

inputs

S1 S0

r

Current State Inputs Next State

S1 S0 TA TB S'1 S'00 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

Output LogicOutput Logic

S1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r

LA1 = S1

LA0 = S1S0

LB1 = S1

LB0 = S1S0

FSM Timing Diagram: Study FSM Timing Diagram: Study carefully!carefully!

CLK

Reset

TA

TB

S'1:0

S1:0

LA1:0

LB1:0

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10

S1 (01) S2 (10) S3 (11) S0 (00)

t (sec)

??

??

S0 (00)

S0 (00) S1 (01) S2 (10) S3 (11) S1 (01)

??

??

0 5 10 15 20 25 30 35 40 45

Green (00)

Red (10)

S0 (00)

Yellow (01) Red (10) Green (00)

Green (00) Red (10)Yellow (01)

S0LA: greenLB: red

S1LA: yellowLB: red

S3LA: redLB: yellow

S2LA: redLB: green

TATA

TB

TB

ResetS1

S0

S'1

S'0

CLK

next state logic output logicstate register

Reset

LA1

LB1

LB0

LA0

TA

TB

inputs outputs

S1 S0

r

Current State Inputs Next State

S1 S0 TA TB S'1 S'00 0 0 X 0 1

0 0 1 X 0 0

0 1 X X 1 0

1 0 X 0 1 1

1 0 X 1 1 0

1 1 X X 0 0

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Design ProcedureDesign Procedure Take problem description and refine it into a Take problem description and refine it into a

state table or diagramstate table or diagram Assign codes to the statesAssign codes to the states Derive Boolean equations and implementDerive Boolean equations and implement

Or, write Verilog and compileOr, write Verilog and compile

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Example: Sequence RecognizerExample: Sequence Recognizer Circuit has input, X, and output, ZCircuit has input, X, and output, Z Recognizes sequence 1101 on XRecognizes sequence 1101 on X

Specifically, if X has been 110 and next bit is 1, make Specifically, if X has been 110 and next bit is 1, make Z highZ high

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How to Design StatesHow to Design States States States rememberremember past history past history

Clearly must remember we’ve seen 110 when next 1 Clearly must remember we’ve seen 110 when next 1 comes alongcomes along

Tell me one necessary state for this example…?Tell me one necessary state for this example…?

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Beginning StateBeginning State Start state: letStart state: let’’s call it As call it A

if 1 appears on input, move to next state Bif 1 appears on input, move to next state B output remains at 0output remains at 0

Input / Output

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Second 1Second 1 New state, CNew state, C To reach C, must have seen 11To reach C, must have seen 11

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Next a 0Next a 0 If 110 has been received, go to DIf 110 has been received, go to D Next 1 will generate a 1 on output ZNext 1 will generate a 1 on output Z

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What else?What else? What happens to arrow on right?What happens to arrow on right? Must go to some state.Must go to some state. Where?Where?

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What Sequence?What Sequence? Here we have to interpret the problem Here we have to interpret the problem

statementstatement WeWe’’ve just seen 01ve just seen 01

Is this beginning of new 1101?Is this beginning of new 1101? Or do we need to start over w/ another 1?Or do we need to start over w/ another 1?

Textbook: decides that itTextbook: decides that it’’s beginning (01…)s beginning (01…)

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Cover every possibilityCover every possibility Well, must have every possibility out of every Well, must have every possibility out of every

statestate In this case, just two: X = 0 or 1In this case, just two: X = 0 or 1 You fill in other casesYou fill in other cases

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Fill inFill in

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Full AnswerFull Answer

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State MinimizationState Minimization When we make state diagram, do we need all When we make state diagram, do we need all

those states?those states? Some may be redundantSome may be redundant State minimization procedures can be usedState minimization procedures can be used

Is a tough problem (NP-complete)Is a tough problem (NP-complete)but pretty good algorithms existbut pretty good algorithms existexact and approximateexact and approximate

We wonWe won’’t cover in this courset cover in this course

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ReadingReading Read 3.4-3.6Read 3.4-3.6 Might be good to look at Chapter 4 (Verilog Might be good to look at Chapter 4 (Verilog

only)only)