1 iii-v mos: record-performance thermally-limited devices, prospects for high-on-current steep...
TRANSCRIPT
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III-V MOS: Record-Performance Thermally-Limited Devices, Prospects for High-On-Current Steep Subthreshold Swing Devices Mark Rodwell, UCSB
IPRM/ISCS Conference, June 30-July , 2015, UCSB
III-V MOSC.-Y. Huang, S. Lee*, A.C. Gossard, V. Chobpattanna, S. Stemmer, B. Thibeault, W. Mitchell : UCSB
Low-voltage devices P. Long, E. Wilson, S. Mehrotra, M. Povolotskyi, G. Klimeck: Purdue
Now with: *IBM, **Intel
2
Why III-V MOS ?
III-V vs. Si: Low m*→ higher velocity. Fewer states→ less scattering → higher current. Can then trade for lower voltage or smaller FETs.
Problems: Low m*→ less charge. Low m* → more S/D tunneling.Narrow bandgap→ more band-band tunneling, impact ionization.
3
Reducing leakage: Vertical spacer, Ultra-thin channel
*Heavy elements look brighterCourtesy of S. Kraemer (UCSB) Lee et al., 2014 VSLI Symposium
Vertical Spacer
N+ S/D
4
Reducing leakage: Vertical spacer, Ultra-thin channel
10 100
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
S. Lee, VLSI 2014 J . Lin, IEDM 2013 T. Kim, IEDM 2013 Intel, IEDM 2009 J . Gu, IEDM 2012 D. Kim, IEDM 2012
I on (
mA
/m
)
Gate Length (nm)
VDS
= 0.5 V
Ioff
=100 nA/m
S. Lee et al., VLSI 2014
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.510-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
DIBL = 76 mV/V
VT = -85 mV at 1 A/m
SSmin
~ 72 mV/dec. (at VDS
= 0.1 V)
SSmin
~ 77 mV/dec. (at VDS
= 0.5 V)
Lg = 25 nm
VDS = 0.1 to 0.7 V
0.2 V increment
Cu
rre
nt
De
ns
ity
(mA
/m
)
Gate Bias (V)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0
0.2
0.4
0.6
0.8
1.0
1.2
Cu
rren
t D
ensi
ty (
mA
/m
)
Drain Bias (V)
Ron
= 303 Ohm-m
at VGS
= 0.7 V
VGS
= -0.4 V to 0.7 V
0.1 V increment
0.01 0.1 160
70
80
90
100
110
120 [2] [4] [3] [7] [1] [6] [5]
Solid: VDS
= 0.5 V
Open: VDS
= 0.1 V
Gate Length (m)
SS
min (
mV
/dec
.)
This work
[1] Lin IEDM 2013,[2] T.-W. Kim IEDM 2013,[3] Chang IEDM 2013,[4] Kim IEDM 2013[5] Lee APL 2013 (UCSB), [6] D. H. Kim IEDM 2012,[7] Gu IEDM 2012,[8] Radosavljevic IEDM 2009
5
Off-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
-0.2 0.0 0.2 0.410-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
IG
SS ~ 60 mV/decat VDS=0.1 V
Cu
rre
nt
De
ns
ity
(mA
/m
)Gate Bias (V)
ID
-0.2 0.0 0.2 0.4
IG
SS ~ 64 mV/decat VDS=0.1 V
Gate Bias (V)
ID
5.0 nm InAs 2.5 nm InAs
0.01 0.1 160
70
80
90
100
110 5.0 nm InAs 2.5 nm InAs
Open: VDS
= 0.1 V
Solid: VDS
= 0.5 V
Gate Length (m)
SS
min (
mV
/dec
)
Better SS at all gate lengths Better electrostatics (aspect ratio) and reduced BTBT (quantized Eg)
~10:1 reduction in minimum off-state leakage~5:1 increase in gate leakage increased eigenstate
Lg =500 nm Lg =500 nm
6
On-state comparison: 2.5 nm vs. 5.0 nm-thick InAs channel
0.01 0.1 10.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8InAs channel thickness 2.5 nm 5.0 nm
VDS
= 0.5 V
Gate Length (m)
Pea
k g
m (
mS
/m
)
0 1 2 3 4 5 6 70
200
400
600
800
1000
1200
x 1012
eff (c
m2 /
s-V)
Carrier Density (/cm2)
2.5 nm InAs 5.0 nm InAs
-0.2 0.0 0.2 0.4 0.60.0
0.5
1.0
1.5
2.0
2.5
Cox
= 4.2 F/cm2
EOT= 0.8 nm
W/L= 25m/21 m
Freq: 200kHz
2.5 nm InAs 5.0 nm InAs
Ga
te C
ap
ac
ita
nc
e (F
/cm
2 )
Gate Bias (V)
0
1
2
3
4
5
6
7
x 10
12
Car
rier
Den
sity
(/c
m2 )
0.4
0.2
-0.2
0.0
-0.4
-0.6
0.6
0.8
EF
E1En
erg
y (e
V)
Position (nm)10 20 30
EF
E1
Position (nm)10 20 30
~1.25 nm ~2.5 nm
2.5 nm thick 5 nm thick
1D-Possion Schrodinger solver(coded by W. Frensley, UT Dallas)
7
ZrO2 vs. HfO2: Peak gm, SS, split-CV, and mobility
0.01 0.1 10.0
0.4
0.8
1.2
1.6
2.0
2.4
0425A1 (30A ZrO2) 0425A2 (30A HfO2) VLSI (30A ZrO2)
VDS
= 0.5 V
Gate Length (m)
Pea
k g
m (
mS
/m
)
0.01 0.1 1
60
65
70
75
80
85
90 VLSI (30A ZrO2) 0425A1 (30A ZrO2) 0425A2 (30A HfO2)
Open: VDS
= 0.1 V
Solid: VDS
= 0.5 V
Gate Length (m)
SS
min (
mV
/dec
)
0.0 0.2 0.4 0.60.0
0.5
1.0
1.5
2.0
2.5W/L= 25m/21 m
Freq: 200kHz
ZrO2 HfO2
Ga
te C
ap
ac
ita
nc
e (F
/cm
2)
Gate Bias (V)
0
1
2
3
4
5
6
7
x 10
12
Car
rier
Den
sity
(/c
m2 )
7(1) ZrO2 higher capacitance than HfO2 , (2) ZrO2 results, low SS, are reproducible
Comparison: two process runs ZrO2 , one run HfO2 , both 2nm (on 1nm Al2O3)
8
Double-heterojunction MOS: 60 pA/mm leakage
• Minimum Ioff~ 60 pA/μm at VD=0.5V for Lg-30 nm• 100:1 smaller Ioff compared to InGaAs spacer• BTBT leakage suppressedisolation leakage dominates
Lg-30nm
C. Y. Huang et al., IEDM 2014
Lg-30nm
9
12 nm Lg III-V MOS
N+InGaAs
InP spacer
InAlAs
Barrier
Lg~12nm
~ 8nm
tch~ 2.5 nm(1.5/1 nm InGaAs/InAs)
Top View
Ni
Cross-setion
N+InP
10
ID-VG and ID-VD curves of 12nm Lg FETs
0.0 0.2 0.4 0.6 0.80.0
0.2
0.4
0.6
0.8
1.0
gm (m
S/m
)I D (m
A/
m)
VGS
(V)
0.0
0.4
0.8
1.2
1.6
2.0
2.4V
DS = 0.1 to 0.7 V,
0.2 V increment
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.70.0
0.5
1.0
1.5
I D (m
A/
m)
VDS
(V)
Ron
= 302 Ohm-m
at VGS
= 1.0 V
VGS
= -0.2 V to 1.2 V
0.2 V increment
-0.2 0.0 0.2 0.4 0.6 0.810-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
101
SS ~ 107.5 mV at V
DS=0.5 V
SS ~ 98.6 mV at V
DS=0.1 V
VDS
= 0.1 to 0.7 V
0.2 V increment
I D, |I G
| (m
A/
m)
VGS
(V)
Ioff~1.3 nA/μm Ion~1.1 mA/μm
Ion/Ioff > 8.3∙105
Lg-12nm
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-0.2 0.0 0.2 0.4 0.60.0
0.5
1.0
1.5
2.0
2.5
Cox
= 4.2 F/cm2
EOT= 0.8 nm
W/L= 25m/21 m
Freq: 200kHz
2.5 nm InAs 5.0 nm InAs
Ga
te C
ap
ac
ita
nc
e (F
/cm
2 )
Gate Bias (V)
0
1
2
3
4
5
6
7
x 10
12
Car
rier
Den
sity
(/c
m2 )
Mobility extraction at Lg-25 µm long channel FETs
0.0 0.2 0.4 0.6 0.8 1.00.0
0.5
1.0
1.5
2.0
2.5
3.0
Carrier d
ensity (10
12 cm-2)
Cac
c (
F/c
m2 )
VGS
(V)
0
2
4
6
8
10V
DS = 0.1 to 0.7 V
0.2 V increment
0 1 2 3 4 5 60
100
200
300
400
500
Mobility
(cm
2 /Vs
)
Carrier density (cm-2)
VDS
= 25 mV to 50 mV
Mobility~ 250 cm2/V s∙
Mobility~ 280 cm2/V s∙
Freq: 200 kHz
EOT~ 0.9~1 nm
This work InAs channel
1.5/1 nm InGaAs/InAs
1.5/1 nm InGaAs/InAs
m*, RS/D more important!0 1 2 3 4 5 6 7
0
200
400
600
800
1000
1200
x 1012
eff (c
m2 /s-
V)
Carrier Density (/cm2)
2.5 nm InAs 5.0 nm InAs
12
Steep FETs
13
Tunnel FETs: truncating the thermal distribution
Source bandgap truncates thermal distribution
J. Appenzeller et al., IEEE TED, Dec. 2005
T-FET
Normal
Must cross bandgap: tunnelingFix (?): broken-gap heterojunction
14
Tunnel FETs: are prospects good ?
Useful devices must be small
Quantization shifts band edges→ tunnel barrier
Band nonparabolicity increases carrier masses
Electrostatics: bands bend in source & channel
What actual on-current might we expect ?
15
Tunneling Probability
barrier
barrier
*2 where),2exp(
barrier) square (WKB,y Probabiliton Transmissi
EmTP
barrier thick 4nm afor %1
barrier thick 2nm afor %10
barrier thick 1nm afor %33
:Then
eV 2.0 ,06.0* :Assume 0
P
Emm b
For high Ion, tunnel barrier must be *very* thin.
~3-4nm minimum barrier thickness:P+ doping, body & dielectric thicknesses
16
T-FET on-currents are low, T-FET logic is slow
-1.5
-1
-0.5
0
0.5
1
1.5
2
5 10 15 20 25
En
ergy
, eV
position, nm10-3 10-2 10-1 100
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
Transmission
En
ergy
(eV
)
3.0%
NEMO simulation: GaSb/InAs tunnel finFET: 2nm thick body, 1nm thick dielectric @ er=12, 12nm Lg
10-5
10-4
10-3
10-2
10-1
100
101
102
0 0.1 0.2 0.3 0.4 0.5 0.6
dra
in c
urre
nt,
A/m
gate-source bias, volts
60mV/dec.
10 mA/mm
Experimental: InGaAs heterojunction HFET;Dewey et al, 2011 IEDM,2012 VLSI Symp.
~15 mA/mm @0.7V
Low current→ slow logic
17
Resonant-enhanced tunnel FETAvci & Young, (Intel) 2013 IEDM
2nd barrier: bound state
dI/dV peaks as state aligns with source
improved subthreshold swing.
Can we also increase the on-current ?
18
Electron anti-reflection coatings
Tunnel barrier:transmission coefficient < 100%reflection coefficient > 0%want: 100% transmission, zero reflectionfamiliar problem
Optical coatingsreflection from lens surfacequarter-wave coating, appropriate nreflections cancel
Microwave impedance-matchingreflection from loadquarter-wave impedance-matchno reflectionSmith chart.
19
T-FET: single-reflector AR coating
Peak transmission approaches 100%
Narrow transmission peak; limits on-current
10-3 10-2 10-1 100-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
TransmissionE
ner
gy(e
V)
TFETTFET+ one barrier
10-5
10-4
10-3
10-2
10-1
100
101
102
0 0.1 0.2 0.3 0.4 0.5
dra
in c
urre
nt,
A/m
gate-source bias, volts
60mV/dec.
TFET+one barrier
Can we do better ?
20
Limits to impedance-matching bandwidth
-7
-6
-5
-4
-3
-2
-1
0
1
0 5 10 15 20
Tra
nsm
issi
on,
dB
Frequency, GHz
1, 2, 3 sectionsMicrowave matching:More sections→ more bandwidthIs there a limit ?
Bode-Fano limitsR. M. Fano, J. Franklin Inst., Jan. 1960
Bound bandwidth for high transmissionexample: bound for RC parallel load→Do electron waves have similar limits ?
0
2||||
1ln
RCd
Yes ! Schrödinger's equation is isomorphic to E&M plane wave.Khondker, Khan, Anwar, JAP, May 1988
T-FET design→ microwave impedance-matching problemFano: limits energy range of high transmissionDesign T-FETs using Smith chart, optimize using filter theoryWorking on this: for now design by random search
)/*)(/()( wherepower,currenty probabilit , , , / xjmxIVfhE *
21
T-FET with 3-layer antireflection coating
-1.5
-1
-0.5
0
0.5
1
1.5
2
5 10 15 20 25 30 35
En
ergy
, eV
position, nm10-3 10-2 10-1 100
0.1
0.15
0.2
0.25
Transmission
En
ergy
(eV
) 3-layer0-layer
10-5
10-4
10-3
10-2
10-1
100
101
102
0 0.1 0.2 0.3 0.4 0.5 0.6dr
ain
curr
ent,
A/m
gate-source bias, volts
P-GaSb/N-InAs tunnel FET
single layer
triple layer60mV/dec.
Interim result; still working on design
Simulation
22
Source superlattice: truncates thermal distribution
Gnani, 2010 ESSDERC
M. Bjoerk et al., U.S. Patent 8,129,763, 2012. E. Gnani et al., 2010 ESSDERCProposed 1D/nanowire device:
Gnani, 2010 ESSDERC: simulation
23
Planar (vs. nanowire) superlattice steep FETLong et al., EDL, Dec. 2014
Planar superlattice FETsuperlattice by ALE regrowtheasier to build than nanowire (?)
Performance (simulations):~100% transmission in miniband.0.4 mA/mm Ion , 0.1mA/mm Ioff ,0.2V
Ease of fabrication ?Tolerances in SL growth ?Effect of scattering ?
simulation
24
(backup slides follow)