1 system-level power estimation and optimization 2005.07.08 chong-min kyung kaist
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System-level Power Estimationand Optimization
2005.07.08Chong-Min Kyung
KAIST
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Contents
Introduction System-level Power Estimation System-level Power Optimization
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Introduction
Power classification
Static power≈ leakage power
Dynamic power Switching power Short-circuit power Glitch power
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Introduction
Power calculation Static Power
Ptotal_leakage = ∑ Pcell_leakage
Dynamic Power Pinternal = Func (Cload,TRinput,output)
TR: toggle rate Pglitch = V2
dd ∑(Cloadnet * fglitch * τ ) fglitch: the frequency of glitch τ : the factor of the width of glitch
Pswitching = ½V2dd ∑(Cload * TRoutput)
Ratio > 0.1um: switching power: 70~90% < 0.07um: leakage power: > 50% Data intensive application
Switching power is a dominant factor.
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Introduction
Opportunities for power reduction
For low power design1. Power model generation2. Power estimation3. Power optimization
Commercial toolAcademic research
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System-level Power Estimation
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Contents
Power Model Generation Analytical Method Empirical Method
System-level Power Estimation Hardware Power Estimation Software Power Estimation Bus Power Estimation
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Power Model Generation
1. Analytical method Use average values of design parameters without
different circuit styles, clock strategies and layout techniques consideration
Average capacity, equivalent gate count, primary input number, etc.
Mainly used for behavior-level power estimation when there is no information about technology library and
implementation information Very low accuracy
2. Empirical method Use the parameters measured by existing
implementations2-1. Fixed-activity model2-2. Activity-sensitive model
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Power Model Generation
2-1. Fixed-activity model Use data sheet of a specific hardware block Pprocessor = Cprocessor x VDD
2 x freq Cprocessor = Pdata_sheet / (Vdata_sheet
2 freqdata_sheet) Low accuracy Mainly used for coarse-grained system-level power estimation
2-2. Activity-sensitive model Use signal activity or its statistics which depends on testbench Transition-sensitive model
Power model is a Look-Up Table (LUT). Very high accuracy
Statistical activity model Power model is a LUT or an equation. High accuracy
Current
input vector
Previous
input vector
SwitchCapacitance
(pF)
Index
Cap2n
-111 … 11n11 … 1n
………
Cap101 … 1n01 … 0n
Cap001 … 0n01 … 0n
),,( outinin DDPfP
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Macro Modeling Method
Macro modeling method Raise abstraction of power model by characterizing macro cell Mainly used to reduce power model complexity in activity-sensiti
ve power model generation Macro cell
32-bit adder, multiplier, MUX, etc. Reduced computation complexity at the cost of accuracy Macro cell characterization
Synthesize macro cell with basic cell library Estimate power value of macro cell with various testbench Generate power model and reduce its complexity
This concept can be used for raising abstraction of power model in hardware or software-level power estimation.
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Macro Modeling Method
Power model of macro modeling method Statistical activity model LUT-based model
For each bus component, build 3-D LUT (with axes of P in, Din, Dout)
Fill power value at each point (Pin, Din, Dout) Requires a lot of memory space
Equation-based model Build a polynomial approximating power consumption. From a large number of input patterns, perform analysis to determi
ne the coefficients. Requires little memory space
),,( outinin DDPfP Pin: average input signal probabilityDin : average input switching activityDout: average output zero delay switching activity
Pin: average input signal probabilityDin : average input switching activityDout: average output zero delay switching activity
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System-level Power Estimation
Estimation speed and power model Trade-off between estimation speed and accuracy of
power model
Abstraction of power estimation System-level power estimation Software-level power estimation Hardware-level power estimation
Behavior-level, RT-level, gate-level, circuit-level
Relativepower results
Absolutepower results
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System-level Power Estimation
System-level power estimation Relative value of power consumption is important.
Objective Power profiling and design exploration
System-level power estimation is composed of1. Hardware power estimation2. Software power estimation in processor3. Bus power estimation
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Hardware Power Estimation
RT-level power estimation Dynamic simulation-based power estimation with coarse-grained
net model from power macro model database and testbench
Macro block
Synthesiscondition
Synthesis
Gate-level design
Gate-level power estimation
Characterization
RT-level design
Fast synthesiswith macro block
Targetlibrary
RT-level power estimation
Testbench
Powerreport
Characterization process Estimation process
Power modeldatabase
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Hardware Power Estimation Tool
There are some commercial tools for hardware power estimation RT-level
Synopsys Power CompilerTM
Gate-level Synopsys Prime PowerTM, Synopsys Power CompilerTM
Circuit-level SPICE, Synopsys PowerMillTM, Cadence VoltageStormTM
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Software Power Estimation
Estimation Processor is too complex to estimate in RT-level. Power consumption is related to each instruction and instructio
n sequence. Estimation method
Power model is added to ISS for instruction-level power profiling.
Bi: energy consumption of inst. i
Ni: number of execution of inst. i
Oij: energy consumption when inst. i is followed by inst. j
Nij: number of pair inst. i and inst. j
Sk: other inst. Effect such as cache misses, pipeline stall, etc.
i ji k
kjijiii SNONBE,
,, )()(
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Software Power Estimation
Power model Instruction-level power model Inter-instruction effect consideration Dynamic effect (cache miss, branch prediction, etc)
Power modeling method1) White-box approach2) Black-box approach
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White-box Approach
Power model Activity-sensitive model
Characterization Use macro modeling method Process
Run gate-level simulation Find predominant parameter Reduce power model complexity
Simple equation or reduced LUT Make instruction-level power model
Accuracy is degraded and estimation speed is increased by reducing the power model complexity.
Accuracy SpeedHigh
Low
Low
High
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Black-box Approach
Characterization flow Measurement Characterization
V : Oscilloscope
Rr V
: Ammeter principle ( r << R )
V
I(t)
Characterization
Measurement
Instruction-levelPower Model
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Black-box Approach Measurement
By current measurement of real chip Power model
Activity-sensitive power model Statistical activity model
Characterization process Current is estimated using real chip with multiple iterations
of subroutine Compare measured value with ISS including dynamic
effects Find a power equation which is similar to the measured
power graph Decide coefficients of power equation by experimental
iteration It is important to find the closest equation to the
measurement results.
21R. Muresan and C. Gebotys,“Current dynamics-based macro-model for power simulation in a complex VLIW DSP processor”,IEE proc.-Comput. Digit. Tech., 2002
Black-box Approach
Measurement method Program under measurements are isolated by using
interrupt signal, NOP instruction and processor wait state for finding exact measurement position and for synchronization.
Pulse/Pattern Generator
Digital Sampling Oscilloscope
Target Chip underMeasurement
synchronization signal
clock
Interruptsignal
currentsignal
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Software Power Estimation Toolfor Research Purpose
Main memory
I Cache D Cache
Cache/bus simulator
RTL power estimation interface
2.0u5.0v
0.8u3.3v
2.0u5.0v
...
IF ID EXE MEM WB
SimplePower core
SimplePower Functional simulator
SimplePower core based on SimpleScalar ISA
Power model Activity sensitive power model Direct simulation and profiling based
on input transitions Generate switch capacitance tables
Current input vector
Previousinput vector
SwitchCapacitance
(pF)
Index
Cap2n
-111 … 11n11 … 1n
………
Cap101 … 1n01 … 0n
Cap001 … 0n01 … 0nImplementation-based
signal generation
Cycle-accurateactivation information
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Software Power Estimation Tool for Research Purpose
Cycle level performance simulator
Parameterizable power model
BinaryHardware
Config
Performance estimate
Power estimate
Wattch Architecture-level power estimation Functional simulator
SimpleScalar: cycle-level performance simulator Power model
Fixed activity power model Categories
Array structure Fully associative CAM Combinational logic and wires Clocking logic
Example: Array structure Power = C1 + C2 * A + C3 * B
A: Bit line number, B: Word line number C1: Diffusion cap., C2: Gate cap.,
C3: Metal cap.
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Bus Power Estimation
Power consumed on the bus consists of two parts Bus component power
Power consumed internally in the bus components Arbiter, decoder, muxes
Interconnection power Power consumed on the bus wires that connect the master and sla
ve interfaces and the bus components Address bus, data bus, control signals
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Bus Component Power Estimation
At System level, only the structural information about bus architecture can be obtained. Bus interconnection Bus width
Global bus power model is used for estimation Characterized power model of bus component is in the
global bus power model Arbiter, decoder, multiplexer Behavior, FSM
ProcessorGlobal Bus
Power Model
bus
IP # 1IP # 2Memory
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Bus Component Characterization
Macro model Pre-calculated power cubic Useful to apply on system level power estimation.
Input parameter of the macro models Data and address bus width, or the operating
frequency The number of masters and slaves Input/output data characteristics
The switching activity, the probability of signal or the Hamming distance of two successive data
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Bus Power Analysis
AMBA AHB bus power analysis A standard for on-chip communication
Power analysis process Bus structure decomposition
Arbiter Decoder Multiplexer
Build macro model of eachcomponent
Bus behavior decomposition and build power FSM IDLE, READ, WRITE, and IDLE with handover
Monitor bus signal activity Power analysis through power FSM
Master#1
Master#2
Master#3
Arbiter Slave#1
Slave#2
Slave#3
MUX
MUX
Decoder
Global bus power model
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Interconnection Power Estimation
Power consumption on each wire P = ½ Vdd
2 · C · f ·α
Vdd : voltage swing between the logic level 1 and 0. C : capacitance of the wire. f : clock frequency. α : switching activity.
Vdd and f is given as fixed value. We need to find C and α.
C can be obtained from wire capacitance model. α can be obtained from system level simulation.
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Interconnection Power Estimation
Wire capacitance model
*
εox : constant, 3.45 x 10-13F/cm, permittivity of SiO2
xint : oxide thickness underneath the interconnect W : interconnect width L : interconnect length
W, xint can be obtained from the technology parameter. L can be estimated from the area of the chip
(where A is area of the chip)
LW
x
W
x
x
WC ox ])1(44.042.2[ 6intint
int
AL
* J. P. Uyemura, ‘Circuit Design for CMOS VLSI’ Kluwer Academic Publishers 1992.
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Interconnection Power Estimation
Switching activity model Switching activity can be obtained from bus
transactions. Bus model monitors bus transition and counts bus
switching.
CPU
Busmodel
System level simulation
mem
DSP IP
Monitoring bus transition
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Bus Power Estimation
Power estimation Application example is simulated in system level
simulator. Power estimator reports power consumption using the
power model of the bus components and interconnection.
Monitored values in the bus transition are used as the input of the power estimator.
CPU
Busmodel
System level simulator
mem
DSP IP
PowerEstimator