1 unit-2‘1’ then the system adhering to this is called negative logic q12. give the differences...

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Digital Logic Design (REC-301) By: Navneet Pal ( Assistant Professor)

UNIT-2 Content

Combinational Logic & Combinational Circuits

Analysis Procedure

Design procedure

Binary adder -subtractor

Decimal adder

Binary multiplier

Magnitude comparator

Multiplexers

Demultiplexers

Decoders

Encoders.

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Q1. What are combinational circuits? Ans: A combinational circuit consists of logic gates whose outputs at any time are determined from the present combination of inputs. A combinational circuit performs an operation that can be specified logically by a set of Boolean functions. It consists of input variables, logic gates, and output variables. Q2. Give the design procedures for the designing of a combinational circuit. Ans: The procedure involves the following steps, • From the specification of the circuit, determine the required number of inputs and outputs and assign a symbol to each.

• Derive the truth table that defines the required relationships between inputs and outputs.

• Obtain the simplified Boolean functions for each output as a function of the input variables.

• Draw the logic diagram and verify the correctness of the design.

Q3. Define half adder. Ans A combinational circuit that performs the addition of two bits is called a half adder. A half adder needs two binary inputs and two binary outputs. The input variables designate the augend and addend bits; the output variables produce the sum and carry Q4. Define magnitude comparator Ans: A magnitude comparator is a combinational circuit that compares two numbers, A and B, and determines their relative magnitudes. The outcome of the comparison is specified by three binary variables that indicate whether a>b, A = b, or A < B.

Q5. What are decoders?Give an application. (NOV/DEC 2014) Ans: A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. If the n bit coded information has unused combinations, he decoder may have fewer than 2n outputs. The decoders are used in code converters, implementation of combinational circuits, address decoding, BCD to 7- segment decoder. Q6. Define priority encoder Ans: A priority encoder is an encoder circuit that includes the priority function. The operation of priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. Q7. Define multiplexer. Give an application. Ans: A multiplexer is combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input lines and n selection lines whose bit combinations determine which input is selected. They can be used as a data selector to select one out of many data inputs, to implement combinational logic circuit, in time multiplexing systems, in frequency multiplexing systems, in data acquisition systems Q8. What is the function of a multiplexers select inputs?

Ans :The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n

input lines and n selection lines whose bit combinations determine which input is selected

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Q9. What is a look ahead carry adder? Ans: The carry propagation time is a limiting factor on the speed with which two numbers are added in parallel. The most widely used technique employs the principle of look-ahead carry adder. Were in the final carry is expressed in terms of the initial carry and is designed such that it does not depend on the intermediate carry values. Q10. What is positive logic system? Give an example. Ans: When high voltage or more positive voltage level is associated with binary ‘1’ and while the low or less positive level is associated with binary ‘0’ then the system adhering to this is called positive logic. Q11. Define Negative Logic. Ans: When high voltage level is associated with binary ‘0’ and while the low level is associated with binary ‘1’ then the system adhering to this is called negative logic Q12. Give the differences between DMUX and MUX) Ans:

S.No MULTIPLEXER DEMULTIPLEXER

1. It has 2n inputs it has 1 input

2. It has 1 output It has 2n outputs

3. It is also called as data selector

It is also called as data distributor

4. It is used at the input side

It is used at the output side

Q13. What is Encoders. Explain with Decimal to BCD Encoder Ans: An encoder produces a digital code which depends on which one of its input is activated

Only one of M inputs is activated at a time

Encoder outputs a N-bit output code

Always: 2N M

Example 4-Line to Binary Encoder:

o 4 inputs o 2 outputs

The logic diagram can be generated using formal methods:

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S0 En

c S1

S9

B0

B3

Y = D + C

And similarly X = D + B

A

B

C

D

X

Y

Application

Decimal to BCD Encoder:

10 inputs

4 outputs

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Q14: Explain Decoder with Example

Ans: An decoder activates only one of its outputs depending on the binary code provided as input

Decoder receives a N-bit input code

Only one of M outputs is activated at a time

Always: 2N M Example

Binary to 4-Line Decoder:

o 2 inputs o 4 outputs

The logic diagram can be generated using formal methods: Implementation

X

Y

A

B

C

D

Application BCD to Decimal Decoder

4 inputs 10 outputs

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Q15 implement BCD to 7 Segment Deoder

Ans:

Horizontal segments: a, c, f a => 0, 2, 3, 5, 6, 7, 8, 9 c => 2, 3, 4, 5, 6, 8, 9 f => 0, 2, 3, 5, 6, 8, 9

Minimisation

DBBDCAa

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Minimisation

CBDCCBAc

Minimisation

DBCBDCDCBAf

Implementation

A

B

C

D

a

Implementation (with NAND gates)

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Q16 Explain Multiplexer

Ans: A multiplexer selects one of its inputs to direct to the output depending on the binary

code provided at the select inputs

Multiplexer receives a M-bit selection code

Only one of N inputs is directed at the output

Always: 2M = N

Example

Two-channel two-bit Multiplexer 4 inputs 1 select input 2 outputs

After minimisation, results: Z0 = A0 S’ + B0 S Z1 = A1 S’ + B1 S

2-channel

MUX

2-channel

MUX

A0

A1

B0

B1

Z0

Z1

S

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I

O0

O1

ON-1

S0 S1 SM-1

DMUX

Q17 Explain Demultiplexer with example

Ans: A demultiplexer transfers its input to one of the outputs depending on the binary

code provided at the select inputs

o Demultiplexer receives a M-bit selection code

o The input is directed to one of the N outputs

o Always: 2M = N

Eight-channel Demultiplexer

o 1 input o 3 select inputs o 8 outputs

I

S0

S1

S2

O0

O1

O2

O3

O4

O5

O6

O7

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12


13


14


15


16


17


18


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Q24: Design a Binary to Gray Code converter

Ans: The logical circuit which converts binary code to equivalent gray code is known as binary to gray code converter. The gray code is a non weighted code. The successive gray code differs in one bit position only that means it is a unit distance code. It is also referred as cyclic code. It is not suitable for arithmetic operations. It is the most popular of the unit distance codes. It is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the axis. Reflection of Gray codes is shown below.

The 4 bits binary to gray code conversion table is given below,

That means, in 4 bit gray code, (4-1) or 3 bit code is reflected against the axis drawn after (24-1)th

or 8th row. The bits of 4 bit gray code are considered as G4G3G2G1. Now from conversion table,

From above SOPs, let us draw K-maps for G4, G3, G2 and G1.

https://www.electrical4u.com/gray-code-binary-to-gray-code-and-that-to-binary-conversion/

https://www.electrical4u.com/555-timer-and-555-timers-working/

https://www.electrical4u.com/555-timer-and-555-timers-working/

https://www.electrical4u.com/k-map/

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Q25: Design a Grey to Binary Code Converter Ans: In gray to binary code converter, input is a multiplies gray code and output is its equivalent binary

code.Let us consider a 4 bit gray to binary code converter.To design a 4 bit gray to binary code converter

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Q26: Design a circuit for 2-bit magnitude comparator

Ans: A magnitude digital comparator is a combinational circuit that compares two digital or binary numbers (consider A and B) and determines their relative magnitudes in order to find out whether one number is equal, less than or greater than the other digital number. A 2-bit comparator compares two binary numbers, each of two bits and produces their relation such as one number is equal or greater than or less than the other. The figure below shows the block diagram of a two-bit comparator which has four inputs and three outputs.The first number A is designated as A = A1A0 and the second number is designated as B = B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B) and L (L = 1 if A<B).

The truth table of this comparator is shown below which depicting various input and output states.

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The k-map simplification for the above truth table is as follows.

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Q27: Design Binary Multiplier

Ans: Binary multiplication process: A Binary Multiplier is a digital circuit used in digital electronics to multiply two binary numbers and provide the result as output. The method used to multiply two binary numbers is similar to the method taught to school children for multiplying decimal numbers which is based on calculating partial product, shifting them and adding them together. Similar approach is used to multiply two binary numbers. Long multiplicand is multiplied by 0 or 1 which is much easier than decimal multiplication as product by 0 or 1 is 0 or same number respectively. Figure 1 below shows the block diagram of a 2-bit binary multiplier. The two numbers A1A0 and B1B0 are multiplied together to produce a 4-bit output P3P2P1P0. (The maximum product term can be 3 * 3 = 9, which is 1001, a 4-bit number).

Let us take an example of multiplying two binary numbers as follows. The process is similar to multiplying two decimal numbers, with a difference that the resulting numbers are all binary.

110 = 6

X 011 = 3

---------------------------

1 1 0 ; 110 X 1

1 1 0 x ; 110 X 1

0 0 0 x x ; 110 X 0

------------------------------

1 0 0 1 0 =18

Now, we have seen that multiplying a number with binary ‘0’produces all zeroes, and with ‘1’ reproduces the number. So, multiplying two binary numbers is a straightforward job. It can be implemented without much difficulty using shifters, AND gates and adders. 2-bit binary multiplier circuit implementation: Let us implement a two bit binary multiplier. Let the two binary numbers be A1A0 and B1B0. The multiplication table will, then, look as: A1 A0

X B1 B0

-------------------------------------------------------------------

B0A1 B0A0

B1A1 B1A0 x

-------------------------------------------------------------------

P3 P2 P1 P0

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Thus, we get the partial products as:

P0 = A0*B0

P1 = A0*B1 xor A1 * B0 ; carry generated here goes to next stage

P2 = A1*B1 xor (A0*B1) * (A1*B0)

P3 = A1*B1 and (A0*B1) * (A1*B0)

Practice Questions

COMBINATIONAL CIRCUITS

1. For the given function, write the Boolean expression in product of maxterm form

f(a,b,c)= ∑m(2,3,5,6,7).?

2. What is a data selector?

3. Mention the uses of decoders.

4. What is a priority encoder?

5. Write the logic equation and draw the internal logic diagram for a 4 to 1 mux?

6. Expand the function f (A, B, C) =A +B’C to standard SOP form?

7. Using k-map find minimum sop for the function.

F (a, b, c) = ∑ m (0, 1, 5, 6, 7)

8. Implement the given function in 4:1 mux f= ∑m(0,1,3,5,6)

9. Design a half adder?

10. Draw a combinational logic circuit, which can compare whether two bits binary

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numbers are same or not?

11 . Design a half adder using NAND – NAND logic

12 . Design a 2-bit magnitude comparator?

13 Using 8 to 1mux, realize the Boolean function

T=F (w, x, y, z)= ∑ m (0,1,2,4,5,7,8,9,12,13)

14. Implement the Boolean function using 8:1 mux.

F (A, B, C, D) =A’BD’+ACD+B’CD+A’C’D.

15. Explain the operation of 4 to 10 decoder.

16. Implement the following multiple output combinational logic circuit using a 3-to8

decoder.

F1=∑ m (1, 2, 3, 5, 7)

F2=∑ m (0, 3, 6)

F3=∑ m (0, 2, 4, 6)

17. Design a 4-bit adder /subtractor-using logic gates and explains its operation.

18. Construct a combinational circuit to convert BCD to EX-3 code.

19 . Design A Full Adder And A Full Subtractor.

20. Design A Full subtractor with using two half subtractor.

21. Design A Full Adder with using two half adder .

22. Design A Full Adder circuit with using two half adder circuit .

23. Design A Full subtractor circuit with using two half subtractor circuit.

24. Implement the given function in 4:1 mux f= ∑m(0,1,3,5,8)

25. Design a half adder using NAND – NAND logic.

26. Explain how a full adder can be built using two half adders.

27. Design a half adder using at most three NOR gates.

28. Using 8 to 1 multiplexer, realize the Boolean function

T = f(w, x, y, z) = Σ(0,1,2,4,5,7,8,9,12,13)

29. Draw the logic diagram of full subtractor and explain its operation.

30. Design a full adder circuit using only NOR gates.

1 unit-2‘1’ then the system adhering to this is called negative logic q12. give the differences...

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