1006clocklesschips

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ASEMINARREPORT

ON

CLOCKLESSCHIPS

COMPUTERSCIENCE&ENGINEERING


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ACKNOWLEDGEMENT

Attheoutset,Ithankthelordalmightyforthegrace,strengthandhopetomake

ourendeavorasuccess

WeexpressourdeepfeltgratitudetoDr.x ,HeadoftheDivisionofComputerScienceforhisconstantencouragement.

IamprofoundlygratefultoMr.x ,Lecturer,DepartmentofComputerScience, my mentor and seminar guide for his valuable guidance support,

suggestionsandencouragement.

Iwouldalsoliketothankourstaffcoordinator,Mr.x forhiswordsofsupport.

Further more I would like to thank all others, especially ourparents and

numerous friends. Thisproject would not havebeen a success without the

inspiration, valuable suggestions and moral support from the through out its

course


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ABSTRACT

Clockless chips are electronic chips that are not usingclock fortiming

signal.Theyareimplementedinasynchronouscircuits.Anasynchronouscircuit

isacircuitinwhichthepartsarelargelyautonomous.Theyarenotgovernedby

aclockcircuitorglobalclocksignal,butinsteadneedonlywaitforthesignals

that indicate completion of instructions and operations. These signals are

specified by simple data transfer protocols. This digital logic design is

contrastedwithasynchronouscircuitwhichoperatesaccordingtoclocktiming

signals.

Thetermasynchronouslogicisusedtodescribeavarietyofdesignstyles,

whichusedifferentassumptionsaboutcircuitproperties.These varyfromthe

bundleddelaymodel-whichuses'conventional'dataprocessingelementswith

completionindicatedbyalocallygenerateddelaymodel-todelay-insensitive

design-wherearbitrarydelaysthroughcircuitelementscanbeaccommodated.

The latter style tends to yield circuits which are larger and slower than

synchronous (orbundled data) implementations,but which are insensitive to

layoutandparametricvariationsandarethus"correctbydesign."

Unlike a conventionalprocessor, a clocklessprocessor (asynchronous

CPU) has no central clock to coordinate theprogress of data through the

pipeline.Instead,stagesoftheCPUarecoordinatedusinglogicdevicescalled

"pipeline controls" or "FIFO sequencers." Basically, thepipeline controller

clocksthenextstageoflogicwhentheexistingstageiscomplete.Inthisway,a

centralclockisunnecessary.Itmayactuallybeeveneasiertoimplementhigh

performancedevicesinasynchronous,asopposedtoclockedlogic.


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CONTENTS

1.INTRODUCTION 11.1Definition 1

1.2ClockConcept 2

2.CLOCKLESSAPPROACH 32.1ClockLimitations 3

2.1AsynchronousView 4

3.PROBLEMSWITHSYNCHRONOUSCIRCUITS 53.1Performance 5

3.2Speed 6

3.3PowerDissipation 6

3.4ElectromagneticNoise 7

4.ASYNCHRONOUSCIRCUITS 84.1ClocklessChipsImplementation 8

4.2ThrowingAwayGlobalClock 8

4.3StandardizeofComponents 9

5.HOWCLOCKLESSCHIPSWORKS 9

6.SIMPLICITYINDESIGN 126.1AsynchronousforHigherPerformance 15

6.2AsynchronousforLowPower 16

6.3AsynchronousforEMNandEmission 17

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7.APPLICATIONSOFCLOCKLESSCHIPS 177.1WearableComputers 17

7.2InfraredCommunicationReceiver 18

7.3InPagers 18

7.4FilterBankforDigitalHearing 18

8.CHALLENGES 20

9.CONCLUSION 21

10.REFERENCES 22

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LISTOFFIGURES

1. Figure1 3

2. Figure2 11

3. Figure3 15

4. Figure4 16

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1.INTRODUCTION1.1DEFINITION

Everyactionofthecomputertakesplaceintinysteps,eachabillionthof

a second long. A simple transfer of data may take only one step; complex

calculationsmaytakemanysteps.Alloperations,however,mustbeginandend

accordingtotheclock'stimingsignals.

Theuseofacentralclockalsocreatesproblems.Asspeedshaveincreased,

distributingthetimingsignalshasbecomemoreandmoredifficult.Present-day

transistorscanprocessdatasoquicklythattheycanaccomplishseveralstepsin

thetimethatittakesawiretocarryasignalfromonesideofthechiptothe

other.Keepingtherhythmidenticalinallpartsofalargechiprequirescareful

design and a great deal of electricalpower. Wouldn't itbe nice to have an

alternative?

Clocklessapproach,whichusesatechniqueknownasasynchronous logic,

differsfromconventionalcomputercircuitdesigninthattheswitchingonand

offofdigitalcircuitsiscontrolledindividuallybyspecificpiecesofdatarather

thanbyatyrannicalclockthatforcesallofthemillionsofthecircuitsonachip

tomarchinunison.Itovercomesallthedisadvantagesofaclockedcircuitsuch

asslowspeed,highpowerconsumption,highelectromagneticnoiseetc.

For these reasons the clockless technology is considered as the technology

which is going to drive majority of electronic chips in the coming years.

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1.2CLOCKCONCEPTThe clock is a tiny crystal oscillator that resides in the heart of every

microprocessor chip. The clock is what which sets thebasic rhythm used

throughout the machine. The clock orchestrates the synchronous dance of

electronsthatcoursethroughthehundredsofmillionsofwiresandtransistorsof

amoderncomputer.

Suchcrystalswhichtick upto2billiontimeseachsecondinthefastestof

today'sdesktoppersonalcomputers,dictatethetimingofeverycircuitinevery

oneofthechipsthatadd,subtract,divide,multiplyandmovetheonesandzeros

thatarethebasicstuffoftheinformationage.

Conventional chips (synchronous) operate under the control of a central

clock,whichsamplesdataintheregistersatpreciselytimedintervals.Computer

chipsoftodayaresynchronous:theycontainamainclockwhichcontrols the

timingoftheentirechips.

Oneadvantageofaclockisthat,theclocksignalstothedevicesofthechip

when to input or output. This functionality of the synchronous design makes

designingthechipmucheasier.Thecircuitwhichusesglobalclockcanallow

datatoflowinthecircuitinanymannerofsequenceandorderdoesnotmatter.

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Clock

(Frequency

Figure1

Thediagramaboveshowstheglobalclockisgoverningallcomponentsinthe

systemthatneedtimingsignals.Allcomponentsoperateexactlyonceperclock

tickandtheiroutputsneedtobereadyandnextclocktick.

2.CLOCKLESSAPPROACH2.1CLOCKLIMITATIONS

Thereareproblemsthatgoalongwiththeclock,however.

Clock speeds are now in the gigahertz range and there is not much roomfor

speedupbeforephysical realities start to complicate things. With a gigahertz

clockpoweringachip,signalsbarelyhaveenoughtimeto make itacrossthe

chipbeforethe nextclocktick.Atthispoint,speedup uptheclock frequency

couldbecome disastrous. This is whena chip thatis notconstrictedbyclock

speedscouldbecomeveryvaluable.

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Onecancreateaclockthatissofastanditsendsitstimingsignalstothe

logic circuits which are governedby the clock timing signals. These logic

circuitsaresupposedtorespondtoeverytickoftheclockandyetwhentheycan

compiletomatchthespeedthenlogiccircuitswillbenotoptimumaccordingto

thespeed ofclockand hencethe inputandoutputcango incorrect. Thiswill

resulthardwareproblemsinceonehastoassemblechipstoachievethespeedof

clockandhencemuchmorecomplicatedsituationarise.

2.2ASYNCRONOUSVIEWBy throwing out the clock, chip makers willbe able to escape from huge

powerdissipation.Clocklesschipsdrawpoweronlywhenthereisusefulwork

todo,enablingahugesavingsinbattery-drivendevices.

Like a team of horses that can only run as fast as its slowest member, a

clockedchipcanrunnofasterthanitsmostslothfulpieceoflogic;theanswer

isn'tguaranteeduntileverypartcompletesitswork.Bycontrast,thetransistors

onanasynchronouschipcanswapinformationindependently,withoutneeding

towaitforeverythingelse.Theresult?Insteadoftheentirechiprunningatthe

speed of its slowest components, it can run at the average speed of all

components.AtbothIntelandSun,thisapproachhasledtoprototypechipsthat

run two to three times faster than comparableproducts using conventional

circuitry.

Anotheradvantageofclocklesschipsisthattheygiveoffverylowlevelsof

electromagneticnoise.Thefastertheclock,themoredifficultitistopreventa

device from interfering with other devices; dispensing with the clock allbut

eliminates this problem. The combination of low noise and low power

consumptionmakesasynchronouschipsanaturalchoiceformobiledevices.

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3.2LOWSPEED

A traditional CPU cannot "go faster" than the expected worst-case

performanceofthesloweststage/instruction/component. Whenanasynchronous

CPUcompletesanoperationmorequicklythananticipated,thenextstagecan

immediately begin processing the results, rather than waiting for

synchronization with a central clock. An operation might finish faster than

normalbecauseofattributesofthedatabeingprocessed(e.g.,multiplicationcan

beveryfastwhenmultiplyingby0or1,evenwhenrunningcodeproducedbya

brain-dead compiler), orbecause of thepresence of a higher voltage orbus

speedsetting,oralowerambienttemperature,than'normal'orexpected.

3.3HIGHPOWERDISSIPATION

As we know that clock is a tiny crystal oscillator that keeps vibrating

during all time as long as the system ispower on, this lead into highpower

dissipationby the synchronous circuit since they use central clock in their

timings.Theclockitselfconsumesabout30percentofthetotalpowersupplied

tothecircuitandsometimescanevenreachhighvaluesuchas70percent.Even

if the synchronous system is not active at the moment still its clock willbe

oscillating and consumespowerthat is dissipated as heat energy. This makes

synchronous system morepower consumer and hence not suitable for use in

designofmobiledevicesandbatterydrivendevices.

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3.4HIGHELECTROMAGNETICNOISE

Since clock itself is crystal oscillator it is then associated with

electromagnetic waves. These wavesproduce electromagnetic noise due to

oscillations.Noisewillalsobeaccompaniedbyemissionspectra.Thehigherthe

speedofclockisthehighernumberofoscillationspersecondandthisleakhigh

valueofelectromagneticnoiseandspectraemission.Thisisnotagoodsignfor

designofmobiledevicestoo.

Apartfromtheproblemsabove,theclockissynchronouscircuitandglobally

distributed over the components which are obviously in running in different

speedandhencetheorderofarriveofthetimingsignalisnotimportant.Data

canbe received and transmitted in any form of order regardless of there

sequentialordertheyarriveatthefiststageofexecution.

The designing of clock frequency shouldbe so sophisticated since the

frequencyoftheclockisfixedandpoormarchofdesigncanresultproblemin

the reusability of resources and interfacing with mixed-time environment

devices.

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4ASYNCRONOUSCIRCUITS

Asynchronous circuits are the electronic digital circuits that are not

governbythecentralclockintheirtiminginsteadtheyarestandardizedintheir

installation and they use handshakes signals for communication to eachother

components. In this case the circuits are not tied up together and forced to

followtheglobalclocktimingsignalsbuteachandeverycomponentisloosely

andtheyrunataveragespeed.

Asynchronous is canbe achievedby implementing three vital techniques and

theseare:

4.1CLOCKLESSCHIPSIMPLEMENTATION

Inorderto achieve asynchronous as final goalone must implement the

electroniccircuitswithoutusingcentralclockandhencemakethesystemfree

fromtiedcomponentsobeyingclock.One trickytechnique isto useclockless

chipsinthecircuitdesign.Sincethesechipsarenotworkingwithcentralclock

andguaranteetofreedifferentcomponentsfrombeingtieduptogether.Nowas

components can run on their own differentperformance and speed hence

asynchronousisestablished.

4.2THROWINGAWAYGLOBALCLOCK

Thereisnowayonecansuccesstoimplementasynchronousincircuitsif

thereisglobalclockthatismanagingthewholesystemtimingsignals.Sincethe

clockisinstalledonlytoenablethesynchronizationofcomponents,bythrowing

awaytheglobalclockitispossible nowforcomponentstobecompletelynot

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synchronized and the communicationbetween them is onlyby handshaking

mechanism.

4.3STANDADISEOFCOMPONENTS

Insynchronoussystemallthecomponentsarecloseduptogetherastobe

managedbycentralclock.Synchronousnesscanbesplitupifthesecomponents

arenotboundtogetherandhencestandardizingthesecomponentsisoneofthe

alternatives.Hereallthecomponentsaregoingtobestandardinagivenrange

ofworkingperformanceandspeed.Thereisaveragespeedinwhichthedesign

ofsystemisdedicatedtocompileandtheworstcaseexecutionwillbeavoided.

5.HOWCLOCKLESSCHIPSWORKS

Beyond a new generation of design-and-testing equipment, successful

development of clockless chips requires the understanding of asynchronous

design.Suchtalentisscarce,asasynchronousprinciples flyinthe faceofthe

way almost every university teaches its engineering students. Conventional

chipscanhavevaluesarriveataregisterincorrectlyandoutofsequence;butin

aclocklesschip,thevaluesthatarriveinregistersmustbecorrectthefirsttime.

One way to achieve this goal is topay close attention to such details as the

lengthsofthewiresandthenumberoflogicgatesconnectedtoagivenregister,

therebyassuringthatsignalstraveltotheregisterintheproperlogicalsequence.

But that meansbeing far more meticulous about thephysical design than

synchronousdesignershavebeentrainedtobe.

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Analternativeistoopenupaseparatecommunicationchannelonthechip.

Clockedchipsrepresentonesandzeroesusinglowandhighvoltagesonasingle

wire, "dual-rail" circuits, on the other hand, use two wires, giving the chip

communicationspathways,notonlytosendbits,butalsotosend"handshake"

signals to indicatewhenwork hasbeencompleted. Fairadditionallyproposes

replacingtheconventionalsystemofdigitallogicwithwhatknownas"null

conventionlogic,"aschemethatidentifiesnotonly"yes"and"no,"butalso"no

answer yet"-a convenient way for clockless chips to recognize when an

operation has not yetbeen completed. All of these ideas and approaches are

differentenoughthatexecutingthemcouldconfoundthemindofanengineer

trained to design to thebeat of a clock. It's no surprise that the two newest

asynchronous startups, Asynchronous Digital Devices and Self-Timed

Solutions, arepopulating now, and clockless-chip research hasbeen goingon

thelongest.

Fora chip tobe successful, allthree elements-design tools, manufacturing

efficiencyandexperienceddesigners-needtocometogether.Theasynchronous

cadrehasverypromisingideas.

Thereisnowwayonecanobtainpureasynchronouscircuitstobeusedinthe

completedesignofthesystemandthisisoneofmajorbarrierofclockless

implementationbutthecircuitsweresuccessfullystandardizedandhencethey

donothavetobeinsynchronousmode.Andhencehandshakeswerethe

solutiontoovercomesynchronization.Onecomponentwhichneedsto

communicatewiththeotherusesthehandshakesignalstoachievethe

establishmentofconnectionandthenwithsetupthetimeatwhichisgoingto

senddataandattheothersideanothercomponentwillalsousethesamekindof

handshakestohardentheconnectionandwaitforthattimetoreceivedata.

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Handshakes

clock

SynchronousSystem(CentralizedControl) AsynchronousSystem(DistributedControl)

Interface

Figure2

Incircuitsimplementedbyclocklesschips,datadonothavetomoveatrandomandoutoforderasinsynchronousinwhichthemovementofdataisnosoessential.Inasynchronouscircuitsdataaretreatedasveryimportantaspectandhencedonotmoveatanytimetheyonlyandonlymovewhenarerequiredto move in case such as transmission between several components. Thistechnique has offered lowpower consumption and low electromagnetic noiseandalsotherewillofcoursebesmoothdatastreaming.

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6.SIMPLICITYINDESIGN

There innocomplexityofasimpledesignforclocklesschips.Theone

fundamentalachievementistothrowthecentralclockawayandstandardization

ofcomponentscanbeusedintensively.

Integratedpipelinemodeplaysanimportantroleintotalsystemdesign.

Thereareaboutfourfactorsregardingpipelineandtheseare:

1.Dominologic

2.Delayinsensitive

3.Bundledata

4.Dualrail

Domino logic is a CMOS-based evolution of the dynamic logic techniques

whichwerebasedoneitherPMOSorNMOStransistors.Itallowsarail-to-rail

logicswing.Itwasdevelopedtospeedupcircuits.

Inacascadestructureconsistingofseveralstages,theevaluationofeachstage

ripplesthenextstageevaluation,similartoadominofallingoneaftertheother.

ThestructureishencecalledDominoCMOSLogic.

Importantfeaturesinclude:

*TheyhavesmallerareasthanconventionalCMOSlogic.

* Parasitic capacitances are smaller so that higher operating speeds are

possible.

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*Operationisfreeofglitchesaseachgatecanmakeonlyonetransition.

* Only non-inverting structures are possible because of the presence of

invertingbuffer.

*Chargedistributionmaybeaproblem

Delayinsensitivecircuitisatypeofasynchronouscircuitwhichperforms

a logic operation often within a computingprocessor chip. Instead of using

clocksignalsorotherglobalcontrolsignals,thesequencingofcomputationin

delayinsensitivecircuitisdeterminedbythedataflow.

Typicallyhandshakesignalsareusedtoindicatethereadinessofsuchacircuit

toacceptnewdata(thepreviouscomputationiscomplete)andthedeliveryof

suchdatabytherequestingfunction.Similarlytheremaybeoutputhandshake

signalsindicatingthereadinessoftheresultandthesafedeliveryoftheresultto

thenextstageinacomputationalchainorpipeline.

Inadelayinsensitivecircuit,thereisthereforenoneedtoprovideaclocksignal

todetermineastartingtimeforacomputation.Instead,thearrivalofdatatothe

inputofasub-circuittriggersthecomputationtostart.Consequently,the next

computation can be initiated immediately when the result of the first

computationiscompleted.

The mainadvantage ofsuchcircuits is theirability to optimizeprocessing of

activities that can take arbitraryperiods of time depending on the data or

requestedfunction.Anexampleofaprocesswithavariabletimeforcompletion

wouldbemathematicaldivisionorrecoveryofdatawheresuchdatamightbein

acache.

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The Delay-Insensitive (DI)class is the mostrobustofallasynchronous

circuitdelaymodels.Itmakesnoassumptionsonthedelayofwiresorgates.In

this model all transitions on gates or wires mustbe acknowledgedbefore

transitioning again. This conditionstops unseentransitions fromoccurring. In

DIcircuitsanytransitiononaninputtoagatemustbeseenontheoutputofthe

gatebefore a subsequent transition on that input is allowed to happen. This

forcessomeinputstatesorsequencestobecomeillegal.ForexampleORgates

mustnevergointothestatewherebothinputsareone,astheentryandexitfrom

thisstatewillnotbeseenontheoutputofthegate.Althoughthismodelisvery

robust,nopracticalcircuitsarepossibleduetotheheavyrestrictions.Insteadthe

Quasi-Delay-Insensitive modelisthesmallestcompromisemodelyetcapableof

generating useful computing circuits. For this reason circuits are often

incorrectly referred to as Delay-Insensitive when they are Quasi-Delay-

Insensitive.

Dual rail is the technique employed to influence asynchronization of

circuitsby establishing two connections to any circuit that is in connection.

Hence itprovides one line for handshakes signals and the other for data

transmission.

Theproposedbundled-datapipelinesincludenoveldata-dependentdelay

lines with integrated control circuitry to efficiently implement speculative

completion sensing. The control circuits arebased on a novel control-circuit

templatethatsimplifiesthedesignofsuchnonlinearpipelines.Extensivepost-

layoutback-endtiminganalysiswasperformedtogainconfidenceinthetiming

margins as well as to quantifyperformance and energy. Comparison with a

synchronouscounterpartsuggeststhatourbestasynchronousdesignyields30%

higheraveragethroughputwithnegligibleenergyoverhead.

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6.1ASYNCRONOUSFOHIGHERPERFOMANCEInordertoincreasetheperformanceofthecircuit,thefollowingare

basicstobeimplements.

*Data-dependentdelays.

*Allcarrybitsneedtobecomputed.

Figure3

Thefigureshowfirstcircuitbeingnotasynchronousandthenthesecondshows

dualrailwitheverybittakenintocomputation.

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6.2ASYNCHRONOUSFORLOWPOWERPowerconsumptionisveryimportantaspectindesigninganymobileand

to increase thebattery capacity and life forbattery driven devices. Hence

asynchronization ofpower is completely inevitable to achieve a low level of

power dissipated. The circuit should consumepower only when and where

active.Restofthetimethecircuitreturnstoanon-dissipatingstate,untilnext

activation.

Thefigureshowshowpowerislessconfusedbyfirsttakingdownthefrequency

bydividingthegivefrequencytotwoandthenextoneshowasmanycircuits

are

cascaded

the

more

the

frequencyisdivided.

This

provides

a

crucial

reductiononpowerconsumption.

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6.3ASYNCRONOUSFORLOWNOISEAnysystemwithclockwillbehavingoscillationsinitandwillcreate

electromagneticnoiseandthisisthesourceoftheactualnoiseonehearsfrom

convectionalcomputers.Foreveryclockcycletherewillbespikeemittedand

emissionofrandomspectraisaccompaniedtogetherwithnoise.

Thisproblemisgreatlyreducedtosignificantconsiderablerangeby

discardingthecentralclockasexplainaboveandthespectraradiationaremuch

smootherinasynchronouscircuits.

7.APPLICATIONSOFCLOCKLESSCHIPS

Clocklesschipsareusedinotherapplicationsalsoonratherthanindesignof

computersandtheseare:

7.1WEARABLECOMPUTERS

Wearable computers are mobile computers that are worn on thebody.

Theyhavebeenappliedtoareassuchasbehavioralmodeling,healthmonitoring

systems, information technologies and media development. Government

organizations,military,andhealthprofessionalshaveallincorporatedwearable

computersintotheirdailyoperations.Wearablecomputersareespeciallyuseful

forapplicationsthatrequirecomputationalsupportwhiletheuser'shands,voice,

eyesorattentionareactivelyengagedwiththephysicalenvironment.

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7.1INFRAREDCOMMUNICATIONRECEIVER

Infrared(IR)radiationiselectromagnetic radiationwhosewavelengthis

longerthanthatofvisiblelight,butshorterthanthatofterahertzradiationand

microwaves. This hasbeen implemented in designing receivers that receive

transmitted data via infrared. Infrared communication receiver is one of

computerperipherals and since it has asynchronous in nature then clockless

chipsareimplementedforitsdesign.

7.2INPAGERS

A pager (sometimes called a beeper) is a simple personal

telecommunications device forshort messages.Aone-way numericpagercan

onlyreceiveamessageconsistingofafewdigits.Typicallyaphonenumberthat

theuseristhenexpectedtocall.Alphanumericpagersareavailable,aswellas

two-waypagersthathavetheabilitytosendandreceiveemail,numericpages,

andSMSmessages.Pagersconsistinglargelyofemergencyservicepersonnel,

medicalpersonnel,andinformationtechnologysupportstaff.

7.3FILTERBANKFORDIGITALHEARING

Afilterbankisanarrayofband-passfiltersthatseparatestheinputsignal

intoseveralcomponents,eachonecarryingasingle frequencysubbandofthe

originalsignal.Italsoisdesirabletodesignthefilterbankinsuchawaythat

subbands canbe recombined to recover original signal. The firstprocess is

calledanalysis,whilethesecond iscalled synthesis.Theoutputofanalysis is

referredas subbandsignalwithas manysubbands as there are filters in filter

bank.

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Thefilterbankservestoisolatedifferentfrequencycomponentsinasignal.

This is useful because for most applications some frequencies are more

important than others. For example these important frequencies canbe coded

withafineresolution.Smalldifferencesatthesefrequenciesaresignificantand

a coding scheme thatpreserves these differences mustbe used. On the other

hand, less important frequencies do not have tobe exact. A coarser coding

schemecanbe used,eventhoughsomeofthe finerdetailswillbe lost inthe

coding.

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8.CHALLENGES

1.Interfacingbetweensynchronousandasynchronous

Manydevicesavailablenowaresynchronousinnature.

Specialcircuitsareneededtoalignthem.

2.Lackofexpertise.

3.Lackoftools.

4.Engineersarenottrainedinthesefields.

5.Academically,nocoursesavailable

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9.CONCLUSION

Ashasbeenstudiedthatimplementationofclocklesschipin

asynchronouscircuithasmuchgreatadvantageoverclockedchips.Theobvious

reasonsfortheirsuperperformanceandaveragespeed,lowpowerconsumption,

lessheatandnoisegeneratedareingreatdemandofthecurrentmarketof

electronicandcomputingworld.Thisisaverynewareaofresearchanddesign

andtestingbutifmorescientistsandengineersarededicatedtothis,thenfor

suretyitthefuturetechnologyformobileelectronicdevices.

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10.REFERENCES1.ScanningtheTechnology:ApplicationsofAsynchronousCircuitsC.H.

(Kees)vanBerkel,MarkB.Josephs,andStevenM.Nowickproceedingsof

IEEE,December2004.

2.ComputerswithoutclocksIvanESutherlandandJoEbergenScientific

American,August2006.

3.IsittimeforClocklesschips?DavidGeerpublishedbyIEEEComputer

Society,March2005.

4.GuestEditorsIntroduction:ClocklessVLSISystemsSohaHassoun,

Yong-BinKimandFabrizioLombardicopublishedbyIEEECSandIEEE

NovemberDecember2005.

5.It'sTimeforClocklessChipsClaireTristramfromMITTechnology

October2008

6.OldtricksfornewchipsApr19th2012FromTheEconomistprintedition

1006clocklesschips

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