10/1/2004eecs150 lab lecture #51 good design & network audio eecs150 fall2004 – lab lecture #5...

10/1/2004 EECS150 Lab Lecture #5 1

Good Design & Network Audio

EECS150 Fall2004 – Lab Lecture #5

Udam Saini


Today (1)

Synplify Warnings ChipScope Administrative Info


Today (2)

Lab #5: Network Audio Network Organization Ethernet Packets Eth2Audio Async FIFO


Synplify Warnings (1) Why Bother?

Part of your project grade Major warnings will cost points

Knowing these will make your life easier

Saves debugging

Incomplete Sensitivity List ModelSim will use the sensitivity list Synplify pretty ignores it


input [15:0] A, B;output [31:0]Sum;output COut;// Adderalways @ (A)

{Sum, COut} = A + B;

Synplify Warnings (2)

input Clock;reg [31:0] Count;// Counteralways @ (posedge Clock)

Count <= Count + 1;input [15:0] A, B;output [31:0]Sum;output COut;// Adderalways @ (A)


OK!

Incomplete Sensitivity

input [15:0] A, B;output [31:0]Sum;output COut;// Adderalways @ (A or B)


OK!


Synplify Warnings (3) Latch Generated

input [1:0] select;input A, B, C;output Out;reg Out;// Muxalways @ (select or A or B or C) begin

case (select)2’b00: Out = A;2’b01: Out = B;2’b10: Out = C;

endcaseend

input [1:0] select;input A, B, C;output Out;reg Out;// Muxalways @ (select or A or B or C) begin

case (select)2’b00: Out = A;2’b01: Out = B;2’b10: Out = C;default: Out = 1’bx;

endcaseend



Combinational Loop

Must remove the loop or add a register

Synplify wont show you the loop Comment out code till it goes away

+0

00

11

12

23∞??

∞??


Synplify Warnings (5) FPGA_TOP2 always has warnings

Un-driven Input Unconnected Output These are truly unneeded pins

Things like the audio chips… In your modules these are a

problem Synplify will optimize your design Unconnected modules removed



Why bother? Getting rid of warnings saves debugging Synplify warnings will result in lost points

Warnings are the only syntax check Verilog is a forgiving language

Undeclared variables default to 1 bit wires This isn’t a good thing


ChipScope (1)

Software based logic analyzer Get results on the computer

Put a logic analyzer right into the FPGA ICON – Connects FPGA to software ILA – Does the actual analysis

More flexible than the bench analyzers

But not as timing accurate


ChipScope (2) Steps to use ChipScope

Generate an ICON Generate an ILA Connect the ILA to the ICON Synthesize, and implement your

design With the ILA and ICON

Program the CaLinx board Run the ChipScope Pro Analyzer

Runs over the JTAG not Slave Serial


ChipScope (3) Logic Analyzer Similarities/Differences

Triggering is similar Can be set to show waves before trigger Can trigger on repeated or combined events

Data/Trigger can be MUCH bigger Up to 256bits wide As many samples as Block RAM on the FPGA

Data is captured synchronously Can’t look at clocks

Much easier to view waveforms


ChipScope (4) ChipScope is useful to verify

In this lab we’re using it just to make absolutely sure

You will NEED ChipScope You cannot debug a large design

without it Bench analyzers wont show enough

signals Detailed ChipScope Tutorial

http://inst.eecs.berkeley.edu/~cs150/fa04/Documents.htm#Tutorials


Administrative Info

Midterm I Midterm I completely graded Some have been handed back in

discussion section. We will hand them out after Lab

Lecture


Lab #5: Network Audio

Play Audio off Ethernet Receive Ethernet packets Decode and remove header Filter packets Play audio data payload

A Major Project Given: Ethernet, Audio, ETC To be written: Packet Decode &

Filtering


Network Organization (1)

Audio Stream

GREEN (0)

TA Station

CaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx2 CaLinx2


Network Organization (2)

DO NOT MODIFY THE PRODUCTION

NETWORK


Ethernet Packets (1) We’re using raw Ethernet

No TCP/IP, its too complex Cant use this on the internet

Raw Ethernet: 48bit Destination MAC Address 48bit Source MAC Address 16bit Ethernet Type Payload 32bit CRC


Ethernet Packets (2)

A Little Theory of Ethernet Bit Serial 100Mbps Link

4/5bit Encoding takes 20% overhead Bit5 is used for Data-Valid and Error

Preamble used for clock extraction Inter Frame Gap ensures packets

aren’t back-to-back CRC used to avoid errors from

transmission



Destination [47:16]

32bits

Destination [15:0] Source [47:32]

Source [31:0]

Ethernet Type [15:0] Reserved [15:0]

PCM Audio Data Sample 0 [31:0]


1028

wor

ds

0xFFFFFFFF

32bits

0xFFFF 0x0090

0xc2001c50

0x0101 0x????



Ethernet Packet Format Broadcast Audio Packet

1024

wor

ds

CRC [31:0]



A Good Packet Total: 1028x 32bit Words 48bit Destination (0xFFFFFFFFFFFF) 48bit Source (0x0090c2001c50) 16bit Packet Type (0x0101) 16bit Padding (0x????) 1024x 32bit PCM Audio Data



A Bad Packet Who knows how long? Source and Destination could be

anything Packet Type probably not 0x0101

Coping with bad packets Do NOT send them to AudioTop

Just keep dropping data until end of packet InPacketValid & InPacketInvalid


Lab #5: Eth2Audio

AP_BIT_CLOCK (12MHz)

Reg

iste

r

MAC Rx Unit

Eth Rx Unit

Input Shift Register

Output Shift Register

AC97 Controller

LM4549A Codec

PHY_RX_CLK (~25MHz)

LXT975 Ethernet

PHY

4bit

Raw

Eth

erne

t Dat

a

4bit

Raw

Eth

erne

t Dat

a

~25

MH

z E

ther

net C

lock

32b

Eth

erne

t Pac

ket D

ata

32b

PC

M A

udio

Dat

a

AP

_SD

AT

A_O

UT

AP

_SD

AT

A_I

N

Receive Block Diagram

Async FIFO32

Eth2Audio

Decode & Filter

32b

PC

M A

udio

Dat

a


Lab #5: Eth2AudioSignal Widt

hDir

Description

DIn 32 I Data from MAC_Top

InValid 1 I Indicates DIn is valid

InPacketValid 1 I Indicates the end of a good(crc) packet

InPacketInvalid 1 I Indicates the end of a bad(crc) packet

EthernetClock 1 I 25MHz Ethernet Clock

EthernetReset 1 I EthernetClock sync. Reset

AudioClock 1 I 12.288MHz Audio Clock

AudioReset 1 I AudioClock sync. Reset

DOut 32 O Data out to AudioTop

OutRequest 1 I AudioTop requesting a new word

OutValid 1 O Indicates DOut is valid


Lab #5: Eth2Audio Design

Word Counter How many bits wide? Efficient Comparisons?

Valid Register Stores whether the packet is valid or not

Reset When do you reset word counter and

valid register? Short and Long Bad Packets


Lab #5: Eth2Audio

Testing We give you a very nice testbench

Read Lab5Testbench.v Read Lab5TestPackets.txt

Fix your module in simulation Checkoff

We should hear nice clean audio Show us your module using

ChipScope


Lab #5: Async FIFO Buffer to match

two data rates Great for data

path clock domain crossings Write on one clock Read on another

Good place to buffer audio


Verilog Tips & Tricks

EECS150 Lab Lecture #5 29

Running a New Simulation without Closing ModelSim

In the ModelSim console, press the up arrow to see the previous command: {do xyzTestbench.fdo}

This command will “recompile” your Verilog files and rerun the simulation.

Rerunning without recompiling: restart –f; run 10us;


Viewing Signals in Submodules

Expand submodules in Workspace pane Click-and-drag signals to waveform Type “restart –f; run 10us;” in console. Do not use the “do” command!


Declaring reg for outputs. Suppose count needs to be assigned a

value in an always blocks. output [3:0] count; reg count;

What’s wrong here? output [3:0] count; reg [3:0] count;

What’s the best way of fixing this? output reg [3:0] count;


Explicitly Connect to Module Ports

We’ve been calling this “dot notation”

Good: adder

my_adder(.A(A),.B(B),.Sum(Sum)); Bad:

adder my_adder(A,B,Sum);


What Can Go Wrong? (1)

Suppose David and Randy are working on a project.

David writes module foo(A,B,F) Randy instantiates it in his design:

wire w1,w2,w3; foo my_foo(w1, w2, w3);


What Can Go Wrong? (2)

David needs to add port C to foo: module foo(A,B,C,F)

David tells Randy about the new port: wire w1,w2,w3,w4; foo my_foo(w1,w2,w3,w4);

Now w3 connects to C instead of F!


Use Meaningful Wire Names

Bad wire w1, w2, w3; foo my_foo(.A(w1), .B(w2), .F(w3));

Good wire foo_a, foo_b, foo_f; foo

my_foo(.A(foo_a),.B(foo_b),.F(foo_f)); More helpful when using ModelSim


Synthesis Warnings

In particular, watch out for these Combinational loop detected Latch generated Incomplete sensitivity list

If any of these appear in your synthesis warnings, your synthesized design will most likely not match simulation.


One Module per File Module name should match file

name Otherwise, it’s difficult to find the

file containing your module.


always @ blocks

For state machines, use 2 or 3 always blocks.

Recall the Mealy Machine:

Output and Next State Combinational Logic

Inputs

Outputs

Next StateCurrent State

State


always @ blocks

always @ (CurrentState or Inputs) beginNextState = CurrentState;Outputs = 0;case(CurrentState)

STATE_Init: begin(Next state and output calculations

here)end…

endcaseend

always @ (posedge Clock)if(Reset) CurrentState <=

STATE_Init;else CurrentState <= NextState;

Output and Next State Combinational Logic

Inputs

Outputs

Next StateCurrent StateState


always @ blocks What about a Moore Machine? State transition part is the same May use three always blocks:

always @ (CurrentState or Inputs) begin

NextState = CurrentState;case(CurrentState)

[Calculate Next State]

endcaseendalways @ (CurrentState) begin

Outputs = 0;case(CurrentState)

[Calculate Output]endcase

end


More Moore Machines Suppose output “foo” is only high

in state STATE_Foo:always @ (CurrentState) begin

foo = 0;case(CurrentState)

…STATE_Foo: foo =

1;…

endcaseend

May also use assign statements:assign foo = (CurrentState == STATE_Foo);


Parameters as State Names Bad

case(CurrentState)3’b000: NextState = 3’b101;3’b001: NextState = 3’b100;…

endcase

Goodparameter STATE_Init = 3’b000, STATE_Foo = 3’b001,

…

case(CurrentState)STATE_Init: NextState = STATE_Bar;STATE_Foo: NextState = STATE_Baz;…

endcase

Parameters make your code easier to read, debug, and change.


Use defparam Suppose you need a 6-bit register. In Register.v:

Parameter width = 32;…

Output [width-1:0] Out;

Do not simply make a file called Register6.v and change the width!

Instead, use defparam:Register MyRegister( … );defparam MyRegister.width = 6;


Use Register.v and Counter.v Suppose you need a counter that

increments to 42 before resetting.// Without Counter.valways @ (posedge Clock)

if(Reset || (Count == 41)) Count <= 0;else if(Enable) Count <= Count + 1;

// With Counter.vCounter MyCounter(.Clock(Clock), .Reset(Reset || (Count == 41), .Set(1’b0), .Load(1’b), .Enable(Enable), .In(0), .Count(Count));defparam MyCounter.width = 6;

Cleaner “always” blocks Don’t forget defparam!


Avoid this Loop

1. Observe error on board2. Make guess about source of error3. Make small change to verilog files4. Generate programming file (may take

up to 20 minutes)5. Surf Facebook6. Go back to step 1

Instead, review your synthesis warnings and use Chipscope to debug.

This is why some projects take 100+ hours


Questions?

10/1/2004eecs150 lab lecture #51 good design & network audio eecs150 fall2004 – lab lecture #5...

Documents

1012004eecs150 lab lecture

b synplify warnings

sensitivity list synplify

udam saini slide

project grade major

count counter

b output31

posedge clock count