10/27/2004ee 42 fall 2004 lecture 241 lecture #24 gates to circuits
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10/27/2004 EE 42 fall 2004 lecture 24 1
Lecture #24 Gates to circuits
10/27/2004 EE 42 fall 2004 lecture 24 2
Topics
Today:
• Implementing gates with MOS transistors
• Gate delays
• Glitches
10/27/2004 EE 42 fall 2004 lecture 24 3
CMOS and complementary logic
• Complementary PMOS and NMOS switches in parallel or in series with complementary logic to form high speed, low power logic
• PMOS devices turn on with low voltages, so we use them in the pull up circuit for a gate
• NMOS devices turn on with high voltages, so we use them in the pull down circuit for a gate
10/27/2004 EE 42 fall 2004 lecture 24 4
Pull up/Pull down
Using CMOS, which has both NMOS and PMOS transistors, we can build gates which turn on a connection to +V when the output is supposed to be high, and another connection to ground when the output is supposed to be low.
(PMOS)
(NMOS)
+V
A
B
C Output
10/27/2004 EE 42 fall 2004 lecture 24 5
CMOS NOR
VDD
A
B
BA
10/27/2004 EE 42 fall 2004 lecture 24 6
CMOS NORVDD
A
B
A+B
IF both A and B are low, then both pull up transistors are on
IF neither A or B are high then both of the pull down transistors are off
And the output
Goes high
10/27/2004 EE 42 fall 2004 lecture 24 7
CMOS NORVDD
A
B
A+B
IF either A and B are low, then at least one of the pull up transistors is off
IF either A or B are high then at least one of the pull down transistors is on
And the output
goes low
10/27/2004 EE 42 fall 2004 lecture 24 8
CMOS NAND
VDD
A
B
AB
10/27/2004 EE 42 fall 2004 lecture 24 9
CMOS NAND
VDD
A
B
C
CBA
10/27/2004 EE 42 fall 2004 lecture 24 10
CMOS logic transitions
• If we look at CMOS with static inputs, it will pull up high logic levels all the way to the supply
• Low logic levels are pulled all the way down to ground.
• We will now look at the behavior of the circuits as they are switching, which will determine the performance of the logic
10/27/2004 EE 42 fall 2004 lecture 24 11
NMOS current vs. Voltage
State 1 or VIN = 1V
VOUT(V)0 3 VDD =5
IOUT(A)
20
60
100
State 3 or VIN = 3V
State 5 or VIN = 5V
The maximum voltage is VDD
VOUT-SAT-D
Current is flat (saturated) beyond VOUT-SAT-D
Current is zero until VIN is larger than VTD
(Drain) current saturation values
10/27/2004 EE 42 fall 2004 lecture 24 12
PMOS current vs. Voltage
VOUT(V)0 3 VDD =5
IOUT(A)
20
60
100
State 3 or VIN = 3V
State 5 or VIN = 5V
VOUT-SAT-D
Current is flat (saturated) below VOUT-SAT-D
Current is zero until VIN is below VTD
(Drain) current saturation values
10/27/2004 EE 42 fall 2004 lecture 24 13
CMOS Inverter
• Since CMOS uses one or more PMOS devices to pull up, and one or more NMOS devices to pull down, we can get most of the dynamics from an inverter.
10/27/2004 EE 42 fall 2004 lecture 24 14
CMOS inverter
VDD
AA
10/27/2004 EE 42 fall 2004 lecture 24 15
• Since +V is the sum of the voltage across the NMOS device and the PMOS device, we can draw a composite IV plot for the two devices, showing the current which is available from each of the two devices.
• On the next slide, notice that when one device is turned on, and able to provide a lot of current, the other device is off
10/27/2004 EE 42 fall 2004 lecture 24 16
Composite IOUT vs. VOUT for CMOS
VDD =5
The maximum voltage is VDD
VOUT(V)0 3
IOUT(A)
20
60
100
State 3 or VIN = 3V
VOUT-SAT-D
Pull-Up PMOS IOUT-SAT-U
Pull-Down NMOS IOUT-SAT-D
Solution
PD current is flat (saturated) beyond VOUT-SAT-D
PU current is flat (saturated) belowVDD - VOUT-SAT-D
10/27/2004 EE 42 fall 2004 lecture 24 17
Output Propagation Delay High to Low
When VOUT > VOUT-SAT-D the available current is IOUT-SAT-D
VOUT(0) = 5V
COUT = 50 fF
IOUT-SAT-D = 100 A
VOUT(V)0 3 5
IOUT(A)
20
60
100VIN = 5V
IOUT-SAT-D = 100 A
For this circuit when VOUT > VOUT-SAT-D the available current is constant at IOUT-SAT-D and the capacitor discharges.
10/27/2004 EE 42 fall 2004 lecture 24 18
Output Propagation Delay High to Low (Cont.)
The propagation delay is thus
nsA
VfF
I
VC
I
VCt
DSATOUT
DDOUT
DSATOUT
OUT 25.1100
5.250
2
10/27/2004 EE 42 fall 2004 lecture 24 19
RD = ¾ VDD/ISAT has a Physical Interpretation
VOUT(0) = 5V
COUT = 50 fF
IOUT-SAT-D = 100 A
VOUT(V)0 3 5
IOUT(A)
20
60
100VIN = 5V
IOUT-SAT-D = 100 A
¾ VDD is the average value of VOUT
Approximate the NMOS device curve by a straight line from (0,0) to (IOUT-SAT-D, ¾ VDD ).
Interpret the straight line as a resistor with
slope = 1/R = ¾ VDD/ISAT
10/27/2004 EE 42 fall 2004 lecture 24 20
Switched Equivalent Resistance Values
The resistor values depend on the properties of silicon, geometrical layout, design style and technology node.
n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type.
The resistance is inversely proportion to the gate width/length in the geometrical layout.
Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size.
The current per unit width of the gate increases nearly inversely with the gate width.
10/27/2004 EE 42 fall 2004 lecture 24 21
Inverter Propagation Delay
t = 0.69RDCOUT = 0.69(10k)(50fF) = 345 ps
Discharge (pull-down)
Discharge (pull-up)
t = 0.69RUCOUT = 0.69(10k)(50fF) = 345 ps
VOUT
VDD
VIN = Vdd
COUT = 50fF
VOUT
VDD
VIN = Vdd
RD
COUT = 50fF
10/27/2004 EE 42 fall 2004 lecture 24 22
Example using resistor model
• Using the resistor model, we can calculate the approximate rise and fall times for more complex gates, such as
)( CBACBABCA
10/27/2004 EE 42 fall 2004 lecture 24 23
CMOS Logic Gate
A
B
C
A
B C
VDD
VOUT
NMOS conduct when input is high.
PMOS only in pull-up
NMOS and PMOS use the same set of input signals
PMOS conducts when input is low
NMOS only in pull-down
NMOS conduct for A + (BC)
PMOS do not conduct when A +(BC)
Logic is Complementary and produces Vout = A + (BC)
10/27/2004 EE 42 fall 2004 lecture 24 24
CMOS Logic Gate: Example Inputs
A
B
C
A
B C
VDD
VOUT
NMOS do not conduct
Logic is Complementary and produces Vout = 1
A = 0B = 0C = 0
PMOS all conduct
Output is High
= VDD
10/27/2004 EE 42 fall 2004 lecture 24 25
CMOS Logic Gate: Example Inputs
A
B
C
A
B C
VDD
VOUT
NMOS B and C conduct; A open
Logic is Complementary and produces Vout = 0
A = 0B = 1C = 1
PMOS A conducts; B and C Open
Output is High
= 0
10/27/2004 EE 42 fall 2004 lecture 24 26
Switched Equivalent Resistance Network
A
B
C
A
B C
VDD
VOUT
AB
C
A
B C
VDD
VOUT
RU
RURU
RD
RD
RDSwitches close when input is high.
Switches close when input is low.