129094123 chameleon chips

8/13/2019 129094123 Chameleon Chips

1/12

FREE TECHNICAL PAPER DOWNLOADwww.Newtechpapers.com

CHAMELEON CHIPS

INTRODUCTION

Today's microprocessors sport a generalp!rpose design "#ic# #as its o"n ad$antagesand disad$antages%

Ad$& One c#ip can r!n a range o programs% T#at's "#y yo! don't need separatecomp!ters or dierent (o)s* s!c# as cr!nc#ing spreads#eets or editing digital p#otos

Disad$& For any one application* m!c# o t#e c#ip's circ!itry isn't needed* and t#e

presence o t#ose +"asted+ circ!its slo"s t#ings do"n%

,!ppose* instead* t#at t#e c#ip's circ!its co!ld )e tailored speciically or t#e pro)lem at

#andsay* comp!teraided designand t#en re"ired* on t#e ly* "#en yo! loaded a ta-preparationprogram% One set o c#ips* little )igger t#an a credit card* co!ld do almost anyt#ing* e$en c#anging

into a "ireless p#one% T#e mar.et or s!c# $ersatile mar$els "o!ld )e #!ge* and "o!ld translate intolo"er costs or !sers%

,o comp!ter scientists are #atc#ing a no$el concept t#at co!ld increase n!m)er

cr!nc#ing po"erand trim costs as "ell% Call it t#e c#ameleon c#ip%

C#ameleon c#ips "o!ld )e an e-tension o "#at can already )e done "it# ieldprogramma)le gate arrays /FP0A,1%

An FP0A is co$ered "it# a grid o "ires% At eac# crosso$er* t#ere's a s"itc# t#at can )e

semipermanently opened or closed )y sending it a special signal% 2s!ally t#e c#ip m!st irst )einserted in a little )o- t#at sends t#e

programming signals% 3!t no"* la)s in E!rope* 4apan* and t#e 2%,% are de$eloping tec#ni5!es to

re"ire FP0Ali.e c#ips anytimeand e$en sot"are t#at can map o!t circ!itry t#at's optimi6ed or

speciic pro)lems%

T#e c#ips still "on't c#ange colors% 3!t t#ey may "ell color t#e "ay "e !se comp!ters in

years to come% it is a !sion )et"een c!stom integrated circ!its and programma)le logic%in t#e case"#en "e are doing #ig#ly perormance oriented tas.s c!stom c#ips t#at do one or t"o t#ings

spectac!larly rat#er t#an lot o t#ings a$eragely is !sed% No" !sing ield programmed c#ips "e #a$ec#ips t#at can )e re"ired in an instant% T#!s t#e )eneits o c!stomi6ation can )e )ro!g#t to t#e

mass mar.et%

A reconig!ra)le processor is a microprocessor "it# erasa)le #ard"are t#at can re"ire

itsel dynamically% T#is allo"s t#e c#ip to adapt eecti$ely to t#e programming tas.s demanded )y

t#e partic!lar sot"are t#ey are interacing "it# at any gi$en time% Ideally* t#e reconig!ra)le

processor can transorm itsel rom a $ideo c#ip to a central processing !nit /cp!1 to a grap#ics c#ip*

or e-ample* all optimi6ed to allo" applications to r!n at t#e #ig#est possi)le speed% T#e ne" c#ipscan )e called a "chip o !ema!." In practical terms* t#is a)ility can translate to immense

le-i)ility in terms o de$ice !nctions% For e-ample* a single de$ice co!ld ser$e as )ot# a camera anda tape recorder /among n!mero!s ot#er possi)ilities1& yo! "o!ld simply do"nload t#e desired

sot"are and t#e processor "o!ld reconig!re itsel to optimi6e perormance or t#at !nction%

Reconig!ra)le processors* competing in t#e mar.et "it# traditional #ard"ired c#ips

and se$eral types o programma)le microprocessors% Programma)le c#ips #a$e )een in e-istence oro$er ten years% Digital signal

processors /D,Ps1* or e-ample* are #ig#perormance programma)le c#ips !sed in cell p#ones*

a!tomo)iles* and $ario!s types o m!sic players%

Anot#er $ersion* programma)le logic c#ips are e5!ipped "it# arrays o memory cells t#at

can )e programmed to perorm #ard"are !nctions !sing sot"are tools% T#ese are more le-i)le

t#an t#e speciali6ed D,P c#ips )!t also slo"er and more e-pensi$e% Hard"ired c#ips are t#e oldest*

c#eapest* and astest )!t also t#e least le-i)le o all t#e options%

Chameeo chips

Hig#ly le-i)le processors t#at can )e reconig!red remotely in t#e ield* C#ameleon's

c#ips are designed to simpliy comm!nication system design "#ile deli$ering increased

FREE TECHNICAL PAPER DOWNLOADwww.Newtechpapers.com-1-


2/12


price7perormance n!m)ers% T#e c#ameleon c#ip is a #ig# )and"idt# reconig!ra)le comm!nications

processor /RCP1%it aims at c#anging a system's design rom a remote location% T#is "ill mean more

$ersatile #and#elds% Processors operate at 89*::: ;*::: ;


3/12


4/12


An FP0A consists o an array o conig!ra)le logic )loc.s t#at implement t#e logical

!nctions% In FP0A's* t#e logic !nctions perormed "it#in t#e logic )loc.s* and sending signals to t#ec#ip can alter t#e connections )et"een t#e )loc.s% T#ese )loc.s are similar in str!ct!re to t#e gate

arrays !sed in some A,IC's* )!t "#ereas standard gate arrays are conig!red and i-ed d!ring

man!act!re* t#e conig!ra)le logic )loc.s in ne" FP0A's can )e re"ired and reprogrammedrepeatedly in aro!nd a microsecond% One ad$antages o FP0A is t#at it needs small time to mar.et

Fle-i)ility and 2pgrade ad$antages C#eap to ma.e %We can conig!re an FP0A !sing Gery

Hig# Density Lang!age GHDL Handel C 4a$a %FP0AJs are !sed presently in Encryption

Image Processing =o)ile Comm!nications %FP0AJs can )e !sed in 90 mo)ile comm!nication

T#e ad$antages o FP0As are t#at Field programma)le gate arrays oer companies t#epossi)ility o de$elloping a c#ip $ery 5!ic.ly* since a c#ip can )e conig!red )y sot"are% A c#ip can

also )e reconig!red* eit#er d!ring e-ec!tion time* or as part o an !pgrade to allo" ne"applications* simply )y loading ne" conig!ration into t#e c#ip% T#e ad$antages can )e seen in terms

o cost* speed and po"er cons!mption% T#e added !nctionality o m!ltiparallelism allo"s one FP0A

to replace m!ltiple A,ICJs%

T#e applications o FP0AJs are in

image processing encryption

mo)ile comm!nication

memory management and digital signal processing

telep#one !nits

mo)ile )ase stations%

Alt#o!g# it is $ery #ard to predict t#e direction t#is tec#nology "ill ta.e* it seems more

t#an li.ely t#at !t!re silicon c#ips "ill )e a com)ination o programma)le logic* memory )loc.s andspeciic !nction )loc.s* s!c# as loating point !nits%

It is #ard to predict at t#is early stage* )!t it loo.s li.ely t#at t#e tec#nology "ill #a$e to

c#ange o$er t#e coming years* and t#e rate o c#ange or ma(or players in todays mar.etplace s!c#

as Intel* =icrosot and A=D "ill )e cr!cial to t#eir s!r$i$al%

T#e precise )e#a$io!r o eac# cell is determined )y loading a string o n!m)ers into a

memory !nderneat# it% T#e "ay in "#ic# t#e cells are interconnected is speciied )y loading anot#er

set o n!m)ers into t#e c#ip% C#ange t#e irst set o n!m)ers and yo! c#ange "#at t#e cells do%

C#ange t#e second set and yo! c#ange t#e "ay t#ey are lin.ed !p% ,ince e$en t#e most comple-

c#ip is* at its #eart* not#ing more t#an a )!nc# o interlin.ed logic circ!its* an FP0A can )eprogrammed to do almost anyt#ing t#at a con$entional i-ed piece o logic circ!itry can do* (!st )y

loading t#e rig#t n!m)ers into its memory% And )y loading in a dierent set o n!m)ers* it can )ereconig!red in t#e t"in.ling o an eye%

3asic reconig!ra)le circ!its already play a #!ge role in telecomm!nications% For instance*relati$ely simple $ersions made )y companies s!c# as ilin- and Altera are "idely !sed or net"or.

ro!ters and s"itc#es* ena)ling circ!it designs to )e easily !pdated electronically "it#o!t replacing

c#ips% In t#ese early applications* #o"e$er* t#e speed at "#ic# t#e c#ips reconig!re t#emsel$es is

not critical% To )e 5!ic. eno!g# or personal inormation de$ices* t#e c#ips "ill need to completely

reconig!re t#emsel$es in a millisecond or less% +T#at .ind o c#ameleon de$ice "o!ld )e t#e .illerapp o reconig!ra)le comp!ting+ T#ese e-perts predict t#at in t#e ne-t co!ple o years

reconig!ra)le systems "ill )e !sed in cell p#ones to #andle t#ings li.e c#anges in

telecomm!nications systems or standards as !sers tra$el )et"een calling regions or )et"eenco!ntries%

As it is getting more e-pensi$e and diic!lt to pattern* or etc#* t#e ela)orate circ!itry!sed in microprocessors many e-perts #a$e predicted t#at maintaining t#e c!rrent rate o p!tting

more circ!its into e$er smaller spaces "ill* sometime in t#e ne-t ;: to ;? years* res!lt in eat!res onmicroc#ips no )igger t#an a e" atoms* "#ic# "o!ld demand a nearly impossi)le le$el o precision in

a)ricating circ!itry 3!t reconig!ra)le c#ips don't need t#at type o precision and "e can ma.e

comp!ters t#at !nction at t#e nanoscale le$el

CS())(/a reconig!ra)le processor de$eloped )y c#ameleon systems1



5/12


RCP arc#itect!re is designed to )e as le-i)le as an FP0A* and as easy to program as a

digital signal processor /D,P1* "it# realtime* $is!al de)!gging capa)ility% T#e de$elopmenten$ironment* comprising C#ameleon's C,IDE sot"are tool s!ite and CT8;;8,D= de$elopment .it*

ena)les c!stomers to de$elop and de)!g comm!nication and signal processing systems r!nning on

t#e RCP% T#e RCP's de$elopment en$ironment #elps o$ercome a !ndamental design and de)!gc#allenge acing comm!nication system designers%In order to )!ild s!icient perormance* c#annel

capacity* and le-i)ility into t#eir systems* today's designers #a$e )een orced to employ an

amalgamation o D,Ps* FP0As and A,ICs* eac# o "#ic# re5!ires a !ni5!e design and de)!g

en$ironment%

T#e RCP platorm "as designed rom t#e gro!nd !p to alle$iate t#is pro)lem& irst )y

signiicantly e-ceeding t#e perormance and c#annel capacity o t#e astest D,Ps second )yintegrating a complete ,oC s!)system* incl!ding an em)edded microprocessor* PCI core* D=A

!nction* and #ig#speed )!s and t#ird )y consolidating t#e design and de)!g en$ironment into asingle platorm)ased design system t#at aords t#e designer compre#ensi$e $isi)ility and control%

T#e C,IDE sot"are s!ite incl!des tools !sed to compile C and assem)ly code or

e-ec!tion on t#e C,8;;8's em)edded microprocessor* and Gerilog sim!lation and synt#esis tools

!sed to create parallel datapat# .ernels "#ic# r!n on t#e C,8;;8's reconig!ra)le processing a)ric%

In addition to code generation tools* t#e pac.age contains so!rcele$el de)!gging toolst#at s!pport sim!lation and realtime de)!gging% C#ameleon's design approac# le$erages t#e

met#ods employed )y most o today's comm!nications system designers% T#e designer starts "it# aC program t#at models signal processing !nctions o t#e )ase)and system% Ha$ing identiied t#e

datalo" intensi$e !nctional )loc.s* t#e designer implements t#em in t#e RCP to accelerate t#em )y;: to ;::old%

T#e designer creates e5!i$alent !nctions or t#ose )loc.s* called .ernels* in C#ameleon's

reconig!ra)le assem)ly lang!ageli.e design entry lang!age% T#e assem)ler t#en a!tomatically

generates standard Gerilog or t#ese .ernels t#at t#e designer can $eriy "it# commercial Gerilog

sim!lators% 2sing t#ese tools* t#e designer can compare test)enc# res!lts or t#e original C !nctions"it# similar res!lts or t#e Gerilog .ernels% In t#e ne-t p#ase* t#e designer synt#esises t#e Gerilog

.ernels !sing C#ameleon's synt#esis tools targeting C#ameleon tec#nology% At t#e end* t#e toolso!tp!t a )it ile t#at is !sed to conig!re t#e RCP%T#e designer t#en integrates t#e application le$el C

code "it# Gerilog .ernels and t#e rest o t#e standard C !nction%C#ameleon's C,IDE compiler andlin.er tec#nology ma.es t#is integration step transparent to t#e designer%

T#e C,8;;8 de$elopment en$ironment ma.es all c#ip registers and memory locations

accessi)le t#ro!g# a de$elopment console t#at ena)les !ll processorli.e de)!gging* incl!ding

eat!res li.e singlestepping and setting )rea.points% 3eore act!ally prod!ctising t#e system* t#e

designer m!st oten perorm a systemle$el sim!lation o t#e data lo" "it#in t#e conte-t o t#eo$erall system% C#ameleon's de$elopment )oard ena)les t#e designer to connect m!ltiple RCPs to

ot#er de$ices in t#e system !sing t#e PCI )!s and7or programma)le I7O pins%

T#is #elps pro$e t#e design concept* and ena)les t#e designer to proile t#e perormanceo t#e "#ole )asestation system in a real"orld en$ironment% Wit# telecomm!nications OE=s acing

s#rin.ing prod!ct lie cycles and increasing mar.et press!res* not to mention t#e constant l!- o

protocols and standards* it's more necessary t#an e$er to #a$e a platorm t#at's reconig!ra)le% T#is

is "#ere t#e c#ameleon c#ips are going to ma.e its eect elt%

T#e C#ameleon C,8;;8 Pac.age is a #ig#)and"idt#* reconig!ra)le comm!nications

processor aimed at

second and t#irdgeneration "ireless )ase stations

i-ed point "ireless local loop /WLL1 $oice o$er IP

D,L/digital s!)scri)er line1 Hig# end dsp operations

80>0 "ireless )ase stations sot"are deined radio

sec!rity processing

+Traditional sol!tions s!c# as FP0As and D,Ps lac. t#e perormance or #ig#)and"idt#

applications* and i-ed !nction sol!tions li.e A,ICs inc!r !naccepta)le limits Eac# prod!ct in t#e



6/12


C,8::: amily #as t#e same !ndamental !nctional )loc.s& a >8)it RI,C processor* a !lleat!red

memory controller* a PCI controller* and a reconig!ra)le processing a)ric* all o "#ic# are

interconnected )y a #ig#speed system )!s% T#e a)o$e mentioned a)ric comprises an array oreconig!ra)le tiles !sed to implement t#e desired algorit#ms% Eac# tile contains se$en >8)it

reconig!ra)le datapat# !nits* o!r )loc.s o local store memory* t"o ;8)it Risc ARC processor K;8?=H6

8 )it PCI controller

reconig!ra)le processing a)ric /RPF1

#ig# speed system )!s

programma)le I7O /;


7/12


reconig!ra)le D,P lets t#e de$eloper tailor t#e #ard"are or a speciic tas.* ac#ie$ing t#e rig#t si6e

and cost or t#e target application% =oreo$er* t#e same platorm can )e re!sed or ot#er applications%

3eca!se de$elopment tools are a critical part o t#is sol!tionBin act* t#ey're tr!e

ena)lersBt#e ne"comers also ens!re t#at t#e tools are ro)!st and tig#tly lin.ed to t#e de$ices'

le-i)le arc#itect!res% W#ile pro$iding an int!iti$e* integrated de$elopment en$ironment or t#edesigners* t#e man!act!rers ens!re aorda)ility as "ell%

RECON'I$URIN$ THE ARCHITECTURE

,ome o t#e ne" conig!ra)le D,P arc#itect!res are reconig!ra)le tooBt#at is*

de$elopers can modiy t#eir landscape on t#e ly* depending on t#e incoming data stream% T#is

capa)ility permits dynamic reconig!ra)ility o t#e arc#itect!re as demanded )y t#e application%Proponents o s!c# c#ips are proclaiming an era o +c#ipondemand*+ "#erein ne" algorit#ms can

)e accommodated onc#ip in real time $ia sot"are% T#is eliminates t#e c!m)ersome (o) o ittingt#e latest algorit#ms and protocols into e-isting rigid #ard"are% A reconig!ra)le comm!nications

processor /RCP1 can reconig!red or dierent processing algorit#ms in one cloc. cycle%

C#ameleon designers are re$ising t#e arc#itect!re to create a c#ip t#at can address a m!c#

)roader range o applications% Pl!s* t#e s!pplier is preparing a ne"* more !serriendly s!ite o tools

or traditional D,P designers% T#!s* t#e company is dropping t#e term reconig!ra)ility or t#e ne"arc#itect!re and going "it# a more traditional name* t#e streaming data processor /,DP1%

T#o!g# t#e ,DP "ill incl!de a reconig!ra)le processing a)ric* it "ill )e s!)stantially altered*

t#e company says% 2nli.e t#e older RCP* t#e ne" c#ip "on't #a$e t#e AR= RI,C core* and it "ills!pport a m!c# #ig#er cloc. rate% Additionally* it "ill )e implemented in a :%;>Mm C=O, process to

meet t#e signal processing needs o a m!c# )roader mar.et% F!rt#er details a"ait t#e release o ,DPsometime in t#e irst 5!arter o 8::>%

W#ile C#ameleon is in t#e redesign mode* !ic.,il$er Tec#nologies is in t#e test mode% T#is

reconig!ra)le proponent* "#ic# preers to call its arc#itect!re an adapti$e comp!ting mac#ine or AC=*

#as reali6ed its irst silicon test c#ip% In act* t#e tests indicate t#at it o!tperorms a #ard"ired* i-ed

!nction A,IC in processing comp!teintensi$e cdma8::: algorit#ms* li.e system ac5!isition* ra.einger* and set maintenance% For e-ample* t#e A,IC's nominal speed or searc#ing 8;? p#ase osets in

a )asic m!ltipat# searc# algorit#m is >%9 seconds% T#e AC= test c#ip too. (!st one second at a 8?=H6cloc. speed to perorm t#e same n!m)er o searc#es in a cdma8::: #andset% Li.e"ise* t#e de$ice

accomplis#es o$er ?*::: adaptations per second in ra.einger operation to cycle t#ro!g# alloperations in t#is application e$ery ?8 Ms /Fig% ;1% In t#e setmaintenance application* t#e c#ip is

almost t#ree times aster t#an an A,IC* claims !ic.,il$er%

THE po"er o a comp!ter stems rom t#e act t#at its )e#a$io!r can )e c#anged "it#

little more t#an a dose o ne" sot"are% A des.top PC mig#t* or e-ample* )e )ro"sing t#e Internet

one min!te* and r!nning a spreads#eet or entering t#e $irt!al "orld o a comp!ter game t#e ne-t%3!t t#e a)ility o a microprocessor /t#e c#ip t#at is at t#e #eart o any PC1 to #andle s!c# a $ariety o

tas.s is )ot# a strengt# and a "ea.nessB)eca!se #ard"are dedicated to a partic!lar (o) can dot#ings so m!c# aster%

Recognising t#is* t#e designers o modern PCs oten #and o$er s!c# tas.s as processing

>D grap#ics* decoding and playing mo$ies* and processing so!ndBt#ings t#at co!ld* in t#eory* )e

done )y t#e )asic microprocessorBto specialist c#ips% T#ese c#ips are designed to do t#eir partic!lar

(o)s e-tremely ast* )!t t#ey are inle-i)le in comparison "it# a microprocessor* "#ic# does its )est

to )e a (ac.oalltrades% ,o t#e #ard"are approac# is aster* )!t !sing sot"are is more le-i)le%

At t#e moment* s!c# reconig!ra)le c#ips are !sed mainly as a "ay o con(!ring !p

specialist #ard"are in a #!rry% Rat#er t#an designing and )!ilding an entirely ne" c#ip to carry o!t apartic!lar !nction* a circ!it designer can !se an FP0A instead% T#is speeds !p t#e design process

enormo!sly* )eca!se ma.ing c#anges )ecomes as simple as do"nloading a ne" conig!ration intot#e c#ip% C#ameleon ,ystems also de$elops reconig!ra)le c#ips or t#e #ig#end telecoms"itc#ing

mar.et%

RECON'I$URA*LE PROCESSORS

A reconig!ra)le processor is a microprocessor "it# erasa)le #ard"are t#at can re"ire

itsel dynamically% T#is allo"s t#e c#ip to adapt eecti$ely to t#e programming tas.s demanded )y

t#e partic!lar sot"are t#ey are interacing "it# at any gi$en time% Ideally* t#e reconig!ra)le

processor can transorm itsel rom a $ideo c#ip to a central processing !nit /cp!1 to a grap#ics c#ip*or e-ample* all optimi6ed to allo" applications to r!n at t#e #ig#est possi)le speed% T#e ne" c#ips



8/12


can )e called a "chip o !ema!." In practical terms* t#is a)ility can translate to immense

le-i)ility in terms o de$ice !nctions% For e-ample* a single de$ice co!ld ser$e as )ot# a camera and

a tape recorder /among n!mero!s ot#er possi)ilities1& yo! "o!ld simply do"nload t#e desiredsot"are and t#e processor "o!ld reconig!re itsel to optimi6e perormance or t#at !nction%

Reconig!ra)le processors* competing in t#e mar.et "it# traditional #ard"ired c#ipsand se$eral types o programma)le microprocessors% Programma)le c#ips #a$e )een in e-istence or

o$er ten years% Digital signal processors /D,Ps1* or e-ample* are #ig#perormance programma)le

c#ips !sed in cell p#ones* a!tomo)iles* and $ario!s types o m!sic players%

W#ile microprocessors #a$e )een t#e dominant de$ices in !se or generalp!rpose

comp!ting or t#e last decade* t#ere is still a large gap )et"een t#e comp!tational eiciency o

microprocessors and c!stom silicon% Reconig!ra)le de$ices* s!c# as FP0As* #a$e come closer toclosing t#at gap* oering a ;:- )eneit in comp!tational density o$er microprocessors* and oten

oering anot#er potential ;:- impro$ement in yielded !nctional density on lo" gran!larityoperations% On #ig#ly reg!lar comp!tations* reconig!ra)le arc#itect!res #a$e a clear s!periority to

traditional processor arc#itect!res% On tas.s "it# #ig# !nctional di$ersity* microprocessors !se

silicon more eiciently t#an reconig!ra)le de$ices% T#e 3RA,, pro(ect is de$eloping a co!pled

arc#itect!re "#ic# allo" a reconig!ra)le array and processor core to cooperate eiciently on

comp!tational tas.s* e-ploiting t#e strengt#s o )ot# arc#itect!res%

We are de$eloping an arc#itect!re and a prototype component t#at "ill com)ine a processor

and a #ig# perormance reconig!ra)le array on a single c#ip% T#e reconig!ra)le array e-tends t#e!se!lness and eiciency o t#e processor )y pro$iding t#e means to tailor its circ!its or special

tas.s% T#e processor impro$es t#e eiciency o t#e reconig!ra)le array or irreg!lar* generalp!rpose comp!tation%

We anticipate t#at a processor com)ined "it# reconig!ra)le reso!rces can ac#ie$e a

signiicant perormance impro$ement o$er eit#er a separate processor or a separate reconig!ra)le

de$ice on an interesting range o pro)lems dra"n rom em)edded comp!ting applications% As s!c#*

"e #ope to demonstrate t#at t#is composite de$ice is an ideal system element or em)edded

processing%

Reconig!ra)le de$ices #a$e pro$en e-tremely eicient or certain types o processing tas.s%

T#e .ey to t#eir cost7perormance ad$antage is t#at con$entional processors are oten limited )yinstr!ction )and"idt# and e-ec!tion restrictions or )y an ins!icient n!m)er or type o !nctional

!nits% Reconig!ra)le logic e-ploits more program parallelism% 3y dedicating signiicantly lessinstr!ction memory per acti$e comp!ting element* reconig!ra)le de$ices ac#ie$e a ;:-

impro$ement in !nctional density o$er microprocessors% At t#e same time t#is lo"er memory ratio

allo"s reconig!ra)le de$ices to deploy acti$e capacity at a iner grained le$el* allo"ing t#em to

reali6e a #ig#er yield o t#eir ra" capacity* sometimes as m!c# as ;:-* t#an con$entional processors%

T#e #ig# !nctional density c#aracteristic o reconig!ra)le de$ices comes at t#e e-pense ot#e #ig# !nctional di$ersity c#aracteristic o microprocessors% =icroprocessors #a$e e$ol$ed to a

#ig#ly optimi6ed conig!ration "it# clear cost7perormance ad$antages o$er reconig!ra)le arrays ora large set o tas.s "it# #ig# !nctional di$ersity% 3y com)ining a reconig!ra)le array "it# a

processing core "e #ope to ac#ie$e t#e )est o )ot# "orlds%

W#ile it is possi)le to com)ine a con$entional processor "it# commercial reconig!ra)le

de$ices at t#e circ!it )oard le$el* integration radically c#anges t#e i7o costs and design point or )ot#

de$ices* res!lting in a 5!alitati$ely dierent system% Nota)ly* t#e lo"er onc#ip comm!nication costs

allo" eicient cooperation )et"een t#e processor and array at a iner grain t#an is sensi)le "it#discrete designs%

RECON'I$URA*LE COMPUTIN$

W#en "e tal. a)o!t reconig!ra)le comp!ting "eJre !s!ally tal.ing a)o!t FP0A)ased systemdesigns% 2nort!nately* t#at doesnJt 5!aliy t#e term precisely eno!g#% ,ystem designers !se FP0As

in many dierent "ays% T#e most common !se o an FP0A is or prototyping t#e design o an A,IC%

In t#is scenario* t#e FP0A is present only on t#e prototype #ard"are and is replaced )y t#e

corresponding A,IC in t#e inal prod!ction system% T#is !se o FP0As #as not#ing to do "it#

reconig!ra)le comp!ting%

Ho"e$er* many system designers are c#oosing to lea$e t#e FP0As as part o t#e

prod!ction #ard"are% Lo"er FP0A prices and #ig#er gate co!nts #a$e #elped dri$e t#is c#ange% ,!c#systems retain t#e e-ec!tion speed o dedicated #ard"are )!t also #a$e a great deal o !nctional



9/12


le-i)ility% T#e logic "it#in t#e FP0A can )e c#anged i or "#en it is necessary* "#ic# #as many

ad$antages% For e-ample* #ard"are )!g i-es and !pgrades can )e administered as easily as t#eir

sot"are co!nterparts% In order to s!pport a ne" $ersion o a net"or. protocol* yo! can redesign t#einternal logic o t#e FP0A and send t#e en#ancement to t#e aected c!stomers )y email% Once

t#eyJ$e do"nloaded t#e ne" logic design to t#e system and restarted it* t#eyJll )e a)le to !se t#e

ne" $ersion o t#e protocol% T#is is conig!ra)le comp!ting reconig!ra)le comp!ting goes one step!rt#er%

Reconig!ra)le comp!ting in$ol$es manip!lation o t#e logic "it#in t#e FP0A at r!ntime%

In ot#er "ords* t#e design o t#e #ard"are may c#ange in response to t#e demands placed !pon t#e

system "#ile it is r!nning% Here* t#e FP0A acts as an e-ec!tion engine or a $ariety o dierent

#ard"are !nctions B some e-ec!ting in parallel* ot#ers in serial B m!c# as a CP2 acts as an

e-ec!tion engine or a $ariety o sot"are t#reads% We mig#t e$en go so ar as to call t#e FP0A areconig!ra)le processing !nit /RP21%

Reconig!ra)le comp!ting allo"s system designers to e-ec!te more #ard"are t#an t#ey

#a$e gates to it* "#ic# "or.s especially "ell "#en t#ere are parts o t#e #ard"are t#at are

occasionally idle% One t#eoretical application is a smart cell!lar p#one t#at s!pports m!ltiple

comm!nication and data protocols* t#o!g# (!st one a time% W#en t#e p#one passes rom a

geograp#ic region t#at is ser$ed )y one protocol into a region t#at is ser$ed )y anot#er* t#e

#ard"are is a!tomatically reconig!red% T#is is reconig!ra)le comp!ting at its )est* and !sing t#isapproac# it is possi)le to design systems t#at do more* cost less* and #a$e s#orter design and

implementation cycles%

Reconig!ra)le comp!ting #as se$eral ad$antages%

First* it is possi)le to ac#ie$e greater !nctionality "it# a simpler #ard"are design% 3eca!se

not all o t#e logic m!st )e present in t#e FP0A at all times* t#e cost o s!pporting additional

eat!res is red!ced to t#e cost o t#e memory re5!ired to store t#e logic design% Consider again

t#e m!ltiprotocol cell!lar p#one% It "o!ld )e possi)le to s!pport as many protocols as co!ld )eit into t#e a$aila)le on)oard RO=% It is e$en concei$a)le t#at ne" protocols co!ld )e !ploaded

rom a )ase station to t#e #and#eld p#one on an asneeded )asis* t#!s re5!iring no additionalmemory%

T#e second ad$antage is lo"er system cost* "#ic# does not maniest itsel e-actly as yo!

mig#t e-pect% On a lo"$ol!me prod!ct* t#ere "ill )e some prod!ction cost sa$ings* "#ic# res!ltrom t#e elimination o t#e e-pense o A,IC design and a)rication% Ho"e$er* or #ig#er$ol!me

prod!cts* t#e prod!ction cost o i-ed #ard"are may act!ally )e lo"er% We #a$e to t#in. interms o lietime system costs to see t#e sa$ings% ,ystems )ased on reconig!ra)le comp!ting

are !pgrada)le in t#e ield% ,!c# c#anges e-tend t#e !se!l lie o t#e system* t#!s red!cing

lietime costs%

T#e inal ad$antage o reconig!ra)le comp!ting is red!ced timetomar.et% T#e act t#atyo!Jre no longer !sing an A,IC is a )ig #elp in t#is respect% T#ere are no c#ip design andprototyping cycles* "#ic# eliminates a large amo!nt o de$elopment eort% In addition* t#e logic

design remains le-i)le rig#t !p !ntil /and e$en ater1 t#e prod!ct s#ips% T#is allo"s anincremental design lo"* a l!-!ry not typically a$aila)le to #ard"are designers% o! can e$en

s#ip a prod!ct t#at meets t#e minim!m re5!irements and add eat!res ater deployment% In t#ecase o a net"or.ed prod!ct li.e a settop )o- or cell!lar telep#one* it may e$en )e possi)le to

ma.e s!c# en#ancements "it#o!t c!stomer in$ol$ement%

RECON'I$URA*LE HARD,ARE

Traditional FP0As are conig!ra)le* )!t not r!ntime reconig!ra)le% =any o t#e older

FP0As e-pect to read t#eir conig!ration o!t o a serial EEPRO=* one )it at a time% And t#ey can only)e made to do so )y asserting a c#ip reset signal% T#is means t#at t#e FP0A m!st )e reprogrammed

in its entirety and t#at its pre$io!s internal state cannot )e capt!red )eore#and% T#o!g# t#eseeat!res are compati)le "it# conig!ra)le comp!ting applications* t#ey are not s!icient or

reconig!ra)le comp!ting%

In order to )eneit rom r!ntime reconig!ration* it is necessary t#at t#e FP0As in$ol$ed

#a$e some or all o t#e ollo"ing eat!res% T#e more o t#ese eat!res t#ey #a$e* t#e more le-i)le

can )e t#e system design% Deciding "#ic# #ard"are o)(ects to e-ec!te and "#en ,"apping #ard"are

o)(ects into and o!t o t#e reconig!ra)le logic Perorming ro!ting )et"een #ard"are o)(ects or

)et"een #ard"are o)(ects and t#e #ard"are o)(ect rame"or.% O co!rse* #a$ing sot"are managet#e reconig!ra)le #ard"are !s!ally means #a$ing an em)edded processor or microcontroller on

)oard% /We e-pect se$eral $endors to introd!ce singlec#ip sol!tions t#at com)ine a CP2 core and a)loc. o reconig!ra)le logic )y yearJs end%1 T#e em)edded sot"are t#at r!ns t#ere is called t#e r!n



10/12


time en$ironment and is analogo!s to t#e operating system t#at manages t#e e-ec!tion o m!ltiple

sot"are t#reads% Li.e t#reads* #ard"are o)(ects may #a$e priorities* deadlines* and conte-ts* etc% It

is t#e (o) o t#e r!ntime en$ironment to organi6e t#is inormation and ma.e decisions )ased !ponit%

T#e reason "e need a r!ntime en$ironment at all is t#at t#ere are decisions to )e made"#ile t#e system is r!nning% And as #!man designers* "e are not a$aila)le to ma.e t#ese decisions%

,o "e impart t#ese responsi)ilities to a piece o sot"are% T#is allo"s !s to "rite o!r application

sot"are at a $ery #ig# le$el o a)straction% To do t#is* t#e r!ntime en$ironment m!st irst locate

space "it#in t#e RP2 t#at is large eno!g# to e-ec!te t#e gi$en #ard"are o)(ect% It m!st t#en

perorm t#e necessary ro!ting )et"een t#e #ard"are o)(ectJs inp!ts and o!tp!ts and t#e )loc.s o

memory reser$ed or eac# data stream% Ne-t* it m!st stop t#e appropriate cloc.* reprogram t#e

internal logic* and restart t#e RP2% Once t#e o)(ect starts to e-ec!te* t#e r!ntime en$ironment m!stcontin!o!sly monitor t#e #ard"are o)(ectJs stat!s lags to determine "#en it is done e-ec!ting% Once

it is done* t#e caller can )e notiied and gi$en t#e res!lts% T#e r!ntime en$ironment is t#en ree toreclaim t#e reconig!ra)le logic gates t#at "ere ta.en !p )y t#at #ard"are o)(ect and to "ait or

additional re5!ests to arri$e rom t#e application sot"are%

T#e principal )eneits o reconig!ra)le comp!ting are t#e a)ility to e-ec!te larger #ard"are

designs "it# e"er gates and to reali6e t#e le-i)ility o a sot"are)ased sol!tion "#ile retaining t#e

e-ec!tion speed o a more traditional* #ard"are)ased approac#% T#is ma.es doing more "it# less areality% In o!r o"n )!siness "e #a$e seen tremendo!s cost sa$ings* simply )eca!se o!r systems do

not )ecome o)solete as 5!ic.ly as o!r competitors )eca!se reconig!ra)le comp!ting ena)les t#eaddition o ne" eat!res in t#e ield* allo"s rapid implementation o ne" standards and protocols on

an asneeded )asis* and protects t#eir in$estment in comp!ting #ard"are%

W#et#er yo! do it or yo!r c!stomers or or yo!rsel$es* yo! s#o!ld at least consider!sing reconig!ra)le comp!ting in yo!r ne-t design% o! may ind* as "e #a$e* t#at t#e )eneits ar

e-ceed t#e initial learning c!r$e% And as reconig!ra)le comp!ting )ecomes more pop!lar* t#ese

)eneits "ill only increase%

AD#ANTA$ES O' RECON'I$URA*ILIT-

T#e term reconig!ra)le comp!ting #as come to reer to a loose class o em)eddedsystems% =any systemonac#ip /,oC1 comp!ter designs pro$ide reconig!ra)ility options t#at

pro$ide t#e #ig# perormance o #ard"are "it# t#e le-i)ility o sot"are% To most designers* ,oCmeans encaps!lating one or more processing elementsBt#at is* generalp!rpose em)edded

processors and7or digital signal processor /D,P1 coresBalong "it# memory* inp!t7o!tp!t de$ices*

and ot#er #ard"are into a single c#ip% T#ese $ersatile c#ips can perorm many dierent !nctions%

Ho"e$er* "#ile ,oCs oer c#oices* t#e !ser can c#oose only among !nctions t#at already reside

inside t#e de$ice% De$elopers also create A,ICsBc#ips t#at #andle a limited set o tas.s )!t do t#em

$ery 5!ic.ly%

T#e limitation o most types o comple- #ard"are de$icesB,oCs* A,ICs* and generalp!rpose cp!sBis t#at t#e logical #ard"are !nctions cannot )e modiied once t#e silicon design is

complete and a)ricated% Conse5!ently* de$elopers are typically orced to amorti6e t#e cost o ,oCsand A,ICs o$er a prod!ct lietime t#at may )e e-tremely s#ort in today's $olatile tec#nology

en$ironment%

,ol!tions in$ol$ing com)inations o cp!s and FP0As allo" #ard"are !nctionality to )e

reprogrammed* e$en in deployed systems* and ena)le medical instr!ment OE=s to de$elop ne"platorms or applications t#at re5!ire rapid adaptation to inp!t% T#e tec#nologies com)ined pro$ide

t#e )est o )ot# "orlds or systemle$el design% Care!l analysis o comp!tational re5!irements

re$eals t#at many algorit#ms are "ell s!ited to #ig#speed se5!ential processing* many can )eneitrom parallel processing capa)ilities* and many can )e )ro.en do"n into components t#at are split

)et"een t#e t"o% Wit# t#is in mind* it ma.es sense to al"ays !se t#e )est tec#nology or t#e (o) at#and%

Processors are )est s!ited to generalp!rpose processing and #ig#speed se5!ential

processing /as are D,Ps1* "#ile FP0As e-cel at #ig#speed parallel processing% T#e generalp!rpose

capa)ility o t#e cp! ena)les it to perorm system management $ery "ell* and allo"s it to )e !sed to

control t#e content o t#e FP0As contained in t#e system% T#is sym)iotic relations#ip )et"een cp!s

and FP0As also means t#at t#e FP0A can oload comp!tationally intensi$e algorit#ms rom t#e cp!*

allo"ing t#e processor to spend more time "or.ing on generalp!rpose tas.s s!c# as data analysis*and more time comm!nicating "it# a printer or ot#er e5!ipment%



11/12


CONCLUSION

T#ese ne" c#ips called c#ameleon c#ips are a)le to re"ire t#emsel$es on t#e ly tocreate t#e e-act #ard"are needed to r!n a piece o sot"are at t#e !tmost speed%an e-ample o s!c#

.ind o a c#ip is a c#ameleon c#ip%t#is can also )e called a @c#ip on demand

Reconig!ra)le comp!ting goes a step )eyond programma)le c#ips in t#e matter o

le-i)ility% It is not only possi)le )!t relati$ely commonplace to +re"rite+ t#e silicon so t#at it canperorm ne" !nctions in a split second% Reconig!ra)le c#ips are simply t#e e-treme end o

programma)ility%

Hig#ly le-i)le processors t#at can )e reconig!red remotely in t#e ield* C#ameleon's

c#ips are designed to simpliy comm!nication system design "#ile deli$ering increased

price7perormance n!m)ers%

T#e c#ameleon c#ip is a #ig# )and"idt# reconig!ra)le comm!nications processor

/RCP1%it aims at c#anging a system's design rom a remote location%t#is "ill mean more $ersatile

#and#elds%

Its applications are in* dataintensi$e Internet*D,P*"ireless )asestations* $oicecompression* sot"aredeined radio* #ig#perormance em)edded telecom and datacom

applications* -D,L concentrators*i-ed "ireless local loop* m!ltic#annel $oice compression*m!ltiprotocol pac.et and cell processing protocols% Its ad$antages are t#at it can create c!stomi6ed

comm!nications signal processors *it #as increased perormance and c#annel co!nt* and it can more5!ic.ly adapt to ne" re5!irements and standards and it #as lo"er de$elopment costs and red!ce

ris.%

A FUTURISTIC DREAM

One day* someone "ill ma.e a c#ip t#at does e$eryt#ing or t#e !ltimate cons!mer de$ice%

T#e c#ip "ill )e smart eno!g# to )e t#e )rains o a cell p#one t#at can transmit or recei$e calls

any"#ere in t#e "orld% I t#e reception is poor* t#e p#one "ill a!tomatically ad(!st so t#at t#e 5!alityimpro$es% At t#e same time* t#e de$ice "ill also ser$e as a #and#eld organi6er and a player or

m!sic* $ideos* or games%

2nort!nately* t#at c#ip doesn't e-ist today%

It "o!ld re5!ire

le-i)ility

#ig# perormance

lo" po"er

and lo" cost

3!t "e mig#t )e getting closer% No" a ne" .ind o c#ip may res#ape t#e semicond!ctor

landscape% T#e c#ip adapts to any programming tas. )y eecti$ely erasing its #ard"are design andregenerating ne" #ard"are t#at is perectly s!ited to r!n t#e sot"are at #and% T#ese c#ips* reerred

to as reconig!ra)le processors* co!ld tilt t#e )alance o po"er t#at #as preser$ed a decadelong

stando )et"een programma)le c#ips and #ard"ired c!stom c#ips%

T#ese ne" c#ips are a)le to re"ire t#emsel$es on t#e ly to create t#e e-act #ard"are

needed to r!n a piece o sot"are at t#e !tmost speed%an e-ample o s!c# .ind o a c#ip is a

c#ameleon c#ip%t#is can also )e called a @c#ip on demand

@Reconig!ra)le comp!ting goes a step )eyond programma)le c#ips in t#e matter o

le-i)ility% It is not only possi)le )!t relati$ely commonplace to +re"rite+ t#e silicon so t#at it can



12/12


perorm ne" !nctions in a split second% Reconig!ra)le c#ips are simply t#e e-treme end o

programma)ility%

I t#ese adapta)le c#ips can reac# a costperormance parity "it# #ard"ired c#ips*c!stomers "ill c#!c. t#e static #ard"ired sol!tions% And i silicon can indeed )ecome dynamic* t#en

so "ill t#e gadgets o t#e inormation age% No longer "ill yo! #a$e to )!y a camera and a taperecorder% o! co!ld (!st )!y one gadget* and t#en do"nload a ne" !nction or it "#en yo! "ant to

ta.e some pict!res or ma.e a recording% 4!st t#in. o t#e possi)ilities or t#e ic.le cons!mer%

Programma)le logic c#ips* "#ic# are arrays o memory cells t#at can )e programmed to

perorm #ard"are !nctions !sing sot"are tools* are more le-i)le t#an D,P c#ips )!t slo"er and

more e-pensi$e For cons!mers* t#is means t#at t#e day isn't ar a"ay "#en a cell p#one can )e

!sed to tal.* transmit $ideo images* connect to t#e Internet* maintain a calendar* and ser$e as

entertainment d!ring tra$el delays "it#o!t t#e need to pl!g in adapter #ard"are

RE'ERENCES

*OOS

Wei in Presentation * Oct 8::: /T#e part o t#e presentation

regarding C,8::: is co$ered in t#is page1

IEEE conerence on Telecomm!nication* 8::;%

,E*SITES

"""%c#ameleonsystems%com

"""%t#in.digit%com

"""%seminartopics%ino

"""%ieee%org

"""%iec%org

"""%5!ic.sil$ertec#nologies%com

"""%-ilin-%com

http://www.chameleon/http://www.thinkdigit.com/http://www.ieee.org/http://www.iec.org/http://www.quicksilver/http://www.chameleon/http://www.thinkdigit.com/http://www.ieee.org/http://www.iec.org/http://www.quicksilver/

129094123 chameleon chips

Documents