16-bit microcontroller mb96300 series - fujitsu...file: designdifferences16fx.doc...

16-bit MICROCONTROLLER

MB96300 SERIES

List of functional limitations 2008-01-18

European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse 47 63225 Langen, Germany File: DesignDifferences16FX.doc

CI-300010-E-V18-MB96300_List_of_functional_limitations.pdf

European MCU Design Centre CI-300010-E-V18

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Revision History

Version Date Remark 1.0 2006-11-08 Initial version 1.1 2006-11-22 Revised 16FXFL0016 1.2 2006-12-06 Added 16FXFL0022, 16FXFL0023 1.3 2007-01-22 Added 16FXFL0024, 16FXFL0025

Improved part number information in list of affected devices of all individual functional limitation description and list of functional limitations.

1.4 2007-02-08 Added MB96V300BRB 1.5 2007-06-06 Added 16FXFL0026 … 16FXFL0031.

Updated 16FXFL0024 to rev. 3. 1.6 2007-07-04 Changed wording in 16FXFL0030. 1.7 2007-12-03 Added 16FXFL0032, 16FXFL0033, 16FXFL0034 1.8 2007-01-18 Added 16FXFL0035, 16FXFL0036, 16FXFL0037


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Table of contents Overview .................................................................................................................................5 16FXFL0001: Power-on debug feature ...............................................................................17 16FXFL0002: Peripheral access during debug mode .......................................................20 16FXFL0003: CANbus 3 output enable register ................................................................23 16FXFL0004: Guarded access break after conditional branch........................................26 16FXFL0005: Data value break on byte access.................................................................29 16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources ...............32 16FXFL0007: Bit positions in Real Time Clock register WTCKSR...................................35 16FXFL0008: Synchronous start of Programmable Pulse Generators ...........................39 16FXFL0009: Embedded debug support data value break...............................................42 16FXFL0010: Embedded debug support data write protection .......................................45 16FXFL0011: EDSU USART Transmit Interrupt .................................................................48 16FXFL0012: DMA stop when CLKB > CLKP1/2 ...............................................................51 16FXFL0013: LCD prescaler ................................................................................................54 16FXFL0014: CLKP2 divider setting...................................................................................57 16FXFL0015: Wake-up by RTC from timer mode ..............................................................60 16FXFL0016: Interrupt while MOVS/MOVSW is executing ...............................................63 16FXFL0017: Flash read buffer after programming ..........................................................68 16FXFL0018: NMI relocation lock .......................................................................................71 16FXFL0019: Phantom wake-up from timer or sleep mode .............................................74 16FXFL0020: Read value of PDR/EPSR..............................................................................77 16FXFL0021: Initial state of external interrupt flag ...........................................................80 16FXFL0022: Permitted settings for the Flash configuration registers ..........................83 16FXFL0023: Usage of Flash read buffer ...........................................................................87 16FXFL0024: Side effect of disabled DMA controller channels.......................................90 16FXFL0025: Increased current consumption...................................................................94 16FXFL0026: Feature emulation .........................................................................................97 16FXFL0027: Trace function limitation.............................................................................101 16FXFL0028: Stuck on SW instruction break ..................................................................104 16FXFL0029: Limitation in using Operand break points as trace triggers ...................107 16FXFL0030: Limitation in using Pass Count of Operand break points of DSU ..........110 16FXFL0031: Wrong instruction execution detection of DSU........................................113 16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time ....118 16FXFL0033: FLASH Reset................................................................................................122


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16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion ...........126 16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3.............................132 16FXFL0036: EDSU2 register not available on all devices (INT9 source selection) ....135 16FXFL0037: Initial value of some I/O timer registers not correct ................................138


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Overview For some devices a shortcut name was used as in the table below:

Table 1: Relation of device shortcut to product name.

Device shortcut Product name MB9638X MB96384RSA, MB96384RWA, MB96384YSA, MB96384YWA, MB96385RSA, MB96385RWA, MB96385YSA,

MB96385YWA MB96F32X MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA MB96F32XB MB96F326ASB, MB96F326AWB, MB96F326RSB, MB96F326RWB, MB96F326YSB, MB96F326YWB MB96F338 MB96F338RSA, MB96F338RWA, MB96F338YSA, MB96F338YWA, MB96F338USA, MB96F338UWA MB96F348H/T MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA MB96F348H/TB MB96F348CSB, MB96F348CWB, MB96F348HSB, MB96F348HWB, MB96F348TSB, MB96F348TWB, MB96F903HSB,

MB96F905HSB, MB96F906HSB MB96F348H/TC MB96F348CSC, MB96F348CWC, MB96F348HSC, MB96F348HWC, MB96F348TSC, MB96F348TWC, MB96F903HSC,

MB96F905HSC, MB96F906HSC MB96F34XY/R MB96F346ASA, MB96F346AWA, MB96F346RSA, MB96F346RWA, MB96F346YSA, MB96F346YWA, MB96F347ASA,

MB96F347AWA, MB96F347RSA, MB96F347RWA, MB96F347YSA, MB96F347YWA, MB96F348ASA, MB96F348AWA, MB96F348RSA, MB96F348RWA, MB96F348YSA, MB96F348YWA

MB96F34XY/RB MB96F346ASB, MB96F346AWB, MB96F346RSB, MB96F346RWB, MB96F346YSB, MB96F346YWB, MB96F347ASB, MB96F347AWB, MB96F347RSB, MB96F347RWB, MB96F347YSB, MB96F347YWB, MB96F348ASB, MB96F348AWB, MB96F348RSB, MB96F348RWB, MB96F348YSB, MB96F348YWB

MB96F35X MB96F356ASA, MB96F356AWA, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWA MB96F35XB MB96F356ASB, MB96F356AWB, MB96F356RSB, MB96F356RWB, MB96F356YSB, MB96F356YWB MB96F37X MB96F378HSA, MB96F378HWA, MB96F378TSA, MB96F378TWA, MB96F379RSA, MB96F379RWA, MB96F379YSA,

MB96F379YWA MB96F38(8/9) MB96F388HSA, MB96F388HWA, MB96F388TSA, MB96F388TWA, MB96F389RSA, MB96F389RWA, MB96F389YSA,

MB96F389YWA MB96F38X MB96F386RSA, MB96F386RWA, MB96F386YSA, MB96F386YWA, MB96F387RSA, MB96F387RWA, MB96F387YSA,


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Device shortcut Product name MB96F387YWA

MB96F38XB MB96F386RSB, MB96F386RWB, MB96F386YSB, MB96F386YWB, MB96F387RSB, MB96F387RWB, MB96F387YSB, MB96F387YWB


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An overview of the functional limitation and the list of affected devices is given below. This table is showing most recent devices only, which are recommended for new designs. For the list of functional limitations for outdated devices, please refer to Table 3.

Table 2: List of functional limitations and affected devices (most recent devices recommended for new designs).

Functional limitation Issue Page

MB

96V3

00B

RB

MB

96F3

2XB

MB

96F3

38

MB

96F3

48H

/TC

MB

96F3

4XY/

RB

MB

96F3

5XB

MB

96F3

7X

MB

96F3

8(8/

9)

MB

9638

X

MB

96F3

8XB

16FXFL0024: Side effect of disabled DMA controller channels

A DMA controller channel that is not enabled can affect the operation of the DMA controller channel that is enabled.

90 ● ●

16FXFL0032: Divider Change of CLKP2/CLKP3 and Change of Stabilization Time

Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

118 ● ● ● ●

16FXFL0033: FLASH Reset

If a Software Reset, a Watchdog Reset or a Clock Stop Reset is asserted while the Flash memory is being programmed, invalid data may be read subsequently.

122 ● ● ●

16FXFL0034: Watchdog intervals and delay on the watchdog reset assertion

a) The specification of the watchdog intervals in the preliminary hardware manual (up to revision “MB96300_HWM_rev13_20070827”) was wrong.

b) If the watchdog is not cleared within the specified interval time, then the watchdog reset assertion will not be

126 ● ● ● ● ● ●


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MB

96V3

00B

RB

MB

96F3

2XB

MB

96F3

38

MB

96F3

48H

/TC

MB

96F3

4XY/

RB

MB

96F3

5XB

MB

96F3

7X

MB

96F3

8(8/

9)

MB

9638

X

MB

96F3

8XB

immediate (maximum delay is one interval time).

16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3

If LCD Controller is used with a duty cycle of 1/2 or 1/3, all LCD-common drivers (COM0, COM1, COM2, COM3) must be enabled in register LCDCMR:COMEN[3:0] although they are not required. The IO-pins of the not required LCD-common drivers cannot be used for other purposes.

132 ●

16FXFL0036: EDSU2 register not available on all devices (INT9 source selection)

The registers EDSU2_TSEL and EDSU2_RSEL are not available.

135 ● ●

16FXFL0037: Initial value of some I/O timer registers

At certain conditions, some registers of the I/O timer do not show the correct initial value.

138 ● ● ● ●

The following table shows the functional limitations of outdated devices. It is not recommended to start new designs with these devices.


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Table 3: List of functional limitations and affected outdated devices (not recommended for new designs)


MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

96F3

8X

16FXFL0001: Power-on debug feature

Debug Support: Power-on debug feature is not available. 17 ●

16FXFL0002: Peripheral access during debug mode

Debug Support: Read/write access in debug mode will freeze debug system when CLKP1/2 is stopped.

20 ●

16FXFL0003: CANbus 3 output enable register

CANBus channel 3: Output Enable register COER3 has different offset than at other CANbus channels. It is 0xABE. It should be 0xACE.

23 ●

16FXFL0004: Guarded access break after conditional branch

Debug Support: If a guarded access area is defined directly behind a conditional branch instruction, the guarded access break is activated even when the conditional branch is taken.

26 ●

16FXFL0005: Data value break on byte access

Debug Support: Data value break on byte access can not be used. 29 ●

16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources

CLKP2 resources (CAN & Sound generator): interrupts can not wakeup the device from Sleep mode

32 ●

16FXFL0007: Bit positions in Real Time Clock register WTCKSR

RTC: bit position of register WTCKSR:[CKSEL1:CKSEL0] should be bit [9:8], but is [1:0].

35 ●

16FXFL0008: Synchronous start of Programmable Pulse Generators

PPG: synchronous start of multiple channels by external trigger is not ensured. There may be a difference in start time by one CLKP1 cycle

39 ●


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MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

96F3

8X

16FXFL0009: Embedded debug support data value break

EDSU: data value break can generate phantom breaks. 42 ●

16FXFL0010: Embedded debug support data write protection

EDSU: New feature "write data protection" is introduced. 45 ●

16FXFL0011: EDSU USART Transmit Interrupt

EDSU: Transmit interrupt of selected USART can not be mapped to INT9 in addition to receive interrupt.

48 ●

16FXFL0012: DMA stop when CLKB > CLKP1/2

DMA may stop after data transfer has completed when CLKB > CLKP. After this, no more DMA transfers can be done

51 ●

16FXFL0013: LCD prescaler

LCD: Prescaler values do not allow operation of LCD w/ sub-clock/RC clock within frequency limits (frame rate < 90Hz)

54 ●

16FXFL0014: CLKP2 divider setting

CLKP2 (CAN clock): divider value 1:2 only allowed if CLKS1


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MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

96F3

8X

pins. 16FXFL0019: Phantom wake-up from timer or sleep mode

Under certain conditions, a phantom wake-up from timer mode or sleep mode can be generated.

74 ● ●

16FXFL0020: Read value of PDR/EPSR

When PDR/EPSR is read, it returns not the actual value, but the value at the last time of a read or write access to peripheral group 1.

77 ● ●

16FXFL0021: Initial state of external interrupt flag

Initial state of external interrupt flag is '1'. 80 ● ●

16FXFL0022: Permitted settings for the Flash configuration registers

Not all settings of the Flash configuration registers described in the Hardware Manual are allowed.

83 ●

16FXFL0023: Usage of Flash read buffer

The Flash read buffer cannot be used in all operation modes. 87 ●


A DMA controller channel that is not enabled can affect the operation of the DMA controller channel that is enabled.

90 ● ● ● ●

16FXFL0025: Increased current consumption

Some devices have increased current consumption. 94 ●

16FXFL0026: Feature emulation

Some features of MB96300 series devices are not supported by the EVA chip.

97 ●

16FXFL0027: Trace function limitation

The trace function of the MB2198 and MB96V300 based debug system does not work correctly at certain conditions.

101 ●

16FXFL0028: Stuck on Software instruction break can not be used together with interrupts. 104 ●


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MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

96F3

8X

SW instruction break 16FXFL0029: Limitation in using Operand break points as trace triggers

Operand break point 1, 2 and 3 cannot be used as trace triggers. 107 ●

16FXFL0030: Limitation in using Pass Count of Operand break points of DSU

The pass counter of the Operand break points 0 to 3 can detect one operand access as multiple accesses and assert a break, sequencer change or trace trigger (depends on the configuration) before the actual number of accesses occurred.

110 ●

16FXFL0031: Wrong instruction execution detection of DSU

Some features of the DSU do not detect the instruction execution correctly.

113 ●


Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

118 ● ● ●


If a Software Reset, a Watchdog Reset or a Clock Stop Reset is asserted while the Flash memory is being programmed, invalid data may be read subsequently.

122 ● ● ● ● ● ●


c) The specification of the watchdog intervals in the preliminary hardware manual (up to revision “MB96300_HWM_rev13_20070827”) was wrong.

d) If the watchdog is not cleared within the specified interval time, then

126 ● ● ● ● ● ● ●


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MB

96V3

00R

B

MB

96F3

2X

MB

96F3

48H

/T

MB

96F3

48H

/TB

MB

96F3

4XY/

R

MB

96F3

5X

MB

96F3

8X

the watchdog reset assertion will not be immediate (maximum delay is one interval time).

16FXFL0035: Limitation when using LCD with duty cycle 1/2 or 1/3

If LCD Controller is used with a duty cycle of 1/2 or 1/3, all LCD-common drivers (COM0, COM1, COM2, COM3) must be enabled in register LCDCMR:COMEN[3:0] although they are not required. The IO-pins of the not required LCD-common drivers cannot be used for other purposes.

132 ● ●

16FXFL0036: EDSU2 register not available on all devices (INT9 source selection)

The registers EDSU2_TSEL and EDSU2_RSEL are not available. 135 ● ● ● ●

16FXFL0037: Initial value of some I/O timer registers

At certain conditions, some registers of the I/O timer do not show the correct initial value.

138 ● ● ● ● ●

FUJITSU SEMICONDUCTOR

Power-on debug feature

16FX functional limitation 16FXFL0001

European MCU Design Centre (EMDC) Fujitsu Microelectronics Europe GmbH Pittlerstrasse 47 63225 Langen, Germany

European MCU Design Centre 16FXFL0001 ver. 2

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Revision History

Version Date Remark 1 2006-10-30 Initial version 2 2007-01-19 Improved part number information in list of affected devices


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16FXFL0001: Power-on debug feature

1. Description of functional limitation The Power-on debug feature is not available.

2. List of affected Devices MB96V300RB

3. Detailed explanation The Power-on debug feature enables debugging the application right after powering up. This is implemented by separating the power supply for the application part and the debug support logic part of 16FX EVA chips.

This feature is not available on the affected devices.

4. Possible workaround None.

5. Fujitsu countermeasure Future 16FX EVA chips will support the Power-on debug feature.


Peripheral access during debug mode




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Revision History



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16FXFL0002: Peripheral access during debug mode

1. Description of functional limitation When the EVA chip is in debug mode and the feature is used to stop the peripheral clocks CLKP1/CLKP2 while being in debug mode, any read/write access to peripherals in clock domain CLKP1 or CLKP2 will freeze the MCU.


3. Detailed explanation 16FX EVA chips offer the feature to stop peripheral clocks CLKP1 and CLKP2 while being in debug mode. This feature prevents that for example timers continue counting while the application is stopped by the user for inspection. If the counters would continue operation, they may overflow and the application would have to handle according interrupts directly after leaving the debug mode.

However, since CLKP1 and CLKP2 are stopped when this feature is chosen, the debug system freezes when the user tries to read or write to registers in the CLKP1 or CLKP2 domain.

4. Possible workaround Memory content can be read or written as long as no registers in CLKP1 or CLKP2 domain are referenced. Avoid reading/writing to registers in CLKP1 and CLKP2 domain while in debug mode.

5. Fujitsu countermeasure Future 16FX EVA chips will enable to read register contents in CLKP1 and CLKP2 domain while being in debug mode, even when CLKP1 and CLKP2 are stopped. Write access to registers in CLKP1 or CLKP2 domain will be ignored.


CANbus 3 output enable register




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Revision History



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16FXFL0003: CANbus 3 output enable register

1. Description of functional limitation CANbus channel 3 Output Enable Register COER3 has different offset than at other CANbus channels. It is 0xABE. It should be 0xACE.


3. Detailed explanation The register layout of all CANbus controllers is the same, so that drivers can make use of a base address for each CANbus and constant offsets to address each register of the CANbus controller with the given base address.

However, CANbus controller 3 has register COER3 on another offset than the other CANbus controllers.

4. Possible workaround Do not use CAN base address and register offset scheme, but individual register addresses as defined in 16FX C-header file.

5. Fujitsu countermeasure Future 16FX chips having CANbus controller channel 3 will have COER3 at address 0xACE.


Guarded access break after conditional branch




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Revision History



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16FXFL0004: Guarded access break after conditional branch

1. Description of functional limitation Debug Support: If a guarded access area is defined directly behind a conditional branch instruction, the guarded access break is activated even when the conditional branch is taken.


3. Detailed explanation See above.


5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation.


Data value break on byte access




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Revision History



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16FXFL0005: Data value break on byte access

1. Description of functional limitation Debug Support: Data value break on byte access can not be used.


3. Detailed explanation Data value break on byte access can not be used. The byte on the other byte lane is not masked correctly (only lower bit is masked, not complete byte).

Operand break (w/o data value break feature) is working without restriction on byte size and word size operands.

4. Possible workaround None. Do not use data value break on byte size. Use only data value break on words.

5. Fujitsu countermeasure Future 16FX EVA chips will not have this limitation.


Wake-up from sleep mode by CLKP2 clock domain resources




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Revision History



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16FXFL0006: Wake-up from sleep mode by CLKP2 clock domain resources

1. Description of functional limitation Resources in CLKP2 domain (like CANbus, Sound Generator) can not wake-up the device from sleep mode.


3. Detailed explanation

4. Possible workaround All CANbus RX pins also have an external interrupt. External interrupts are located in the CLKP1 domain, which is not affected. Hence, for wake-up by CANbus, it is possible to use the external interrupt on the RX pin to wake-up the MCU from any low power mode. However, the wake-up event will always occur when the external interrupt detects a sensitive event on the RX/INT

5. Fujitsu countermeasure Future 16FX chips will not have this limitation.


Bit positions in Real Time Clock register WTCKSR




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Revision History



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16FXFL0007: Bit positions in Real Time Clock register WTCKSR

1. Description of functional limitation RTC: bit position for write access of register WTCKSR:[CKSEL1:CKSEL0] should be bit [9:8], but is [1:0].


3. Detailed explanation 7 6 5 4 3 2 1 0 - - - - - - INTE4 INT4 WTCER - - - - - - R/W R/W Initial value X X X X X X 0 0 15 14 13 12 11 10 9 8 - - - - - - CKSEL1 CKSEL0 WTCKSR - - - - - - R/W R/W Initial value X X X X X X 0 0

Registers WTCER and WTCKSR are located at the lower and upper byte of a 16-bit word.

At 16-bit read access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, and bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are located at bit 9 and 8, respectively.

However, at 16-bit write access, WTCER:INT4 and WTCER:INTE4 are located at bits 1 and 0, but bits WTCKSR:CKSEL1 and WTCKSR:CKSEL0 are also located at bit 1 and 0, respectively.

Hence,

1. when writing a 16-bit word to {WTCKSR, WTCER} the value on bit position 1 and 0 is written into WTCER:INTE4 and WTCER:INT4, and also into WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

2. when writing a 8-bit word to WTCER the value on bit position 1 and 0 of WTCER is also written into WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

Read access to these register is not affected.


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4. Possible workaround Do not use byte access to write the content of WTCER, because it will overwrite former content of WTCKSR:CKSEL1 and WTCKSR:CKSEL0.

To set the content of {WTCKSR, WTCER} to the binary value XXXX.XXab.XXXX.XXcd, use the following procedure:

Step Content of WTCKSR:INTE4, INT4

Content of WTCER:CKSEL1,CKSEL0

1. Make sure the RTC interrupt is disabled as by initial value of the Interrupt Control Register ICR for the interrupt vector of the RTC.

Initial value Initial value

2. Write the content of {WTCKSR, WTCER} by 16-bit access, value = XXXX.XXab.XXXX.XXcd

c, d c, d

3. Write the content of WTCKSR by 8-bit access, value = XXXX.XXab a, b c, d

4. Continue as usual, i. e. enable interrupts etc.



Synchronous start of Programmable Pulse Generators




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Revision History



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16FXFL0008: Synchronous start of Programmable Pulse Generators

1. Description of functional limitation For the Programmable Pulse Generators, the synchronous start of multiple channels by external trigger is not ensured. There may be a difference in start time by one CLKP1 cycle.






Embedded debug support data value break




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Revision History



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16FXFL0009: Embedded debug support data value break

1. Description of functional limitation The Embedded Debug Support which can be built with the memory patch function, features a data value break. The data value break can generate phantom breaks.


3. Detailed explanation When using the data value break of the Embedded Debug Support implemented by the Memory Patch function, a break condition can be generated though the condition was not met.

4. Possible workaround None. Do not use data value break function in the embedded debug support of the memory patch unit or check in the interrupt handler, that the data value has matched.



Embedded debug support data write protection




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Revision History



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16FXFL0010: Embedded debug support data write protection

1. Description of functional limitation The memory patch unit’s embedded debug support does not feature data write protection.


3. Detailed explanation The data patch function allows superseding the values read from a memory location by a value stored in the memory patch function. This is implemented by redirecting read accesses to the memory patch function. The memory location to be patched is not selected.

However, write accesses to the memory location are not redirected.

4. Possible workaround None

5. Fujitsu countermeasure Future 16FX chips feature also write access redirection to the memory patch function. By this, it is possible to implement a write protection.


EDSU USART Transmit Interrupt




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Revision History



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16FXFL0011: EDSU USART Transmit Interrupt

1. Description of functional limitation The register EDSU does not allow to map the transmit interrupt of the USART, which is selected by EDSU:SEL1, EDSU:SEL0, to the INT9 interrupt. However, performance of a debug system can be increased by offering the possibility to map the selected USART’s transmit interrupt to the INT9 interrupt.




5. Fujitsu countermeasure Future 16FX chips’ EDSU register feature the bits EDSU:TIE and EDSU:TINT to map the selected USART’s transmit interrupt to the INT9 interrupt.


DMA stop when CLKB > CLKP1/2




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Revision History



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16FXFL0012: DMA stop when CLKB > CLKP1/2

1. Description of functional limitation DMA may stop after data transfer has completed when CLKB > CLKP. After this, no more DMA transfers can be done.



4. Possible workaround None. Do not use DMA on CLKP1 domain devices, when CLKB > CLKP1. Do not use DMA on CLKP2 domain devices, when CLKB > CLKP2.

5. Fujitsu countermeasure Future 16FX MCUs will be fixed to allow usage of DMA when CLKB > CLKP1 and CLKB > CLKP2..


LCD prescaler




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Revision History



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16FXFL0013: LCD prescaler

1. Description of functional limitation The LCD prescaler values do not allow operation of LCD w/ sub-clock/RC clock within frequency limits (frame rate < 90Hz).




5. Fujitsu countermeasure Future 16FX MCUs will offer different prescaler seetings in the LCR register.

Old setting of LCR:FP1,FP0:

FP1 FP0 When peripheral clock CLKP1 is selected

When sub clk CLKSC or RC clock CLKRC is selected

0 0 FCLKP1/(213 X N) FCLKP1/(23 X N) 0 1 FCLKP1/(214 X N) FCLKP1/(24 X N) 1 0 FCLKP1/(215 X N) FCLKP1/(25 X N) 1 1 FCLKP1/(216 X N) FCLKP1/(26 X N)

New setting of LCR:FP1,FP0:

FP1 FP0 When peripheral clock CLKP1 is selected

When sub clk CLKSC or RC clock CLKRC is selected

0 0 FCLKP1/(213 X N) FCLKP1/(28 X N) 0 1 FCLKP1/(215 X N) FCLKP1/(29 X N) 1 0 FCLKP1/(217 X N) FCLKP1/(210 X N) 1 1 FCLKP1/(219 X N) FCLKP1/(211 X N)


CLKP2 divider setting




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Revision History



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16FXFL0014: CLKP2 divider setting

1. Description of functional limitation CLKP2 divider setting as defined by CKFCR:PC2D[3:0] = ‘0001’ can only be used for frequency of:

• CLKS2


Wake-up by RTC from timer mode




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Revision History



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16FXFL0015: Wake-up by RTC from timer mode

1. Description of functional limitation The real-time clock can not wake-up the MCU from timer mode




5. Fujitsu countermeasure Future 16FX MCUs will not have this limitation.


Interrupt while MOVS/MOVSW is executing




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Revision History

Version Date Remark 1 2006-11-03 Initial version 2 2006-11-14 Improved description, added workarounds, added that Fujitsu will

offer modified Assembler that enables workaround by command-line switch -@movs_16FX

3 2006-11-22 Added list of affected library functions 4 2007-01-19 Improved part number information in list of affected devices


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16FXFL0016: Interrupt while MOVS/MOVSW is executing

1. Description of functional limitation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes.

2. List of affected Devices MB96V300RB, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA

3. Detailed explanation When MOVSI, MOVSD, MOVSIW or MOVSDW instruction is executed and the source start address is an odd address (address not dividable by 2) and an interrupt is accepted by the CPU, then the fetched interrupt vector is invalid and the application crashes.

When memory model “small” or “medium” (Data address space 16bit), the instructions MOVSI, MOVSD, MOVSIW or MOVSDW are used by the Softune C-compiler for the following C-language constructs:

C-language construct Example • Passing an argument of type struct or

union to a function

• The object which is passed as argument must start at an odd address

typedef struct {

int len;

char buf[20];

} my_type;

void procedure_a(my_type);

my_type my_struct;

procedure_a(my_struct);

// Problem, if my_struct has odd address

• Passing a return value of a function of type struct or union or double.

typedef struct { int len; char buf[20]; } my_type; my_type my_struct; my_type procedure_b(void); my_struct = procedure_b(); // Problem, if return value of procedure_b // is on odd address.

• Initializing a local variable of type struct or union

struct { int len; char buf[20] } my_struct = { 6, “Hello!” }; // Problem, if my_struct is on odd address.

• Copy variables of type struct or union or double

struct { int len; char buf[20] } my_struct_a, my_struct_b; my_struct_a = my_struct_b;


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C-language construct Example // Problem, if my_struct_b is on odd address

• Passing an argument to a function which is the return value of a previous function call of type double

double fabs(double); double sin(double); double x; … x = fabs(sin(x));

• Sign inversion of a variable of type double

double x, y; y = -x; // Problem if x is on odd address.

The following table lists the library functions that are using the MOVSI, MOVSD, MOVSIW or MOVSDW instruction in certain memory models:

Memory model Library function name LARGE COMPACT SMALL MEDIUM

acos yes yes yes yes asin yes yes yes yes atan yes yes yes yes atan2 yes yes yes yes div yes yes yes yes ldiv yes yes yes yes log yes yes yes yes log10 yes yes yes yes pow yes yes yes yes tan yes yes yes yes atof yes yes ceil yes yes cos yes yes cosh yes yes exp yes yes floor yes yes fmod yes yes fprintf yes yes fscanf yes yes modf yes yes printf yes yes scanf yes yes sin yes yes sinh yes yes sprintf yes yes sscanf yes yes strtod yes yes tanh yes yes vfprintf yes yes vprintf yes yes vsprintf yes yes


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4. Possible workaround Workarounds rely on exclusion of one of the three conditions of this limitation. Hence:

3. Avoid using MOVSI, MOVSD, MOVSIW or MOVSDW instruction. You can do by avoiding using above mentioned C-language constructs. Or you can only use memory model “Large” or “Compact”.

4. Avoid odd addresses for variables of type struct, union or double. When MOVSI, MOVSD, MOVSIW or MOVSDW is used with variables on even addresses, there is no limitation.

5. Avoid accepting interrupts while MOVSI, MOVSD, MOVSIW or MOVSDW is executing. This can be performed by the following modification of the assembly language code, which disables interrupts before executing MOVSI and re-enables it after MOVSI finishes:

Original code Modified code

MOVSI DTB, ADB

PUSHW PS

AND CCR, #0x0BF

MOVSI DTB, ADB

POPW PS

5. Fujitsu countermeasure 1. By November 30, 2006, Fujitsu will offer a modified version of 16LX/16FX Assembler

tool.

The new Assembler tool will have two new command line switches:

Switch Call example Effect -@movs_16FX fasm907s -cpu MB96V300RB -@movs_16FX Special code will be generated in which

interrupts are disabled during execution of MOVSI, MOVSD, MOVSIW or MOVSDW

-@Xmovs_16FX fasm907s -@movs_16FX -@Xmovs_16FX Ignore -@movs_16FX option (default behavior)

2. By November 30, 2006, Fujitsu will offer a library compiled with the modified Assembler tool with the command line switch to apply the workaround activated.

3. Future MCUs will not have this limitation.


Flash read buffer after programming




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Revision History



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16FXFL0017: Flash read buffer after programming

1. Description of functional limitation During programming the Flash, the Flash Code and Data read buffer content becomes invalid.

2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA


4. Possible workaround Before programming, disable Flash read buffers by programming MFMCS:CRBE, DRBE, SFMCS:CRBE, DRBE.

5. Fujitsu countermeasure Future MCUs will not have this limitation.


NMI relocation bit lock




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Revision History



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16FXFL0018: NMI relocation lock

1. Description of functional limitation Even when NMI is enabled, it is possible to relocate the NMI function to the NMI_R pin or vice versa by changing the value of PRRR7:NMI_R. By this, the NMI function can be deactivated or issued, depending on the state of the NMI and NMI_R pins.




5. Fujitsu countermeasure Future MCUs will not have this limitation. The bit PRRR7:NMI_R is locked when the NMI function is enabled.


Phantom wake-up from timer- or sleep mode




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Revision History



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16FXFL0019: Phantom wake-up from timer or sleep mode

1. Description of functional limitation A phantom wake-up from timer mode or sleep mode can be generated.



4. Possible workaround After wake-up, application should check for wake-up cause and return to sleep/timer mode if no wake-up cause was found.



Read value of PDR/EPSR




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Revision History



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16FXFL0020: Read value of PDR/EPSR

1. Description of functional limitation When the general purpose ports’ PDR/EPSR are read, the read value is not the value at the time, the read is executed, but the value at the last time of a read or write access to any resource of clock domain CLKP1.



4. Possible workaround Read the PDR/EPSR register twice and use last value.



Initial state of external interrupt flag




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Revision History



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16FXFL0021: Initial state of external interrupt flag

1. Description of functional limitation The initial state of the external interrupt flags EIRRn:ER[7:0] have initial value ‘1’ instead of required value ‘0’.



4. Possible workaround Do not rely on initial value of EIRR.



Permitted settings for the Flash configuration registers




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Revision History

Version Date Remark 1 2006-11-28 Initial version 2 2006-12-06 Revised header, 16FXFL number, formatting of tables 3 2007-01-19 Improved part number information in list of affected devices


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16FXFL0022: Permitted settings for the Flash configuration registers

1. Description of functional limitation Not all settings of the Flash configuration registers described in the Hardware Manual are allowed. In certain cases this leads to a higher number of wait cycles.

2. List of affected Devices MB96F348HSA, MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA

3. Detailed explanation Not all features of the Flash interface are supported by the affected devices. Hence some of the recommended settings in the HWM do not apply for these devices. Instead the Flash interface must be configured as described in the next chapter.

4. Possible workaround • The MFMTC0:ADS and SFMTC0:ADS bits must always be set to ‘1’.

• The MFMTC0:CLKBW and SFMTC0:CLKBW bits must always be set to ‘1’.

• If the CLKB frequency is lower than the CLKS1 frequency (CLKB divider setting CKFRC:BCD not “0000”), disable the code and data read buffer (Set MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to ‘0’).

Recommended settings for Synchronous reading:

Max CLKS1 frequency

CKFCR:BCD setting

FMTC setting (number of Wait States)

Code/data read buffer

Div1 Enabled or disabled 25MHz Div2 – Div16

0239h (1WS) Disabled

Div1 Enabled or disabled Div2

223Ah (2WS) Disabled 50MHz

Div3 – Div16 2239h (1WS) Disabled

Div1 4B3B (3WS) Enabled or disabled Div2, Div3 4B3A (2WS) Disabled 56MHz Div4 – Div16 4B39 (1WS) Disabled


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Recommended settings for Synchronous reading and writing:

Max CLKS1 frequency

CKFCR:BCD setting




223Ah (2WS) Disabled


4B3D (5WS) Disabled

Recommended settings for Asynchronous reading/writing:

Max CLKS1 frequency

CKFCR:BCD setting




0231h (1WS) Disabled



Usage of Flash Read buffer




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Revision History

Version Date Remark 1 2006-11-28 Initial version 2 2006-12-06 Revised header 3 2007-01-19 Improved part number information in list of affected devices


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16FXFL0023: Usage of Flash read buffer

1. Description of functional limitation The Flash read buffer cannot be used in all operation modes.

2. List of affected Devices MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA

3. Detailed explanation The Flash read buffer cannot be used in the following two cases:

• A divided CLKB clock is used (CLKS1 frequency higher than CLKB frequency)

• During Flash programming and erasing

In both cases, invalid data could be read from the Flash.

4. Possible workaround • Usage of a divided CLKB clock: Disable all read buffer by setting MFMCS:DRBE,

CRBE and SFMCS:DRBE,CRBE to ‘0’ before writing to the CKFCR:BCD bits.

• Flash programming and erasing: Disable all read buffer by setting MFMCS:DRBE, CRBE and SFMCS:DRBE,CRBE to ‘0’ before submitting the program/erase command. The read buffer can be enabled again after termination of the program/erase algorithm.



Side effect of disabled DMA controller channels




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Revision History

Version Date Remark 1 2007-01-14 Initial version 2 2007-01-19 Improved part number information in list of affected devices 3 2007-06-06 Extended list of affected devices: MB96F348HSA,

MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA (as already in chapter “Overview”).

4 2008-01-10 Extended list of devices: B versions of MB9634x and MB9638x.


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1. Description of functional limitation A DMA controller channel that is not enabled can affect the operation of a DMA controller channel that is enabled, when the content of the DISEL register of both channels is the same.

2. List of affected Devices MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CWA, MB96F348HSA, MB96F348HWA, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TWA, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96V300RB-ES

3. Detailed explanation A DMA controller channel x that is not enabled (DER:ENx = 0), for which the content of the DISEL register is the same as the content of the DISEL register of a DMA controller channel y, that is enabled (DER:ENy = 1), can affect the operation of the DMA controller channel y.

The effect is that if DMA controller channel y is receives an interrupt, it performs the data transfer correctly, but the interrupt is not filtered correctly. Instead of the interrupt being filtered as long as the Data Count register (DCT) is not 0, the interrupt is forwarded to the CPU. Hence, the DMA interrupt service routine is called at each data transfer and not only after the DMA has completed the transfer.

4. Possible workaround DISEL registers of DMA controller channels which are not intended to be used must be initialized to a value that is not used by DMA controller channels which are used.

For example, all DISEL registers are initialized to a value that is never used by DMA, e. g. 12 (= delayed interrupt).

Please take care not to overwrite the value of the DISEL register of disabled DMA channels later in the application.


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5. Fujitsu countermeasure Type A: First countermeasure is to initialize DISEL registers at reset to a value that is never used by DMA controller channels (12 = delayed interrupt). For products of this type, please take care that the software does not override the content of the DISEL register of disabled DMA channels to a value that is used by enabled DMA channels.

Type B: Second workaround is to remove the functional limitation. For these products, even when DISEL register content of a disabled channel x is the same as DISEL register content of enabled channel y, operation of channel y is not affected. Nevertheless, the content of all DISEL registers is reset to 12 at reset.

The following table gives an overview of the status of different products.

Product Functional limitation present

Countermeasure type

MB96V300RB MB96F348HSA, MB96F348HWA, MB96F348TSA, MB96F348TWA, MB96F348CSA, MB96F348CWA

Yes No countermeasure, please use software workaround

MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB

Yes Type A. Please take care not to override DISEL register of disabled channels to a value used in enabled channels.

All other 16FX devices No Type B


Increased current consumption




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Revision History



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16FXFL0025: Increased current consumption

1. Description of functional limitation Some devices have increased current consumption.

2. List of affected Devices MB96F348HSA, MB96F348TWA, MB96F348HWA, MB96F348CWA, MB96F348CSA

3. Detailed explanation Some devices have increased current consumption as shown in the table below.

Device Approximate additional current consumption Unit MB96F348HSA 140 µA MB96F348TWA 140 µA MB96F348HWA 280 µA

4. Possible workaround There is no workaround available.

5. Fujitsu countermeasure Future MCUs will not have this increased current consumption.


Feature emulation




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Revision History

Version Date Remark 1 2007-02-16 Initial version 2 2007-04-17 Added WOT for MB96340, MB96320, MB96350 series 3 2007-07-18 Added relocation for ICU 2, 3, 4, 5


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16FXFL0026: Feature emulation

1. Description of functional limitation Some features of MB96300 series devices are not supported by the EVA chip.

2. List of affected Devices MB96V300RB-ES

3. Detailed explanation The following features of MB96300 series devices are not supported by the affected device

Feature Register Pin function

USART 7 PRRR8:SIN7_R, PRRR8:SOT7_R, PRRR8:SCK7_R USART 8 PRRR8:SIN8_R, PRRR8:SOT8_R, PRRR8:SCK8_R USART 9 PRRR8:SIN9_R, PRRR8:SOT9_R, PRRR9:SCK9_R Clock Output Function channel 0

PRRR9:CKOT0_R

Output Compare Unit 10 PRRR9:OUT10_R Free Running Timer 2 PRRR9:FRCK_2 Sound Generator 1 PRRR9:SGA1_R, PRRR9:SGO1_R Input Capture Unit 2, 3, 4, 5

PRRR4:IN2_R, PRRR4:IN3_R, PRRR4:IN4_R, PRRR:IN5_R

Programmable Pulse Generator 8

PRRR10:PPG8_R, PRRR10:TTG8_R















External bus chip selects 0, 1, 2, 4, 5

PRRR12:CS0_R, PRRR12:CS1_R, PRRR12:CS2_R, PRRR12:CS4_R, PRRR12:CS5_R

WOT output of Real time clock

WTCR:OE (bit available, but no function if a device of series MB96340, MB96320 or MB96350 is emulated)

WOT


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4. Possible workaround No workaround is possible.

5. Fujitsu countermeasure Future EVA chips will not have this limitation. MB96V300RB-ES will be updated by MB96V300BRB-ES.


Trace function limitation




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Revision History

Version Date Remark 1 2007-04-04 Initial version


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16FXFL0027: Trace function limitation

1. Description of functional limitation Reading trace data of the MB2198 and MB96V300 based debug system does not work correctly at certain conditions.


3. Detailed explanation Under certain conditions it is not possible to read out the trace data. The probability of the problem depends on the number of trace events which occur at a break. The Trace RAW shows the address 0x000000 for each trace frame. The shown instructions are meaningless. Because the other Trace views are deduced from the RAW data, these show also invalid data.

The trace data are nevertheless recorded correctly in the Trace memory.

4. Possible workaround When the Trace shows this symptom, manually perform a Single Step. This results in correct reading of the Trace buffer and hence correct display of the trace.

5. Fujitsu countermeasure The limitation will be corrected on MB96V300BRB-ES.


Stuck on SW instruction break




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Revision History



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16FXFL0028: Stuck on SW instruction break

1. Description of functional limitation Software instruction break can not be used together with interrupts.


3. Detailed explanation • If interrupts are occurring together with using SW instruction breaks, it could cause wrong

behaviour of the MCU:

• (1) A wrong branch address to the IRQ handler could happen at simultaneous occurrence of decoding INTE instruction (SW break entry) and an IRQ event. The debugger application will loose connection to the MCU.

• (2) The application seems to stuck at the break point if an IRQ is already occurred during staying in a break point. Pressing the continue button to leave the break point seems to have no effect (except handling the IRQ).

4. Possible workaround Use hardware instruction break instead.

5. Fujitsu countermeasure The limitation will be fixed on MB96V300BRB.


Limitation in using Operand break points as trace trigger




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Revision History



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16FXFL0029: Limitation in using Operand break points as trace triggers

1. Description of functional limitation Operand break point 1, 2 and 3 cannot be used as trace triggers.


3. Detailed explanation Some break channels of the 16FX-DSU can be used to start and stop tracing (Trace trigger). Instruction break channel 0 to 3 and Operand break channel 0 to 3 are intended for use as Trace trigger.

On the affected device, Trace trigger functionality of Operand break channel 1 to 3 is not available.

4. Possible workaround No workaround available.

5. Fujitsu countermeasure The limitation will be fixed on MB96V300BRB-ES.


Limitation in using Pass Count of Operand break points of DSU




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Revision History

Version Date Remark 1 2007-04-19 Initial version 2 2007-07-04 Changed wording (Pass count instead of Detection Counter)


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16FXFL0030: Limitation in using Pass Count of Operand break points of DSU

1. Description of functional limitation The pass counter of the Operand break points 0 to 3 can detect one operand access as multiple accesses and assert a break, sequencer change or trace trigger (depends on the configuration) before the actual number of accesses occurred.


3. Detailed explanation For all four operand break points of the 16FX-DSU a pass count can be used. In the pass counter the number of detection events for the corresponding operand break point can be configured. The counter is decremented at every detection event. When the counter has elapsed the configured function will be triggered (e.g. Break, sequencer change, trace trigger).

On MB96V300RB-ES the counter may detect a single break event as multiple events and trigger the configured function too early. This misbehaviour depends on the ongoing bus transfers.




Wrong instruction execution detection of DSU




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Revision History



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16FXFL0031: Wrong instruction execution detection of DSU

1. Description of functional limitation Some features of the DSU do not detect the instruction execution correctly.

Trace start/stop event detection

If a trace start/stop event is set at an instruction after a conditional branch instruction and the branch is taken, the event occurs accidentally even if the instruction is not executed.

The trace status changes to ‘enabled’ or ‘disable’ depending on the configuration of the Trace event. A ‘Trace trigger’ frame is recorded to the Trace memory.

Example: label:

INSTR1 INSTR2 INSTR3 COND_BRANCH label: INSTR4 Trace start or stop set to this instruction INSTR5

If the condition for COND_BRANCH matches and the CPU jumps to ‘label’, the trace trigger is hit nevertheless.

Real time instruction monitoring

If an instruction monitoring address is set to an instruction after a conditional branch instruction and the branch is taken, the instruction execution is indicated at the pin even if the instruction is not executed.



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3. Detailed explanation The reason for this behaviour is that the CPU starts executing the instruction located after the conditional branch (INSTR4) but does not finish it. When the CPU has evaluated the branch condition and the condition is TRUE, it continues the execution at the branch target address (INSTR1) and discards the instruction after the branch (INSTR4). The DSU interprets this CPU behaviour wrongly as ‘execution of address after the conditional branch instruction’.

Following instructions are affected: CBNE_A_IMM_rel CWBNE_A_IMM_rel BBC_IOB_rel BBC_DIRB_rel BBC_ADRB_rel BBS_IOB_rel BBS_DIRB_rel BBS_ADRB_rel SBBS_ADRB_rel CWBNE_ea_IM_rel CBNE_ea_IMM_rel DBNZ_ea DWBNZ_ea Bcc_rel

Trace start/stop event detection

16FX-DSU4 support two different kinds of Trace start/stop events: triggered by Operand break channel or triggered by Instruction break channel. This limitation is regarding the Instruction break.

Assuming that an Instruction break channel is configured as Trace start or Trace stop event and the address is configured to point to an instruction after a conditional branch instruction (e.g. BCC). If the CPU executes the conditional branch and jumps to the branch target address the Trace start or Trace stop event is triggered. This will cause the trace to start or stop – depending on the configuration.

Real time instruction monitoring

16FX-DSU support real time instruction monitoring which 4 addresses. An execution of the configured address can be monitored at 4 different pins of MB96V300RB.

Assuming that a Real time instruction monitoring address is set to an instruction after a conditional branch, the execution is indicated even if the CPU branches to the jump target of the branch.


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4. Possible workaround Do not use instructions after conditional branch instructions as Trace start or Trace stop events or for real time instruction monitoring.



Divider Change of CLKP2/CLKP3 and Change of Stabilization Time




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Revision History

Version Date Remark 1 2007-11-12 Initial version 2 2007-11-14 Typo correction: 6 cycles SC_T[6] wait time is needed after SUB

clock stabilization time change (not after MAIN clock stab.change)3 2007-11-15 MB96F387 removed from list of affected devices 4 2007-11-19 Better description of the Workaround (example to ensure the wait

time in between divider change by peripheral access)


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1. Description of functional limitation Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

2. List of affected Devices MB96F326ASA, MB96F326ASB, MB96F326AWA, MB96F326AWB, MB96F326RSA, MB96F326RSB, MB96F326RWA, MB96F326RWB, MB96F326YSA, MB96F326YSB, MB96F326YWA, MB96F326YWB, MB96F348CSB, MB96F348CSC, MB96F348CWB, MB96F348CWC, MB96F348HSB, MB96F348HSC, MB96F348HWB, MB96F348HWC, MB96F348TSB, MB96F348TSC, MB96F348TWB, MB96F348TWC, MB96F356ASA, MB96F356ASB, MB96F356AWA, MB96F356AWB, MB96F356RSA, MB96F356RSB, MB96F356RWA, MB96F356RWB, MB96F356YSA, MB96F356YSB, MB96F356YWA, MB96F356YWB, MB96F903HSB, MB96F903HSC, MB96F905HSB, MB96F905HSC, MB96F906HSB, MB96F906HSC, MB96V300BRB-ES

3. Detailed explanation Changing of clock divider settings of CLKP2 and CLKP3 and change of stabilization time of the main clock or sub clock may be ignored, if the previous change has happened too short before.

A minimum number of 6 cycles CLKB plus 6 cycles CLKS2 is needed for the clock divider settings, before the divider setting is allowed to be changed again.

A minimum number of 6 cycles CLKS1 plus 6 cycles MC_T[6] (main clock timer, bit6) is needed, before the main clock stabilization time is allowed to be changed again.

A minimum number of 6 cycles CLKS1 plus 6 cycles SC_T[6] (sub clock timer, bit 6) is needed, before the sub clock stabilization time is allowed to be changed again.

Following configuration registers are affected:

• CKFCR_PC2D (Peripheral group 2 clock divider)

• PLLCR_PC3D (Peripheral group 3 clock divider)

• CKSSR_MCST (Main clock stabilization time)

• CKSSR_SCST (Sub clock stabilization time)

Reason is the relaxation time of the used synchronizer circuit, which is needed to ensure data consistency of multiple bits.


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4. Possible workaround (1) Ensure minimum relaxation time of 6 cycles CLKB and 6 cycles CLKS2 before changing the clock divider setting again. Usually time for function entry or calling interrupt service is sufficient already. However it is worth to check minimum cycles between the divider changes of CKFCR_PC2D or PLLCR_PC3D, especially if low speed is used for CLKS2. If these minimum clock cycles can not be ensured otherwise, execute 3 dummy accesses to peripherals (read or write) before updating the clock divider again. The peripheral group 2 (CAN) or peripheral group 3 (USB) needs to be accessed, according to the clock divider to be changed. Synchronization time for the peripheral access consists of 2 clock cycles CLKB plus 2 clock cycles CLKP2 or CLKP3 in best case (synchronous mode). CLKP2 and CLKP3 are derived (divided) clocks of CLKS2.

(2) Do not change the Main clock or Sub clock stabilization time more than one times. Otherwise the relaxation time needs to be ensured (6 * 64 cycles of CLKMC or CLKSC + 6 cycles CLKS1). Usually it should not be required to change this setting multiple times.

5. Fujitsu countermeasure This phenomenon is fixed on future devices (since MB96F338 and MB96F379).

The fixed devices have no such functional limitation.


FLASH Reset




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Revision History

Version Date Remark 1 2007-11-14 Initial version (Uwe Moslehner) 2 2007-11-15 Description updated (Carsten Schonlau) 3 2007-12-06 Description updated, list of affected devices updated (mfr) 4 2008-01-10 Flash Memory Control Status registers renamed from

MFMCS/SFMCS to MCSRA/MCSRB. Effect of limitation for Flash A and Flash B described (Carsten Schonlau)


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1. Description of functional limitation If a Software Reset, a Watchdog Reset or a Clock Stop Reset is asserted while the Flash memory is being programmed or erased, invalid data may be read subsequently.

2. List of affected Devices MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA, MB96F346ASA, MB96F346ASB, MB96F346AWA, MB96F346AWB, MB96F346RSA, MB96F346RSB, MB96F346RWA, MB96F346RWB, MB96F346YSA, MB96F346YSB, MB96F346YWA, MB96F346YWB, MB96F347ASA, MB96F347ASB, MB96F347AWA, MB96F347AWB, MB96F347RSA, MB96F347RSB, MB96F347RWA, MB96F347RWB, MB96F347YSA, MB96F347YSB, MB96F347YWA, MB96F347YWB, MB96F348ASA, MB96F348ASB, MB96F348AWA, MB96F348AWB, MB96F348CSA, MB96F348CSB, MB96F348CSC, MB96F348CWA, MB96F348CWB, MB96F348CWC, MB96F348HSA, MB96F348HSB, MB96F348HSC, MB96F348HWA, MB96F348HWB, MB96F348HWC, MB96F348RSA, MB96F348RSB, MB96F348RWA, MB96F348RWB, MB96F348TSA, MB96F348TSB, MB96F348TSC, MB96F348TWA, MB96F348TWB, MB96F348TWC, MB96F348YSA, MB96F348YSB, MB96F348YWA, MB96F348YWB, MB96F356ASA, MB96F356AWA, MB96F356RSA, MB96F356RWA, MB96F356YSA, MB96F356YWA, MB96F386RSA, MB96F386RSB, MB96F386RWA, MB96F386RWB, MB96F386YSA, MB96F386YSB, MB96F386YWA, MB96F386YWB, MB96F387RSA, MB96F387RSB, MB96F387RWA, MB96F387RWB, MB96F387YSA, MB96F387YSB, MB96F387YWA, MB96F387YWB, MB96F903HSB, MB96F903HSC, MB96F905HSB, MB96F905HSC, MB96F906HSB, MB96F906HSC

3. Detailed explanation After submitting a Flash write or erase command, the Flash memory executes the automatic algorithm. In this state, a read access to the Flash memory returns the status of the hardware sequence flags instead of the Flash data (“BUSY state”). After completion of the automatic algorithm, the Flash memory automatically changes back into the “READ” state.

In case of an abnormal operation (for example when trying to program a bit from ‘0’ to ‘1’), the Flash memory enters the “TIMEOUT” state where also hardware sequence flags are output instead of Flash data. Return from “TIMEOUT” state to the “READ” state is possible by submitting the “Read/Reset” command

Executing a Power reset (Power-on or Low voltage) or an External reset initializes the Flash memory state machine from any state back to the “READ” state.

However the Flash memory is not initialized in case of a Software Reset, Watchdog Reset or Clock Stop Reset. This means the Flash memory continues to output the hardware sequence flags when being read. After reset release, the CPU reads the ROM configuration blocks of the Flash A (and Flash B for products supporting Flash B), leading to the following situation:

• Application crash if Flash A outputs the hardware sequence flags while the CPU reads the reset vector.

• Automatic setting of the Flash write protection registers does not work in case this feature is used. This is relevant only for products supporting Flash B).


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4. Possible workaround For Flash memory A: No Software, Watchdog or Clock Stop reset must be asserted when the Flash memory A is in the “BUSY” or “TIMEOUT” state (MCSRA:RDY=’0’).

• Do not assert a software reset as long as the MCSRA:RDY bit is ‘0’.

• Make sure the Watchdog timer is cleared on time when the MCSRA:RDY bit is ‘0’.

• Do not activate the Clock Stop reset function when programming the Flash memory A.

For Flash memory B: Do not use the automatic setting of the Flash write protection for this Flash.

Otherwise, the same restrictions as for Flash memory A apply (No Software, Watchdog or Clock Stop reset must be asserted when the Flash memory B is in the “BUSY” or “TIMEOUT” state (MCSRB:RDY=’0’)).

The TIMEOUT state should be left by submitting the “read/reset” command as soon as this state is indicated by the hardware sequence flags.

5. Fujitsu countermeasure The Flash state machine is initialized by any reset, including Software, Watchdog and Clock Stop reset.

Future MCUs will not have this limitation.


Watchdog intervals and delay on the watchdog reset assertion




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Revision History

Version Date Remark 1 2007-11-14 Initial version (Maria Constans) 2 2007-11-15 Interval change added, description updated (Carsten Schonlau)


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1. Description of functional limitation a) The specification of the watchdog intervals in the preliminary hardware manual (up to

revision “MB96300_HWM_rev13_20070827”) was wrong.

b) If the watchdog is not cleared within the specified interval time, then the watchdog reset assertion will not be immediate (maximum delay is one interval time).

2. List of affected Devices MB96F326ASA, MB96F326AWA, MB96F326RSA, MB96F326RWA, MB96F326YSA, MB96F326YWA, MB96F346ASA, MB96F346AWA, MB96F346RSA, MB96F346RWA, MB96F346YSA, MB96F346YWA, MB96F347ASA, MB96F347AWA, MB96F347RSA, MB96F347RWA, MB96F347YSA, MB96F347YWA, MB96F348ASA, MB96F348AWA, MB96F348CSA, MB96F348CSC, MB96F348CWB, MB96F348HSA, MB96F348HSC, MB96F348HWB, MB96F348RSA, MB96F348RWA, MB96F348TSA, MB96F348TSC, MB96F348TWB, MB96F348YSA, MB96F348YWA, MB96F356ASA, MB96F356RSA, MB96F356YSA, MB96F386RSA, MB96F386RWA, MB96F386YSA, MB96F386YWA, MB96F387RSA, MB96F387RWA, MB96F387YSA, MB96F387YWA, MB96F903HSB, MB96F905HSB, MB96F906HSB, MB96V300BRB-ES, MB96V300RB-ES

The corrected specification of the watchdog intervals in the hardware manual is valid for ALL 16FX devices.


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3. Detailed explanation a) The specification of the watchdog interval times in the hardware manual is corrected.

The effective watchdog interval times are half as long as previously specified:

Figure 12.2-2 Configuration of the Watchdog Timer Configuration Register (WDTC)

Old specification Corrected specification

WTI3 WTI2 WTI1 WTI0 Watchdog Timer Interval selection

bits (CLKWT is clock selected by

WTCS[1:0] bits)

Watchdog Timer Interval selection bits

(CLKWT is clock selected by WTCS[1:0] bits)

0 0 0 0 29 / CLKWT 28 / CLKWT 0 0 0 1 210 / CLKWT 29 / CLKWT 0 0 1 0 211 / CLKWT 210 / CLKWT 0 0 1 1 212 / CLKWT 211 / CLKWT 0 1 0 0 213 / CLKWT 212 / CLKWT 0 1 0 1 214 / CLKWT 213 / CLKWT 0 1 1 0 215 / CLKWT 214 / CLKWT 0 1 1 1 216 / CLKWT 215 / CLKWT 1 0 0 0 217 / CLKWT 216 / CLKWT 1 0 0 1 218 / CLKWT 217 / CLKWT 1 0 1 0 219 / CLKWT 218 / CLKWT 1 0 1 1 220 / CLKWT 219 / CLKWT 1 1 0 0 221 / CLKWT 220 / CLKWT 1 1 0 1 222 / CLKWT 221 / CLKWT 1 1 1 0 223 / CLKWT 22

16-bit microcontroller mb96300 series - fujitsu...file: designdifferences16fx.doc...

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