16f1847

2011 Microchip Technology Inc. Preliminary DS41453B

PIC16(L)F1847Data Sheet

18/20/28-Pin Flash Microcontrollerswith nanoWatt XLP Technology

DS41453B-page 2 Preliminary 2011 Microchip Technology Inc.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-182-7

Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

2011 Microchip Technology Inc. Preliminary DS41453B-page 3

High-Performance RISC CPU: C Compiler Optimized Architecture 256 bytes Data EEPROM Up to 14 Kbytes Linear Program Memory

Addressing Up to 1024 bytes Linear Data Memory Addressing Interrupt Capability with Automatic Context Saving 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)- FSRs can read program and data memory

Flexible Oscillator Structure: Precision 32 MHz Internal Oscillator Block:

- Factory calibrated to 1%, typical- Software selectable frequencies range of

31 kHz to 32 MHz 31 kHz Low-Power Internal Oscillator Four Crystal modes up to 32 MHz Three External Clock modes up to 32 MHz 4X Phase Lock Loop (PLL) Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Two-Speed Oscillator Start-up Reference Clock Module:

- Programmable clock output frequency and duty-cycle

Special Microcontroller Features: 1.8V-5.5V Operation PIC16F1847 1.8V-3.6V Operation PIC16LF1847 Self-Programmable under Software Control Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT):

- Programmable period from 1ms to 268s Programmable Code Protection In-Circuit Serial Programming (ICSP) via

two pins In-Circuit Debug (ICD) via two pins Enhance Low-Voltage Programming Power-Saving Sleep mode

Extreme Low-Power Management PIC16LF1847 with nanoWatt XLP: Operating Current: 34 A/MHz Sleep mode: 30 nA Watchdog Timer: 500 nA Timer1 Oscillator: 600 nA @ 32 kHz

Analog Features: Analog-to-Digital Converter (ADC) module:

- 10-bit resolution, 12 channels- Auto acquisition capability- Conversion available during Sleep

Analog Comparator module:- Two rail-to-rail analog comparators- Power mode control- Software controllable hysteresis

Voltage Reference module:- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

Peripheral Highlights: 15 I/O Pins and 1 Input Only Pin:

- High current sink/source 25 mA/25 mA- Programmable weak pull-ups- Programmable interrupt-on-change pins

Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler Enhanced Timer1:

- 16-bit timer/counter with prescaler- External Gate Input mode- Dedicated, low-power 32 kHz oscillator driver

Up to three Timer2-types: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler

Up to two Capture, Compare, PWM (CCP) modules Up to two Enhanced CCP (ECCP) modules:

- Software selectable time bases- Auto-shutdown and auto-restart- PWM steering

Up to two Master Synchronous Serial Port (MSSP) with SPI and I2CTM with:- 7-bit address masking- SMBus/PMBusTM compatibility

Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module

PIC16(L)F184718/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

PIC16(L)F1847


mTouch Sensing Oscillator module:- Up to 12 input channels

Data Signal Modulator module:- Selectable modulator and carrier sources

SR Latch:- Multiple Set/Reset input options- Emulates 555 Timer applications

PIC16(L)F1847 Family Types

Dev

ice

Program Memory Data Memory

I/Os

(1)

10-b

it A

DC

(ch)

Cap

Sens

e (c

h)

Com

para

tors

Tim

ers

(8/1

6-bi

t)

EUSA

RT

MSS

P

ECC

P (F

ull-B

ridge

)

ECC

P (H

alf-B

ridge

)

CC

P

SR L

atch

Wor

ds

SRA

M(b

ytes

)

Dat

a EE

PRO

M(b

ytes

)

PIC16LF1847 8K 1024 256 16 12 12 2 4/1 1 2 1 1 2 YesPIC16F1847 8K 1024 256 16 12 12 2 4/1 1 2 1 1 2 YesNote 1: One pin is input only.

2011 M

icrochip Technology Inc.Prelim

inaryD

S41453B

-page 5

PIC16(L)F1847

Pin Diagram 18-Pin PDIP, SOIC (PIC16(L)F1847)

Pin Diagram 20-Pin SSOP (PIC16(L)F1847)

PDIP, SOIC

P

I

C

1

6

(

L

)

F

1

8

4

7

1

234

18171615

56

7

141312

RA2/AN2/C12IN2-/C12IN+/VREF-/DACOUTRA3/AN3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3/SRQ

RA4/AN4/C2OUT/T0CKI/CCP4/SRNQRA5/MCLR/VPP/SS1(1,2)

VSS

RB0/T1G/CCP1(1)/P1A(1)/INT/SRI/FLT0

RB1/AN11/RX(1,2)/DT(1,2)/SDA1/SDI1

RA1/AN1/C12IN1-/SS2RA0/AN0/C12IN0-/SDO2

RA7/OSC1/CLKIN/P1C(1)/CCP2(1)/P2A(1)

RA6/OSC2/CLKOUT/CLKR/P1D(1)/P2B(1)/SDO1(1)

VDDRB7/AN6/T1OSCO/P1D(1,2)/P2B(1,2)/MDCIN1/ICSPDATRB6/AN5/T1CKI/T1OSCI/P1C(1,2)/CCP2(1,2)/P2A(1,2)/ICSPCLK

89

1110

RB2/AN10/MDMIN/TX(1,2)/CK(1,2)/RX(1)/DT(1)/SDA2/SDI2/SDO1(1,2)

RB3/AN9/MDOUT/CCP1(1,2)/P1A(1,2)RB5/AN7/P1B/TX(1)/CK(1)/SCL2/SCK2/SS1(1,2)

RB4/AN8/SCL1/SCK1/MDCIN2

Note 1: Pin function is remappable via APFCON register.2: Default function location.

SSOP

Note 1: Pin function is remappable via APFCON register.2: Default function location.

P

I

C

1

6

(

L

)

F

1

8

4

7

1

234

20191817

5

7

8

16

1413

RA2/AN2/C12IN2-/C12IN+/VREF-/DACOUTRA3/AN3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3/SRQ

RA4/AN4/C2OUT/TOCKI/CCP4/SRNQRA5/MCLR/VPP/SS1(1,2)

VSS


RB1/AN11/RX(1,2)/DT(1,2)/SDA1/SDI1

RA1/AN1/C12IN1-/SS2RA0/AN0/C12IN0-/SDO2



VDD

RB7/AN6/T1OSCO/P1D(1,2)/P2B(1,2)/MDCIN1/ICSPDATRB6/AN5/T1CKI/T1OSCI/P1C(1,2)/CCP2(1,2)/P2A(1,2)/ICSPCLK

910

1211

RB2/AN10/MDMIN/TX(1,2)/CK(1,2)/RX(1)/DT(1)/SDA2/SDI2/SDO1(1,2)

RB3/AN9/MDOUT/CCP1(1,2)/P1A(1,2)RB5/AN7/P1B/TX(1)/CK(1)/SCL2/SCK2/SS1(1,2)

RB4/AN8/SCL1/SCK1/MDCIN2

6 15VSS VDD

PIC16(L)F1847


Pin Diagram 28-Pin QFN/UQFN (PIC16(L)F1847)

Note 1: Pin function is remappable via APFCON register.

PIC16(L)F1847

RA

2/AN

2/C

12IN

2-/C

12IN

+/VR

EF-

/DA

CO

UT

RA3

/AN

3/C

12IN

3-/C

1IN

+/V R

EF+

/C1O

UT/

CC

P3/

SRQ

RA

4/A

N4/

C2O

UT/

TOC

KI/C

CP

4/SR

NQ

RA5/ MCLR/VPP/SS1(1)

VSS


RB

1/A

N11

/RX

(1) /D

T(1)

/SD

A1/

SD

I1

RA

1/A

N1/

C12

IN1-

/SS2

RA

0/A

N0/

C12

IN0-

/SD

O2



VDD

RB7/AN6/T1OSCO/P1D(1)/P2B(1)/MDCIN1/ICSPDATRB6/AN5/T1CKI/T1OSCI/P1C(1)/CCP2(1)/P2A(1)/ICSPCLK

RB

2/A

N10

/MD

MIN

/TX

(1) /C

K(1

) /RX

(1) /D

T(1)

/SD

A2/

SD

I2/S

DO

1(1)

RB

3/A

N9/

MD

OU

T/C

CP1

(1) /P

1A(1

)

RB

5/A

N7/

P1B

/TX

(1) /C

K(1

) /SC

L2/S

CK

2/S

S1(

1)R

B4/

AN

8/S

CL1

/SC

K1/

MD

CIN

2

VSS VDD

NC

NC

28 27 26 25 24 231234567 8 9 10 11

2221201918171615

141312N

C NC

NC

NC

NC

NC

QFN

2011 M


inaryD

S41453B

-page 7

PIC16(L)F1847

TABLE 1: 18/20/28-PIN SUMMARY (PIC16(L)F1847)I

/

O

1

8

-

P

i

n

P

D

I

P

/

S

O

I

C

2

0

-

P

i

n

S

S

O

P

2

8

-

P

i

n

Q

F

N

A

N

S

E

L

A

/

D

R

e

f

e

r

e

n

c

e

C

a

p

S

e

n

s

e

C

o

m

p

a

r

a

t

o

r

S

R

L

a

t

c

h

T

i

m

e

r

s

C

C

P

E

U

S

A

R

T

M

S

S

P

I

n

t

e

r

r

u

p

t

M

o

d

u

l

a

t

o

r

P

u

l

l

-

u

p

B

a

s

i

c

RA0 17 19 23 Y AN0 CPS0 C12IN0- SDO2 N

RA1 18 20 24 Y AN1 CPS1 C12IN1- SS2 N

RA2 1 1 26 Y AN2 VREF-DACOUT

CPS2 C12IN2-C12IN+

N

RA3 2 2 27 Y AN3 VREF+ CPS3 C12IN3-C1IN+C1OUT

SRQ CCP3 N

RA4 3 3 28 Y AN4 CPS4 C2OUT SRNQ T0CKI CCP4 N RA5 4 4 1 N SS1(1) Y(2) MCLR

VPP

RA6 15 17 20 N P1D(1)P2B(1)

SDO1(1) N OSC2, CLKOUTCLKR

RA7 16 18 21 N P1C(1)CCP2(1)P2A(1)

N OSC1, CLKIN

RB0 6 7 7 N SRI T1G CCP1(1)P1A(1)FLT0

INTIOC

Y

RB1 7 8 8 Y AN11 CPS11 RX(1,3)DT(1,3)

SDA1SDI1

IOC Y

RB2 8 9 9 Y AN10 CPS10 RX(1)DT(1)

TX(1,3)CK(1,3)

SDA2, SDI2SDO1(1,3)

IOC MDMIN Y

RB3 9 10 10 Y AN9 CPS9 CCP1(1,3)P1A(1,3)

IOC MDOUT Y

RB4 10 11 12 Y AN8 CPS8 SCL1,SCK1 IOC MDCIN2 Y

RB5 11 12 13 Y AN7 CPS7 P1B TX(1)CK(1)

SCL2, SCK2SS1(1,3)

IOC Y

RB6 12 13 15 Y AN5 CPS5 T1CKIT1OSCI

P1C(1,3)CCP2(1,3)P2A(1,3)

IOC Y ICSPCLK/ICDCLK

RB7 13 14 16 Y AN6 CPS6 T1OSCO P1D(1,3)P2B(1,3)

IOC MDCIN1 Y ICSPDAT/ICDDAT

VDD 14 15,16 17,19 VDD

Vss 5 5,6 3,5 VSS

Note 1: Pin functions can be moved using the APFCON register(s).2: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 3: Default function location.

PIC16(L)F1847


Table of Contents1.0 Device Overview ........................................................................................................................................................................ 112.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 173.0 Memory Organization ................................................................................................................................................................. 194.0 Device Configuration .................................................................................................................................................................. 475.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 536.0 Reference Clock Module ............................................................................................................................................................ 717.0 Resets ........................................................................................................................................................................................ 758.0 Interrupts .................................................................................................................................................................................... 839.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 9910.0 Watchdog Timer (WDT) ........................................................................................................................................................... 10111.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 10512.0 I/O Ports ................................................................................................................................................................................... 11913.0 Interrupt-on-Change ................................................................................................................................................................. 13114.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 13515.0 Temperature Indicator Module ................................................................................................................................................. 13716.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 13917.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 15318.0 SR Latch................................................................................................................................................................................... 15919.0 Comparator Module.................................................................................................................................................................. 16520.0 Timer0 Module ......................................................................................................................................................................... 17521.0 Timer1 Module ......................................................................................................................................................................... 17922.0 Timer2/4/6 Modules.................................................................................................................................................................. 19123.0 Data Signal Modulator (DSM) .................................................................................................................................................. 19524.0 Capture/Compare/PWM (ECCP1, ECCP2, CCP3, CCP4) Modules ........................................................................................ 20525.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 23326.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 28927.0 Capacitive Sensing Module...................................................................................................................................................... 31928.0 In-Circuit Serial Programming (ICSP) ................................................................................................................................ 32929.0 Instruction Set Summary .......................................................................................................................................................... 33330.0 Electrical Specifications............................................................................................................................................................ 34731.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 37932.0 Development Support............................................................................................................................................................... 38133.0 Packaging Information.............................................................................................................................................................. 385Appendix A: Revision History............................................................................................................................................................. 397Appendix B: Device Differences......................................................................................................................................................... 397Index .................................................................................................................................................................................................. 399The Microchip Web Site ..................................................................................................................................................................... 407Customer Change Notification Service .............................................................................................................................................. 407Customer Support .............................................................................................................................................................................. 407Reader Response .............................................................................................................................................................................. 408Product Identification System............................................................................................................................................................. 409


PIC16(L)F1847

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following: Microchips Worldwide Web site; http://www.microchip.com Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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PIC16(L)F1847


NOTES:


PIC16(L)F1847

1.0 DEVICE OVERVIEWThe PIC16F/LF1847 are described within this datasheet. They are available in 18/20/28-pin packages.Figure 1-1 shows a block diagram of thePIC16F/LF1847 devices. Table 1-2 shows the pinoutdescriptions.

Reference Table 1-1 for peripherals available perdevice.

TABLE 1-1: DEVICE PERIPHERAL SUMMARY

Peripheral

PIC

16F/

LF18

47ADC Capacitive Sensing Module Digital-to-Analog Converter (DAC) Digital Signal Modulator (DSM) EUSART Fixed Voltage Reference (FVR) Reference Clock Module SR Latch Capture/Compare/PWM Modules

ECCP1 ECCP2

CCP3 CCP4

ComparatorsC1 C2

Master Synchronous Serial PortsMSSP1 MSSP2

TimersTimer0 Timer1 Timer2 Timer4 Timer6

PIC16(L)F1847


FIGURE 1-1: PIC16F/LF1847 BLOCK DIAGRAM

PORTA

EUSART

Comparators

MSSPx

Timer2-Timer1Timer0

ECCPx

ADC10-Bit

CCPx

PORTB

SRLatch

Note 1: See applicable chapters for more information on peripherals.2: See Table 1-1 for peripherals available on specific devices.

CPU

ProgramFlash Memory

EEPROMRAM

OSC1/CLKINOSC2/CLKOUT Timing

Generation

INTRCOscillator

MCLR

(Figure 2-1)

Modulator CapSense

ClockCLKR

Reference

Types DAC

FVR


PIC16(L)F1847

TABLE 1-2: PIC16F/LF1847 PINOUT DESCRIPTION

Name Function Input TypeOutput Type Description

RA0/AN0/CPS0/C12IN0-/SDO2

RA0 TTL CMOS General purpose I/O.AN0 AN A/D Channel 0 input.

CPS0 AN Capacitive sensing input 0.C12IN0- AN Comparator C1 or C2 negative input.SDO2 CMOS SPI data output.

RA1/AN1/CPS1/C12IN1-/SS2 RA1 TTL CMOS General purpose I/O.AN1 AN A/D Channel 1 input.

CPS1 AN Capacitive sensing input 1.C12IN1- AN Comparator C1 or C2 negative input.

SS2 ST Slave Select input 2.RA2/AN2/CPS2/C12IN2-/C12IN+/VREF-/DACOUT


CPS2 AN Capacitive sensing input 2.C12IN2- AN Comparator C1 or C2 negative input.C12IN+ AN Comparator C1 or C2 positive input.VREF- AN A/D Negative Voltage Reference input.

DACOUT AN Voltage Reference output.RA3/AN3/CPS3/C12IN3-/C1IN+/VREF+/C1OUT/CCP3/SRQ


CPS3 AN Capacitive sensing input 3.C12IN3- AN Comparator C1 or C2 negative input.C1IN+ AN Comparator C1 positive input.VREF+ AN A/D Voltage Reference input.

C1OUT CMOS Comparator C1 output.CCP3 ST CMOS Capture/Compare/PWM3.SRQ CMOS SR latch non-inverting output.

RA4/AN4/CPS4/C2OUT/T0CKI/CCP4/SRNQ


CPS4 AN Capacitive sensing input 4.C2OUT CMOS Comparator C2 output.T0CKI ST Timer0 clock input.CCP4 ST CMOS Capture/Compare/PWM4.SRNQ CMOS SR latch inverting output.

RA5/MCLR/VPP/SS1 RA5 TTL CMOS General purpose I/O.MCLR ST Master Clear with internal pull-up.

VPP HV Programming voltage.SS1 ST Slave Select input 1.

Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open DrainTTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels

Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register.2: Default function location.

PIC16(L)F1847



RA6 TTL CMOS General purpose I/O.OSC2 XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT CMOS FOSC/4 output.CLKR CMOS Clock Reference Output.P1D CMOS PWM output.P2B CMOS PWM output.

SDO1 CMOS SPI data output 1.RA7/OSC1/CLKIN/P1C(1)/CCP2(1)/P2A(1)

RA7 TTL CMOS General purpose I/O.OSC1 XTAL Crystal/Resonator (LP, XT, HS modes).CLKIN CMOS External clock input (EC mode).P1C CMOS PWM output.

CCP2 ST CMOS Capture/Compare/PWM2.P2A CMOS PWM output.


RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.

T1G ST Timer1 Gate input.CCP1 ST CMOS Capture/Compare/PWM1.P1A CMOS PWM output.INT ST External interrupt.SRI ST SR latch input.

FLT0 ST ECCP Auto-Shutdown Fault input.RB1/AN11/CPS11/RX(1,2)/DT(1,2)/SDA1/SDI1


AN11 AN A/D Channel 11 input.CPS11 AN Capacitive sensing input 11.

RX ST USART asynchronous input.DT ST CMOS USART synchronous data.

SDA1 I2C OD I2C data input/output 1.SDI1 CMOS SPI data input 1.

RB2/AN10/CPS10/MDMIN/TX(1,2)/CK(1,2)/RX(1)/DT(1)/SDA2/SDI2/SDO1(1,2)


AN10 AN A/D Channel 10 input.CPS10 AN Capacitive sensing input 10.MDMIN CMOS Modulator source input.

TX CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.RX ST USART asynchronous input.DT ST CMOS USART synchronous data.

SDA2 I2C OD I2C data input/output 2.SDI2 ST SPI data input 2.SDO1 CMOS SPI data output 1.

TABLE 1-2: PIC16F/LF1847 PINOUT DESCRIPTION (CONTINUED)





PIC16(L)F1847

RB3/AN9/CPS9/MDOUT/CCP1(1,2)/P1A(1,2)



MDOUT CMOS Modulator output.CCP1 ST CMOS Capture/Compare/PWM1.P1A CMOS PWM output.

RB4/AN8/CPS8/SCL1/SCK1/MDCIN2


AN8 AN A/D Channel 8 input.CPS8 AN Capacitive sensing input 8.SCL1 I2C OD I2C clock 1.SCK1 ST CMOS SPI clock 1.

MDCIN2 ST Modulator Carrier Input 2.RB5/AN7/CPS7/P1B/TX(1)/CK(1)/SCL2/SCK2/SS1(1,2)


AN7 AN A/D Channel 7 input.CPS7 AN Capacitive sensing input 7.P1B CMOS PWM output.TX CMOS USART asynchronous transmit.CK ST CMOS USART synchronous clock.

SCL2 I2C OD I2C clock 2.SCK2 ST CMOS SPI clock 2.SS1 ST Slave Select input 1.

RB6/AN5/CPS5/T1CKI/T1OSI/P1C(1,2)/CCP2(1,2)/P2A(1,2)/ICSPCLK


AN5 AN A/D Channel 5 input.CPS5 AN Capacitive sensing input 5.T1CKI ST Timer1 clock input.T1OSO XTAL XTAL Timer1 oscillator connection.

P1C CMOS PWM output.CCP2 ST CMOS Capture/Compare/PWM2.P2A CMOS PWM output.

ICSPCLK ST Serial Programming Clock.RB7/AN6/CPS6/T1OSO/P1D(1,2)/P2B(1,2)/MDCIN1/ICSPDAT



T1OSO XTAL XTAL Timer1 oscillator connection.P1D CMOS PWM output.P2B CMOS PWM output.

MDCIN1 ST Modulator Carrier Input 1.ICSPDAT ST CMOS ICSP Data I/O.

VDD VDD Power Positive supply.





PIC16(L)F1847


VSS VSS Power Ground reference.






PIC16(L)F1847

2.0 ENHANCED MID-RANGE CPUThis family of devices contain an enhanced mid-range8-bit CPU core. The CPU has 49 instructions. Interruptcapability includes automatic context saving. Thehardware stack is 16 levels deep and has Overflow andUnderflow Reset capability. Direct, indirect, and relativeaddressing modes are available. Two File SelectRegisters (FSRs) provide the ability to read programand data memory.

Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set

2.1 Automatic Interrupt Context Saving

During interrupts, certain registers are automaticallysaved in shadow registers and restored when returningfrom the interrupt. This saves stack space and usercode. See Section 8.5 Automatic Context Saving,for more information.

2.2 16-level Stack with Overflow and Underflow

These devices have an external stack memory 15 bitswide and 16 words deep. A Stack Overflow or Under-flow will set the appropriate bit (STKOVF or STKUNF)in the PCON register, and if enabled will cause a soft-ware Reset. See section Section 3.4 Stack for moredetails.

2.3 File Select RegistersThere are two 16-bit File Select Registers (FSR). FSRscan access all file registers and program memory,which allows one Data Pointer for all memory. When anFSR points to program memory, there is 1 additionalinstruction cycle in instructions using INDF to allow thedata to be fetched. General purpose memory can nowalso be addressed linearly, providing the ability toaccess contiguous data larger than 80 bytes. There arealso new instructions to support the FSRs. SeeSection 3.4 Stackfor more details.

2.4 Instruction SetThere are 49 instructions for the enhanced mid-rangeCPU to support the features of the CPU. SeeSection 29.0 Instruction Set Summary for moredetails.

PIC16(L)F1847


FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

12

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

InstructionDecode &

Control

TimingGeneration

OSC1/CLKIN

OSC2/CLKOUT

VDD

8

8

Brown-outReset

12

3

VSS

InternalOscillator

Block

ConfigurationData Bus 8

14ProgramBus

Instruction reg

Program Counter

8 Level Stack(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

InstructionDecode &

Control

TimingGeneration

VDD

8

8

3

VSS

InternalOscillator

Block

Configuration15 Data Bus 8

14ProgramBus

Instruction Reg

Program Counter

16-Level Stack(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

IndirectAddr

FSR0 Reg

STATUS Reg

MUX

ALUInstruction

Decode andControl

TimingGeneration

VDD

8

8

3

VSS

InternalOscillator

Block

Configuration

FlashProgramMemory

RAM

FSR regFSR regFSR1 Reg15

15

MU

X15

Program MemoryRead (PMR)

12

FSR regFSR regBSR Reg

5


PIC16(L)F1847

3.0 MEMORY ORGANIZATIONThere are three types of memory in PIC16(L)F1847:Data Memory, Program Memory and Data EEPROMMemory(1).

Program Memory Data Memory

- Core Registers- Special Function Registers- General Purpose RAM- Common RAM- Device Memory Maps- Special Function Registers Summary

Data EEPROM memory(1)

The following features are associated with access andcontrol of program memory and data memory:

PCL and PCLATH Stack Indirect Addressing

3.1 Program Memory OrganizationThe enhanced mid-range core has a 15-bit programcounter capable of addressing a 32K x 14 programmemory space. Table 3-1 shows the memory sizesimplemented for the PIC16F/LF1847 family. Accessing alocation above these boundaries will cause awrap-around within the implemented memory space.The Reset vector is at 0000h and the interrupt vector isat 0004h (see Figure 3-1).

Note 1: The Data EEPROM Memory and themethod to access Flash memory throughthe EECON registers is described inSection 11.0 Data EEPROM and FlashProgram Memory Control.

TABLE 3-1: DEVICE SIZES AND ADDRESSESDevice Program Memory Space (Words) Last Program Memory Address

PIC16(L)F1847 8,192 1FFFh

PIC16(L)F1847


FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1847

3.1.1 READING PROGRAM MEMORY AS DATA

There are two methods of accessing constants in pro-gram memory. The first method is to use tables ofRETLW instructions. The second method is to set anFSR to point to the program memory.

3.1.1.1 RETLW InstructionThe RETLW instruction can be used to provide accessto tables of constants. The recommended way to createsuch a table is shown in Example 3-1.

EXAMPLE 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-ple to implement. If your code must remain portablewith previous generations of microcontrollers, then theBRW instruction is not available so the older table readmethod must be used.

3.1.1.2 Indirect Read with FSRThe program memory can be accessed as data by set-ting bit 7 of the FSRxH register and reading the match-ing INDFx register. The MOVIW instruction will place thelower 8 bits of the addressed word in the W register.Writes to the program memory cannot be performed viathe INDF registers. Instructions that access the pro-gram memory via the FSR require one extra instructioncycle to complete. Example 3-2 demonstrates access-ing the program memory via an FSR.

The HIGH directive will set bit if a label points to alocation in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR

PC

15

0000h

0004h0005h-07FFh

Stack (16 Levels)

Reset Vector

Interrupt Vector

CALL, RETURNRETFIE, RETLW

0800h-

Note 1: Reserved. Shadows to 0000h-1FFFh.

0FFFh1000h

Page 0

Page 1

1FFFh

17FFh1800h

2000h

7FFFh

Page 2

Page 3

Rollover Page 0(1)

Rollover Page 3(1)

constantsBRW ;Add Index in W to

;program counter to;select data

RETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW DATA_INDEXCALL constants; THE CONSTANT IS IN W

constantsRETLW DATA0 ;Index0 dataRETLW DATA1 ;Index1 dataRETLW DATA2RETLW DATA3

my_function; LOTS OF CODEMOVLW LOW constantsMOVWF FSR1LMOVLW HIGH constantsMOVWF FSR1HMOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W


PIC16(L)F18473.2 Data Memory OrganizationThe data memory is partitioned in 32 memory bankswith 128 bytes in a bank. Each bank consists of(Figure 3-2):

12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM

The active bank is selected by writing the bank numberinto the Bank Select Register (BSR). Unimplementedmemory will read as 0. All data memory can beaccessed either directly (via instructions that use thefile registers) or indirectly via the two File SelectRegisters (FSR). See Section 3.5 IndirectAddressing for more information.

3.2.1 CORE REGISTERSThe core registers contain the registers that directlyaffect the basic operation of the PIC16F/LF1847. Theseregisters are listed below:

INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON

3.2.1.1 STATUS RegisterThe STATUS register, shown in Register 3-1, contains:

the arithmetic status of the ALU the Reset status

The STATUS register can be the destination for anyinstruction, like any other register. If the STATUSregister is the destination for an instruction that affectsthe Z, DC or C bits, then the write to these three bits isdisabled. These bits are set or cleared according to thedevice logic. Furthermore, the TO and PD bits are notwritable. Therefore, the result of an instruction with theSTATUS register as destination may be different thanintended.

For example, CLRF STATUS will clear the upper threebits and set the Z bit. This leaves the STATUS registeras 000u u1uu (where u = unchanged).It is recommended, therefore, that only BCF, BSF,SWAPF and MOVWF instructions are used to alter theSTATUS register, because these instructions do notaffect any Status bits. For other instructions notaffecting any Status bits (Refer to Section 29.0Instruction Set Summary).

Note: The core registers are the first 12addresses of every data memory bank.

Note 1: The C and DC bits operate as Borrowand Digit Borrow out bits, respectively, insubtraction.

PIC16(L)F1847


REGISTER 3-1: STATUS: STATUS REGISTER

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

TO PD Z DC(1) C(1)

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets1 = Bit is set 0 = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as 0bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction0 = A WDT time-out occurred

bit 3 PD: Power-down bit1 = After power-up or by the CLRWDT instruction0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit1 = The result of an arithmetic or logic operation is zero0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit(1)

1 = A carry-out from the 4th low-order bit of the result occurred0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1)

1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register.


PIC16(L)F18473.2.2 SPECIAL FUNCTION REGISTERThe Special Function Registers are registers used bythe application to control the desired operation ofperipheral functions in the device. The registers asso-ciated with the operation of the peripherals aredescribed in the appropriate peripheral chapter of thisdata sheet.

3.2.3 GENERAL PURPOSE RAMThere are up to 80 bytes of GPR in each data memorybank.

3.2.3.1 Linear Access to GPRThe general purpose RAM can be accessed in anon-banked method via the FSRs. This can simplifyaccess to large memory structures. See Section 3.5.2Linear Data Memory for more information.

3.2.4 COMMON RAMThere are 16 bytes of common RAM accessible from allbanks.

FIGURE 3-2: BANKED MEMORY PARTITIONING

3.2.5 DEVICE MEMORY MAPSThe memory maps for the device family are as shownin Table 3-2.

0Bh0Ch

1Fh20h

6Fh70h

7Fh

00h

Common RAM(16 bytes)

General Purpose RAM(80 bytes maximum)

Core Registers(12 bytes)

Special Function Registers(20 bytes maximum)

Memory Region7-bit Bank Offset

TABLE 3-2: MEMORY MAP TABLESDevice Banks Table No.

PIC16F/LF1847 0-7 Table 3-38-15 Table 3-4

16-23 Table 3-524-31 Table 3-6

31 Table 3-7

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TABLE 3-3: PIC16F/LF1847 MEMORY MAP, BANKS 0-7

Legend: = Unimplemented data memory locations, read as 0.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch 30Ch 38Ch 00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh 30Dh 38Dh 00Eh 08Eh 10Eh 18Eh 20Eh 28Eh 30Eh 38Eh 00Fh 08Fh 10Fh 18Fh 20Fh 28Fh 30Fh 38Fh 010h 090h 110h 190h 210h 290h 310h 390h 011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSP1BUF 291h CCPR1L 311h CCPR3L 391h 012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSP1ADD 292h CCPR1H 312h CCPR3H 392h 013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSP1MSK 293h CCP1CON 313h CCP3CON 393h 014h PIR4 094h PIE4 114h CM2CON1 194h EEDATH 214h SSP1STAT 294h PWM1CON 314h 394h IOCBP015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h 395h IOCBN016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h 396h IOCBF017h TMR1H 097h WDTCON 117h FVRCON 197h 217h SSPCON3 297h 317h 397h 018h T1CON 098h OSCTUNE 118h DACCON0 198h 218h 298h CCPR2L 318h CCPR4L 398h 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h SSP2BUF 299h CCPR2H 319h CCPR4H 399h 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah SSP2ADD 29Ah CCP2CON 31Ah CCP4CON 39Ah CLKRCON01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh SSP2MSK 29Bh PWM2CON 31Bh 39Bh 01Ch T2CON 09Ch ADRESH 11Ch 19Ch SPBRGH 21Ch SSP2STAT 29Ch CCP2AS 31Ch 39Ch MDCON01Dh 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh SSP2CON 29Dh PSTR2CON 31Dh 39Dh MDSRC01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2 29Eh CCPTMRS 31Eh 39Eh MDCARL01Fh CPSCON1 09Fh 11Fh 19Fh BAUDCON 21Fh SSP2CON3 29Fh 31Fh 39Fh MDCARH020h

GeneralPurposeRegister96 Bytes

0A0h


120h


1A0h


220h


2A0h


320h


3A0h


06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh070h 0F0h

Accesses70h 7Fh

170hAccesses70h 7Fh

1F0hAccesses70h 7Fh

270hAccesses70h 7Fh

2F0hAccesses70h 7Fh

370hAccesses70h 7Fh

3F0hAccesses70h 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

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BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS404h FSR0L 484h FSR0L 504h FSR0L 584h FSR0L 604h FSR0L 684h FSR0L 704h FSR0L 784h FSR0L405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON40Ch 48Ch 50Ch 58Ch 60Ch 68Ch 70Ch 78Ch 40Dh 48Dh 50Dh 58Dh 60Dh 68Dh 70Dh 78Dh 40Eh 48Eh 50Eh 58Eh 60Eh 68Eh 70Eh 78Eh 40Fh 48Fh 50Fh 58Fh 60Fh 68Fh 70Fh 78Fh 410h 490h 510h 590h 610h 690h 710h 790h 411h 491h 511h 591h 611h 691h 711h 791h 412h 492h 512h 592h 612h 692h 712h 792h 413h 493h 513h 593h 613h 693h 713h 793h 414h 494h 514h 594h 614h 694h 714h 794h 415h TMR4 495h 515h 595h 615h 695h 715h 795h 416h PR4 496h 516h 596h 616h 696h 716h 796h 417h T4CON 497h 517h 597h 617h 697h 717h 797h 418h 498h 518h 598h 618h 698h 718h 798h 419h 499h 519h 599h 619h 699h 719h 799h 41Ah 49Ah 51Ah 59Ah 61Ah 69Ah 71Ah 79Ah 41Bh 49Bh 51Bh 59Bh 61Bh 69Bh 71Bh 79Bh 41Ch TMR6 49Ch 51Ch 59Ch 61Ch 69Ch 71Ch 79Ch 41Dh PR6 49Dh 51Dh 59Dh 61Dh 69Dh 71Dh 79Dh 41Eh T6CON 49Eh 51Eh 59Eh 61Eh 69Eh 71Eh 79Eh 41Fh 49Fh 51Fh 59Fh 61Fh 69Fh 71Fh 79Fh 420h


4A0hGeneralPurposeRegister80 Bytes

520hGeneralPurposeRegister80 Bytes

5A0hGeneralPurposeRegister80 Bytes

620h General Purpose Register 48 Bytes

6A0h

UnimplementedRead as 0

720h


7A0h



46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh470h

Accesses70h 7Fh

4F0h

Accesses70h 7Fh

570h

Accesses70h 7Fh

5F0h

Accesses70h 7Fh

670h

Accesses70h 7Fh

6F0h

Accesses70h 7Fh

770h

Accesses70h 7Fh

7F0h

Accesses70h 7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

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TABLE 3-5: PIC16F/LF1847 MEMORY MAP, BANKS 16-23BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23

800h INDF0 880h INDF0 900h INDF0 980h INDF0 A00h INDF0 A80h INDF0 B00h INDF0 B80h INDF0801h INDF1 881h INDF1 901h INDF1 981h INDF1 A01h INDF1 A81h INDF1 B01h INDF1 B81h INDF1802h PCL 882h PCL 902h PCL 982h PCL A02h PCL A82h PCL B02h PCL B82h PCL803h STATUS 883h STATUS 903h STATUS 983h STATUS A03h STATUS A83h STATUS B03h STATUS B83h STATUS804h FSR0L 884h FSR0L 904h FSR0L 984h FSR0L A04h FSR0L A84h FSR0L B04h FSR0L B84h FSR0L805h FSR0H 885h FSR0H 905h FSR0H 985h FSR0H A05h FSR0H A85h FSR0H B05h FSR0H B85h FSR0H806h FSR1L 886h FSR1L 906h FSR1L 986h FSR1L A06h FSR1L A86h FSR1L B06h FSR1L B86h FSR1L807h FSR1H 887h FSR1H 907h FSR1H 987h FSR1H A07h FSR1H A87h FSR1H B07h FSR1H B87h FSR1H808h BSR 888h BSR 908h BSR 988h BSR A08h BSR A88h BSR B08h BSR B88h BSR809h WREG 889h WREG 909h WREG 989h WREG A09h WREG A89h WREG B09h WREG B89h WREG80Ah PCLATH 88Ah PCLATH 90Ah PCLATH 98Ah PCLATH A0Ah PCLATH A8Ah PCLATH B0Ah PCLATH B8Ah PCLATH80Bh INTCON 88Bh INTCON 90Bh INTCON 98Bh INTCON A0Bh INTCON A8Bh INTCON B0Bh INTCON B8Bh INTCON80Ch 88Ch 90Ch 98Ch A0Ch A8Ch B0Ch B8Ch 80Dh 88Dh 90Dh 98Dh A0Dh A8Dh B0Dh B8Dh 80Eh 88Eh 90Eh 98Eh A0Eh A8Eh B0Eh B8Eh 80Fh 88Fh 90Fh 98Fh A0Fh A8Fh B0Fh B8Fh 810h 890h 910h 990h A10h A90h B10h B90h 811h 891h 911h 991h A11h A91h B11h B91h 812h 892h 912h 992h A12h A92h B12h B92h 813h 893h 913h 993h A13h A93h B13h B93h 814h 894h 914h 994h A14h A94h B14h B94h 815h 895h 915h 995h A15h A95h B15h B95h 816h 896h 916h 996h A16h A96h B16h B96h 817h 897h 917h 997h A17h A97h B17h B97h 818h 898h 918h 998h A18h A98h B18h B98h 819h 899h 919h 999h A19h A99h B19h B99h 81Ah 89Ah 91Ah 99Ah A1Ah A9Ah B1Ah B9Ah 81Bh 89Bh 91Bh 99Bh A1Bh A9Bh B1Bh B9Bh 81Ch 89Ch 91Ch 99Ch A1Ch A9Ch B1Ch B9Ch 81Dh 89Dh 91Dh 99Dh A1Dh A9Dh B1Dh B9Dh 81Eh 89Eh 91Eh 99Eh A1Eh A9Eh B1Eh B9Eh 81Fh 89Fh 91Fh 99Fh A1Fh A9Fh B1Fh B9Fh 820h


8A0h


920h


9A0h


A20h


AA0h


B20h


BA0h


86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh870h

Accesses70h 7Fh

8F0hAccesses70h 7Fh

970hAccesses70h 7Fh

9F0hAccesses70h 7Fh

A70hAccesses70h 7Fh

AF0hAccesses70h 7Fh

B70hAccesses70h 7Fh

BF0hAccesses70h 7Fh

87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh

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2011 M

icrochip Technology Inc.



BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31C00h INDF0 C80h INDF0 D00h INDF0 D80h INDF0 E00h INDF0 E80h INDF0 F00h INDF0 F80h INDF0C01h INDF1 C81h INDF1 D01h INDF1 D81h INDF1 E01h INDF1 E81h INDF1 F01h INDF1 F81h INDF1C02h PCL C82h PCL D02h PCL D82h PCL E02h PCL E82h PCL F02h PCL F82h PCLC03h STATUS C83h STATUS D03h STATUS D83h STATUS E03h STATUS E83h STATUS F03h STATUS F83h STATUSC04h FSR0L C84h FSR0L D04h FSR0L D84h FSR0L E04h FSR0L E84h FSR0L F04h FSR0L F84h FSR0LC05h FSR0H C85h FSR0H D05h FSR0H D85h FSR0H E05h FSR0H E85h FSR0H F05h FSR0H F85h FSR0HC06h FSR1L C86h FSR1L D06h FSR1L D86h FSR1L E06h FSR1L E86h FSR1L F06h FSR1L F86h FSR1LC07h FSR1H C87h FSR1H D07h FSR1H D87h FSR1H E07h FSR1H E87h FSR1H F07h FSR1H F87h FSR1HC08h BSR C88h BSR D08h BSR D88h BSR E08h BSR E88h BSR F08h BSR F88h BSRC09h WREG C89h WREG D09h WREG D89h WREG E09h WREG E89h WREG F09h WREG F89h WREGC0Ah PCLATH C8Ah PCLATH D0Ah PCLATH D8Ah PCLATH E0Ah PCLATH E8Ah PCLATH F0Ah PCLATH F8Ah PCLATHC0Bh INTCON C8Bh INTCON D0Bh INTCON D8Bh INTCON E0Bh INTCON E8Bh INTCON F0Bh INTCON F8Bh INTCONC0Ch C8Ch D0Ch D8Ch E0Ch E8Ch F0Ch F8Ch C0Dh C8Dh D0Dh D8Dh E0Dh E8Dh F0Dh F8Dh C0Eh C8Eh D0Eh D8Eh E0Eh E8Eh F0Eh F8Eh C0Fh C8Fh D0Fh D8Fh E0Fh E8Fh F0Fh F8Fh C10h C90h D10h D90h E10h E90h F10h F90h C11h C91h D11h D91h E11h E91h F11h F91h C12h C92h D12h D92h E12h E92h F12h F92h C13h C93h D13h D93h E13h E93h F13h F93h C14h C94h D14h D94h E14h E94h F14h F94h C15h C95h D15h D95h E15h E95h F15h F95h C16h C96h D16h D96h E16h E96h F16h F96h C17h C97h D17h D97h E17h E97h F17h F97h C18h C98h D18h D98h E18h E98h F18h F98h C19h C99h D19h D99h E19h E99h F19h F99h C1Ah C9Ah D1Ah D9Ah E1Ah E9Ah F1Ah F9Ah C1Bh C9Bh D1Bh D9Bh E1Bh E9Bh F1Bh F9Bh C1Ch C9Ch D1Ch D9Ch E1Ch E9Ch F1Ch F9Ch C1Dh C9Dh D1Dh D9Dh E1Dh E9Dh F1Dh F9Dh C1Eh C9Eh D1Eh D9Eh E1Eh E9Eh F1Eh F9Eh C1Fh C9Fh D1Fh D9Fh E1Fh E9Fh F1Fh F9Fh C20h


CA0h


D20h


DA0h


E20h


EA0h


F20h


FA0h

See Table 3-7 for more information

C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFhC70h

Accesses70h 7Fh

CF0hAccesses70h 7Fh

D70hAccesses70h 7Fh

DF0hAccesses70h 7Fh

E70hAccesses70h 7Fh

EF0hAccesses70h 7Fh

F70hAccesses70h 7Fh

FF0hAccesses70h 7Fh

CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh

PIC16(L)F1847


TABLE 3-7: PIC16F/LF1847 MEMORY MAP, BANK 31

3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY

The Special Function Register Summary for the devicefamily are as follows:


Bank 31FA0h

FE3h


FE4h STATUS_SHADFE5h WREG_SHADFE6h BSR_SHADFE7h PCLATH_SHADFE8h FSR0L_SHADFE9h FSR0H_SHADFEAh FSR1L_SHADFEBh FSR1H_SHADFECh FEDh STKPTRFEEh TOSLFEFh TOSH

Device Bank(s) Page No.

PIC16(L)F1847

0 291 302 313 324 335 346 357 368 37

9-30 3831 39


PIC16(L)F1847

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value onPOR, BORValue on all other Resets

Bank 0000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)xxxx xxxx xxxx xxxx

001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register)

xxxx xxxx xxxx xxxx

002h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000003h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000008h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000009h(1) WREG Working Register 0000 0000 uuuu uuuu00Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000000Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u00Ch PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx xxxx xxxx00Dh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx xxxx xxxx00Eh Unimplemented

00Fh Unimplemented

010h Unimplemented

011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000012h PIR2 OSFIF C2IF C1IF EEIF BCL1IF CCP2IF 0000 0--0 0000 0--0013h PIR3 CCP4IF CCP3IF TMR6IF TMR4IF --00 0-0- --00 0-0-014h PIR4 BCL2IF SSP2IF ---- --00 ---- --00015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu018h T1CON TMR1CS T1CKPS T1OSCEN T1SYNC TMR1ON 0000 00-0 uuuu uu-u019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONET1GVAL T1GSS 0000 0x00 uuuu uxuu

01Ah TMR2 Timer2 Module Register 0000 0000 0000 000001Bh PR2 Timer2 Period Register 1111 1111 1111 111101Ch T2CON T2OUTPS TMR2ON T2CKPS -000 0000 -000 000001Dh Unimplemented

01Eh CPSCON0 CPSON CPSRM CPSRNG CPSOUT T0XCS 00-- 0000 00-- 000001Fh CPSCON1 CPSCH ---- 0000 ---- 0000Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.

Shaded locations are unimplemented, read as 0.Note 1: These registers can be addressed from any bank.

PIC16(L)F1847





xxxx xxxx xxxx xxxx

082h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000083h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000088h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000089h(1) WREG Working Register 0000 0000 uuuu uuuu08Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000008Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u08Ch TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 111108Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 111108Eh Unimplemented

08Fh Unimplemented

090h Unimplemented

091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000092h PIE2 OSFIE C2IE C1IE EEIE BCL1IE CCP2IE 0000 0--0 0000 0--0093h PIE3 CCP4IE CCP3IE TMR6IE TMR4IE --00 0-0- --00 0-0-094h PIE4 BCL2IE SSP2IE ---- --00 ---- --00095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111096h PCON STKOVF STKUNF RMCLR RI POR BOR 00-- 11qq qq-- qquu097h WDTCON WDTPS SWDTEN --01 0110 --01 0110098h OSCTUNE TUN --00 0000 --00 0000099h OSCCON SPLLEN IRCF SCS1 SCS0 0011 1-00 0011 1-0009Ah OSCSTAT T1OSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 10q0 0q00 qqqq qq0q09Bh ADRESL A/D Result Register Low xxxx xxxx uuuu uuuu09Ch ADRESH A/D Result Register High xxxx xxxx uuuu uuuu09Dh ADCON0 CHS GO/DONE ADON -000 0000 -000 000009Eh ADCON1 ADFM ADCS ADNREF ADPREF 0000 -000 0000 -00009Fh Unimplemented

TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)


Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.

Note 1: These registers can be addressed from any bank.


PIC16(L)F1847




xxxx xxxx xxxx xxxx

102h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000103h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000108h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000109h(1) WREG Working Register 0000 0000 uuuu uuuu10Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000010Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u10Ch LATA LATA7 LATA6 LATA4 LATA3 LATA2 LATA1 LATA0 xx-x xxxx uu-u uuuu10Dh LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx xxxx uuuu uuuu10Eh Unimplemented

10Fh Unimplemented

110h Unimplemented

111h CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1HYS C1SYNC 0000 -100 0000 -100112h CM1CON1 C1INTP C1INTN C1PCH C1NCH 0000 --00 0000 --00113h CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2HYS C2SYNC 0000 -100 0000 -100114h CM2CON1 C2INTP C2INTN C2PCH C2NCH 0000 --00 0000 --00115h CMOUT MC2OUT MC1OUT ---- --00 ---- --00116h BORCON SBOREN BORRDY 1--- ---q u--- ---u117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR ADFVR 0qrr 0000 0qrr 0000118h DACCON0 DACEN DACLPS DACOE DACPSS DACNSS 000- 00-0 000- 00-0119h DACCON1 DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 000011Ah SRCON0 SRLEN SRCLK SRQEN SRNQEN SRPS SRPR 0000 0000 0000 000011Bh SRCON1 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E 0000 0000 0000 000011Ch Unimplemented

11Dh APFCON0 RXDTSEL SDO1SEL SS1SEL P2BSEL CCP2SEL P1DSEL P1CSEL CCP1SEL 0000 0000 0000 000011Eh APFCON1 TXCKSEL ---- ---0 ---- ---011Fh Unimplemented





PIC16(L)F1847





xxxx xxxx xxxx xxxx

182h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000183h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000188h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000189h(1) WREG Working Register 0000 0000 uuuu uuuu18Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000018Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u18Ch ANSELA ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 ---1 1111 ---1 111118Dh ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 1111 111- 1111 111-18Eh Unimplemented

18Fh Unimplemented

190h Unimplemented

191h EEADRL EEPROM / Program Memory Address Register Low Byte 0000 0000 0000 0000192h EEADRH EEPROM / Program Memory Address Register High Byte -000 0000 -000 0000193h EEDATL EEPROM / Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu194h EEDATH EEPROM / Program Memory Read Data Register High Byte --xx xxxx --uu uuuu195h EECON1 EEPGD CFGS LWLO FREE WRERR WREN WR RD 0000 x000 0000 q000196h EECON2 EEPROM control register 2 0000 0000 0000 0000197h Unimplemented

198h Unimplemented

199h RCREG USART Receive Data Register 0000 0000 0000 000019Ah TXREG USART Transmit Data Register 0000 0000 0000 000019Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 000019Ch SPBRGH Baud Rate Generator Data Register High 0000 0000 0000 000019Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 001019Fh BAUDCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 01-0 0-00 01-0 0-00






PIC16(L)F1847




xxxx xxxx xxxx xxxx

202h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000203h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000208h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000209h(1) WREG Working Register 0000 0000 uuuu uuuu20Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000020Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u20Ch WPUA WPUA5 --1- ---- --1- ----20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 111120Eh Unimplemented

20Fh Unimplemented

210h Unimplemented

211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu212h SSP1ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000213h SSP1MSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 1111214h SSP1STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000215h SSP1CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000218h Unimplemented

219h SSP2BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu21Ah SSP2ADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 000021Bh SSP2MSK Synchronous Serial Port (I2C mode) Address Mask Register 1111 1111 1111 111121Ch SSP2STAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 000021Dh SSP2CON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 000021Eh SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 000021Fh SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000





PIC16(L)F1847





xxxx xxxx xxxx xxxx

282h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000283h(1) STATUS TO PD Z DC C ---1 1000 ---q quuu284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000288h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000289h(1) WREG Working Register 0000 0000 uuuu uuuu28Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 000028Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u28Ch Unimplemented

28Dh Unimplemented

28Eh Unimplemented

28Fh Unimplemented

290h Unimplemented

291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu292h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx uuuu uuuu293h CCP1CON P1M DC1B CCP1M 0000 0000 0000 0000294h PWM1CON P1RSEN P1DC 0000 0000 0000 0000295h CCP1AS CCP1ASE CCP1AS PSS1AC PSS1BD 0000 0000 0000 0000296h PSTR1CON STR1SYNC STR1D STR1C STR1B STR1A ---0 0001 ---0 0001297h Unimplemented

298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu29Ah CCP2CON P2M DC2B CCP2M 0000 0000 0000 000029Bh PWM2CON P2RSEN P2DC 0000 0000 0000 000029Ch CCP2AS CCP2ASE CCP2AS PSS2AC PSS2BD 0000 0000 0000 000029Dh PSTR2CON STR2SYNC STR2D STR2C STR2B STR2A ---0 0001 ---0 000129Eh CCPTMRS C4TSEL C3TSEL C2TSEL C1TSEL 0000 0000 0000 000029Fh Unimplemented






PIC16(L)F1847




xxxx xxxx xxxx xxxx


30Dh Unimplemented

30Eh Unimplemented

30Fh Unimplemented

310h Unimplemented

311h CCPR3L Capture/Compare/PWM Register 3 (LSB) xxxx xxxx uuuu uuuu312h CCPR3H Capture/Compare/PWM Register 3 (MSB) xxxx xxxx uuuu uuuu313h CCP3CON DC3B CCP3M --00 0000 --00 0000314h Unimplemented

315h Unimplemented

316h Unimplemented

317h Unimplemented

318h CCPR4L Capture/Compare/PWM Register 4 (LSB) xxxx xxxx uuuu uuuu319h CCPR4H Capture/Compare/PWM Register 4 (MSB) xxxx xxxx uuuu uuuu31Ah CCP4CON DC4B CCP4M --00 0000 --00 000031Bh Unimplemented

31Ch Unimplemented

31Dh Unimplemented

31Eh Unimplemented

31Fh Unimplemented





PIC16(L)F1847





xxxx xxxx xxxx xxxx


38Dh Unimplemented

38Eh Unimplemented

38Fh Unimplemented

390h Unimplemented

391h Unimplemented

392h Unimplemented

393h Unimplemented

394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 0000 0000397h Unimplemented

398h Unimplemented

399h Unimplemented

39Ah CLKRCON CLKREN CLKROE CLKRSLR CLKRDC CLKRDIV 0011 0000 0011 000039Bh Unimplemented

39Ch MDCON MDEN MDOE MDSLR MDOPOL MDBIT 0010 ---0 0010 ---039Dh MDSRC MDMSODIS MDMS x--- xxxx u--- uuuu39Eh MDCARL MDCLODIS MDCLPOL MDCLSYNC MDCL xxx- xxxx uuu- uuuu39Fh MDCARH MDCHODIS MDCHPOL MDCHSYNC MDCH xxx- xxxx uuu- uuuu






PIC16(L)F1847




xxxx xxxx xxxx xxxx


40Dh Unimplemented

40Eh Unimplemented

40Fh Unimplemented

410h Unimplemented

411h Unimplemented

412h Unimplemented

413h Unimplemented

414h Unimplemented

415h TMR4 Timer4 Module Register 0000 0000 0000 0000416h PR4 Timer4 Period Register 1111 1111 1111 1111417h T4CON T4OUTPS TMR4ON T4CKPS -000 0000 -000 0000418h Unimplemented

419h Unimplemented

41Ah Unimplemented

41Bh Unimplemented

41Ch TMR6 Timer6 Module Register 0000 0000 0000 000041Dh PR6 Timer6 Period Register 1111 1111 1111 111141Eh T6CON T6OUTPS TMR6ON T6CKPS -000 0000 -000 000041Fh Unimplemented





PIC16(L)F1847


Banks 9-30x00h/x80h(1)

INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory(not a physical register)

xxxx xxxx xxxx xxxx

x00h/x81h(1)

INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register)

xxxx xxxx xxxx xxxx

x02h/x82h(1)

PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000

x03h/x83h(1)

STATUS TO PD Z DC C ---1 1000 ---q quuu

x04h/x84h(1)

FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu

x05h/x85h(1)

FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000

x06h/x86h(1)

FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu

x07h/x87h(1)

FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000

x08h/x88h(1)

BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000

x09h/x89h(1)

WREG Working Register 0000 0000 uuuu uuuu

x0Ah/x8Ah(2)

PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000

x0Bh/x8Bh(1)

INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000u

x0Ch/x8Ch x1Fh/x9Fh

Unimplemented






PIC16(L)F1847

Bank 31F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory


F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory(not a physical register)

xxxx xxxx xxxx xxxx

F82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000F83h(1) STATUS TO PD Z DC C ---1 1000 ---q quuuF84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuuF85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuuF87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000F88h(1) BSR BSR4 BSR3 BSR2 BSR1 BSR0 ---0 0000 ---0 0000F89h(1) WREG Working Register 0000 0000 uuuu uuuuF8Ah(1) PCLATH Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000F8Bh(1) INTCON GIE PEIE TMR0IE INTE IOCE TMR0IF INTF IOCF 0000 000x 0000 000uF8Ch FE3h

Unimplemented

FE4h STATUS_SHAD

Z_SHAD DC_SHAD C_SHAD ---- -xxx ---- -uuu

FE5h WREG_SHAD

Working Register Shadow 0000 0000 uuuu uuuu

FE6h BSR_SHAD

Bank Select Register Shadow ---x xxxx ---u uuuu

FE7h PCLATH_SHAD

Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu

FE8h FSR0L_SHAD

Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu

FE9h FSR0H_SHAD

Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu

FEAh FSR1L_SHAD

Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu

FEBh FSR1H_SHAD

Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu

FECh Unimplemented

FEDh STKPTR Current Stack pointer ---1 1111 ---1 1111FEEh TOSL Top-of-Stack Low byte xxxx xxxx uuuu uuuuFEFh TOSH Top-of-Stack High byte -xxx xxxx -uuu uuuu





PIC16(L)F1847


3.3 PCL and PCLATHThe Program Counter (PC) is 15 bits wide. The low bytecomes from the PCL register, which is a readable andwritable register. The high byte (PC) is not directlyreadable or writable and comes from PCLATH. On anyReset, the PC is cleared. Figure 3-3 shows the fivesituations for the loading of the PC.

FIGURE 3-3: LOADING OF PC IN DIFFERENT SITUATIONS

3.3.1 MODIFYING PCLExecuting any instruction with the PCL register as thedestination simultaneously causes the Program Coun-ter PC bits (PCH) to be replaced by the contentsof the PCLATH register. This allows the entire contentsof the program counter to be changed by writing thedesired upper 7 bits to the PCLATH register. When thelower 8 bits are written to the PCL register, all 15 bits ofthe program counter will change to the values con-tained in the PCLATH register and those being writtento the PCL register.

3.3.2 COMPUTED GOTOA computed GOTO is accomplished by adding an offset tothe program counter (ADDWF PCL). When performing atable read using a computed GOTO method, care shouldbe exercised if the table location crosses a PCL memoryboundary (each 256-byte block). Refer to the ApplicationNote AN556, Implementing a Table Read (DS00556).

3.3.3 COMPUTED FUNCTION CALLSA computed function CALL allows programs to maintaintables of functions and provide another way to executestate machines or look-up tables. When performing atable read using a computed function CALL, careshould be exercised if the table location crosses a PCLmemory boundary (each 256-byte block).

If using the CALL instruction, the PCH and PCLregisters are loaded with the operand of the CALLinstruction. PCH is loaded with PCLATH.

The CALLW instruction enables computed calls by com-bining PCLATH and W to form the destination address.A computed CALLW is accomplished by loading the Wregister with the desired address and executing CALLW.The PCL register is loaded with the value of W andPCH is loaded with PCLATH.

3.3.4 BRANCHINGThe branching instructions add an offset to the PC.This allows relocatable code and code that crossespage boundaries. There are two forms of branching,BRW and BRA. The PC will have incremented to fetchthe next instruction in both cases. When using eitherbranching instruction, a PCL memory boundary may becrossed.

If using BRW, load the W register with the desiredunsigned address and execute BRW. The entire PC willbe loaded with the address PC + 1 + W.

If using BRA, the entire PC will be loaded with PC + 1 +,the signed value of the operand of the BRA instruction.

PCLPCH 014PC

06 7ALU Result

8

PCLATH

PCLPCH 014PC

06 4OPCODE

11PCLATH

PCLPCH 014PC

06 7W

8PCLATH

Instruction with PCL as

Destination

GOTO, CALL

CALLW

PCLPCH 014PC

PC + W15

BRW

PCLPCH 014PC

PC + OPCODE 15

BRA


PIC16(L)F18473.4 StackAll devices have a 16-level x 15-bit wide hardwarestack (refer to Figures 3-4 through 3-7). The stackspace is not part of either program or data space. ThePC is PUSHed onto the stack when CALL or CALLWinstructions are executed or an interrupt causes abranch. The stack is POPed in the event of a RETURN,RETLW or a RETFIE instruction execution. PCLATH isnot affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVRENbit = 0 (Configuration Word 2). This means that afterthe stack has been PUSHed sixteen times, the seven-teenth PUSH overwrites the value that was stored fromthe first

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