17. timing diagrams for altmemphy ip · 2020. 10. 1. · chapter 17: timing diagrams for altmemphy...

EMI_RM_015-1.3

© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIare trademarks of Altera Corporation and registered in the U.Strademarks or service marks are the property of their respectivsemiconductor products to current specifications in accordanceservices at any time without notice. Altera assumes no responsdescribed herein except as expressly agreed to in writing by Alon any published information and before placing orders for pr

External Memory Interface HandbookVolume 3: Reference MaterialNovember 2012

November 2012EMI_RM_015-1.3

17. Timing Diagrams for ALTMEMPHY IP

This chapter shows timing diagrams for the DDR, DDR2, and DDR3 SDRAM high-performance controllers II (HPC II).

DDR and DDR2 High-Performance Controllers IIThis section discusses the following timing diagrams for the DDR and DDR2 HPC II:

■ “Half-Rate Read”

■ “Half-Rate Write”

■ “Full-Rate Read”

■ “Full-Rate Write”

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17–2Chapter 17:

Timing Diagram

s for ALTMEM

PHY IPDDR and DDR2 High-Perform

ance Controllers II

External Mem

ory Interface HandbookNovem

ber 2012Altera Corporation

Volume 3: Reference M

aterial

EFF0011 AABBCCDD EEFF0011 AABBCCDD EEFF0011

0000000

3

F


[6]

[7]

Half-Rate Read

The following sequence corresponds with the numbered items in Figure 17–1:

Figure 17–1. Half-Rate Read Operation for HPC II

phy_clk

Local Interfacelocal_address[25:0]

local_size[4:0]local_ready

local_burstbeginlocal_read_req

local_rdata[31:0]local_rdata_valid

local_be[3:0]

afi_addr[27:0]

Controller - AFI

afi_ba[5:0]afi_cs_n[3:0]

AFI Command[2:0]afi_dm[3:0]

afi_dqs_burst[0]afi_dqs_burst[1]

afi_doing_rd[1:0]afi_rdata[31:0]

afi_rdata_valid[1:0]

mem_cke[1:0]

AFI Memory Interface

mem_clkmem_ba[2:0]

mem_addr[13:0]mem_cs_n[0]

Mem Command[2:0]mem_dqsmem_dm

mem_dq[7:0]mem_odt[1:0]

000000200000002

0000004 0000000

AABBCCDD E

0000000 0000000 0000008 00000000

0000010

B F B F BRD NOP RD NOPRD

F

3AABBCCDD E

0000 0000 0008 00000

0010

RD NOPNOP NOPRD NOP RD

DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE

[5]

[1] [2] [3] [4]

Chapter 17: Timing Diagrams for ALTMEMPHY IP 17–3DDR and DDR2 High-Performance Controllers II

1. The user logic requests the first read by asserting the local_read_req signal, and the size and address for this read. In this example, the request is a burst of length of 2 to the local address 0×000000. This local address is mapped to the following memory address in half-rate mode:

mem_row_address = 0×000000

mem_col_address = 0×0000

mem_bank_address = 0×00

2. The user logic initiates a second read to a different memory column within the same row. The request for the second write is a burst length of 2. In this example, the user logic continues to accept commands until the command queue is full. When the command queue is full, the controller deasserts the local_ready signal. The starting local address 0x000002 is mapped to the following memory address in half-rate mode:



17–4Chapter 17:

Timing Diagram

s for ALTMEM


ance Controllers II

External Mem




aterial

0000000

[4] [5] [6]

D AABBCCDDEEFF0011 EEFF0011

0000000

F

F0

3

000 0010

OP NOPWR

D CC BB AA 11 00 FF EE DD CC BB AA 11 00 FF EEDD CC BB AA 11 00 FF EE

Half-Rate Write

Figure 17–2. Half-Rate Write Operation for HPC II

Local Interface

local_address[25:0]

local_size[4:0]

local_ready

local_burstbegin

local_be[3:0]

local_write_req

local_wdata[31:0]

afi_addr[27:0]

Controller - AFI

afi_ba[5:0]

afi_cs_n[3:0]

AFI Command[2:0]

afi_dm[3:0]

afi_wlat[4:0]

afi_dqs_burst[0]

afi_dqs_burst[1]

afi_wdata[31:0]

afi_wdata_valid[1:0]

mem_cke[1:0]AFI Memory Interface

mem_clk

mem_ba[2:0]

mem_addr[13:0]

mem_cs_n[0]

Mem Command[2:0]

mem_dqs

mem_dm

mem_dq[7:0]

mem_odt[1:0]

phy_clk

00000020000000 00000042

[1] [2] [3]

AABBCCDD AABBCCDD AABBCCDDEEFF0011 EEFF0011 EEFF0011

AABBCCDD AABBCCDEEFF0011

0000000 0000000 0000000 0000000 0000008 0000000 0000010

B F B F B F B F B

ACT NOP WR NOP WR NOP WR NOPNOP WR

0 FF

2

3 0

0000 0000 0000 0000 0008 0

NOP ACT NOP WR NOP NOP NWR WR

00 00 D



1. The user logic asserts the first write request to row 0 so that row 0 is open before the next transaction.

2. The user logic asserts a second local_write_req signal with size of 2 and address of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is asserted along with the local_write_req signal, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle. If the local_ready signal was not asserted, the user logic must keep the write request, size, and address signals asserted until the local_ready signal is registered high.

3. The controller issues the necessary memory command and address signals to the ALTMEMPHY megafunction for it to send to the memory device.

4. The controller asserts the afi_wdata_valid signal to indicate to the ALTMEMPHY megafunction that valid write data and write data masks are present on the inputs to the ALTMEMPHY megafunction.

5. The controller asserts the afi_dqs_burst signals to control the timing of the DQS signal that the ALTMEMPHY megafunction issues to the memory.

6. The ALTMEMPHY megafunction issues the write command, and sends the write data and write DQS to the memory.

November 2012 Altera Corporation External Memory Interface HandbookVolume 3: Reference Material

17–6Chapter 17:

Timing Diagram

s for ALTMEM


ance Controllers II

External Mem




aterial

ABCD EF01 ABCD EF01

ABCD EF01 ABCD EF01

[6]

[5]

Full-Rate Read

Figure 17–3. Full-Rate Read Operation for HPC II

phy_clk

local_address[23:0]local_size[2:0]

local_readylocal_burstbegin

local_read_reqlocal_rdata_validlocal_rdata[15:0]

local_be[1:0]

afi_addr[12:0]afi_ba[1:0]

afi_cs_nAFI Command[2:0]

afi_dm[1:0]afi_dqs_burstafi_doing_rd

afi_rdata[15:0]afi_rdata_valid

mem_ckemem_clk

mem_ba[1:0]mem_addr[12:0]

mem_cs_nMem Command[2:0]

mem_dqsmem_dm

mem_dq[7:0]mem_odt

000000000000 000002

2

FFFFFFFF

3

0000

0

NOP NOP NOP

NOP NOP NOP

RD RD

RDRD

000000 000004

3

FFFFFFFF

0

00000000 0004

0000 00CD AB 01 EF CD AB 01 EF


Local Interface

Controller - AFI

[1] [2] [3]

[4]



1. The user logic requests the first read by asserting local_read_req signal, and the size and address for this read. In this example, the request is a burst length of 2 to a local address 0x000000. This local address is mapped to the following memory address in full-rate mode:



17–8Chapter 17:

Timing Diagram

s for ALTMEM


ance Controllers II

External Mem




aterial

000000

0000

0000

NOP

0 3

EF01 ABCD EF01 ABCD EF01

0 0010 0000

OP WR NOP

CD AB 01 EF CD AB 01 EF CD AB 01 EF

[5]

[4]

Full-Rate Write

Figure 17–4. Full-Rate Write Operation for HPC II

phy_clk



local_be[1:0]local_write_req

local_rdata[15:0]local_wdata[15:0]

afi_addr[12:0]afi_ba[1:0][1:0]

afi_cs_nAFI Command[2:0]

afi_dm[1:0]afi_wlat[4:0]

afi_dqs_burstafi_wdata[15:0]afi_wdata_valid

mem_ckemem_clk


mem_cs_nMem Command[2:0]

mem_dqsmem_dm

mem_dq[7:0]mem_odt

000000 000004 000008

2

3

FFFF

0000 ABCD EF01 ABCD EF01 ABCD EF01

0000 0008 0000 0010

0

NOP ACT NOP WR NOP WR NOP WR NOP WR

3 0 3

04

0000 ABCD

0

0000 0008 000

NOP ACT NOP WR NOP WR NOP WR N

00

Local Interface

Controller - AFI


[3][2][1]

[6]

Chapter 17: Timing Diagrams for ALTMEMPHY IP 17–9DDR3 High-Performance Controller II



2. The user logic asserts a second local_write_req signal with a size of 2 and address of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is asserted along with the local_write_req signal, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle. If the local_ready signal was not asserted, the user logic must keep the write request, size, and address signals asserted until the local_ready signal is registered high.





DDR3 High-Performance Controller IIThis section discusses the following timing diagrams for the DDR3 HPC II:

■ “Half-Rate Read”

■ “Half-Rate Write”

■ “Half-Rate Read (Non Burst-Aligned Address)”

■ “Half-Rate Write (Non Burst-Aligned Address)”

■ “Half-Rate Read With Gaps”

■ “Full-Rate Read”

■ “Half-Rate Write Operation (Merging Writes)”

■ “Write-Read-Write-Read Operation”


17–10Chapter 17:

Timing Diagram

s for ALTMEM

PHY IPDDR3 High-Perform

ance Controller II

External Mem




aterial


0000000

3

F


[6]

[7]

Half-Rate Read (Burst-Aligned Address)

Figure 17–5. Half-Rate Read Operation for HPC II—Burst-Aligned Address

phy_clk





local_be[3:0]

afi_addr[27:0]

Controller - AFI






mem_cke[1:0]


mem_clkmem_ba[2:0]




000000200000002

0000004 0000000

AABBCCDD E

0000000 0000000 0000008 00000000

0000010

B F B F BRD NOP RD NOPRD

F

3AABBCCDD E

0000 0000 0008 00000

0010

RD NOPNOP NOPRD NOP RD

DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE DDCCBB AA 11 00 FF EE

[5]

[1] [2] [3] [4]






mem_bank_address = 0×00

2. The user logic initiates a second read to a different memory column within the same row. The request for the second read is a burst length of 2. In this example, the user logic continues to accept commands until the command queue is full. When the command queue is full, the controller deasserts the local_ready signal. The starting local address 0x000002 is mapped to the following memory address in half-rate mode:



17–12Chapter 17:

Timing Diagram

s for ALTMEM


ance Controller II

External Mem




aterial

0000000

[4] [5] [6]

D AABBCCDDEEFF0011 EEFF0011

0000000

F

F0

3

000 0010

OP NOPWR

D CC BB AA 11 00 FF EE DD CC BB AA 11 00 FF EEDD CC BB AA 11 00 FF EE

Half-Rate Write (Burst-Aligned Address)

Figure 17–6. Half-Rate Write Operation for HPC II—Burst-Aligned Address

Local Interface

local_address[25:0]

local_size[4:0]

local_ready

local_burstbegin

local_be[3:0]

local_write_req

local_wdata[31:0]

afi_addr[27:0]

Controller - AFI

afi_ba[5:0]

afi_cs_n[3:0]

AFI Command[2:0]

afi_dm[3:0]

afi_wlat[4:0]

afi_dqs_burst[0]

afi_dqs_burst[1]

afi_wdata[31:0]


mem_cke[1:0]AFI Memory Interface

mem_clk

mem_ba[2:0]

mem_addr[13:0]

mem_cs_n[0]

Mem Command[2:0]

mem_dqs

mem_dm

mem_dq[7:0]

mem_odt[1:0]

phy_clk

00000020000000 00000042

[1] [2] [3]

AABBCCDD AABBCCDD AABBCCDDEEFF0011 EEFF0011 EEFF0011

AABBCCDD AABBCCDEEFF0011

0000000 0000000 0000000 0000000 0000008 0000000 0000010

B F B F B F B F B

ACT NOP WR NOP WR NOP WR NOPNOP WR

0 FF

2

3 0

0000 0000 0000 0000 0008 0

NOP ACT NOP WR NOP NOP NWR WR

00 00 D




2. The user logic asserts a second local_write_req signal with size of 2 and address of 0 (col = 0, row = 0, bank = 0, chip = 0). The local_ready signal is asserted along with the local_write_req signal, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle. If the local_ready signal was not asserted, the user logic must keep the write request, size, and address signals asserted until the local_ready signal is registered high.






17–14Chapter 17:

Timing Diagram

s for ALTMEM


ance Controller II

External Mem




aterial

BBCCDD EEFFEEFFAABBAABB AABBAABBEEFF0011 AABBCCDD EEFF0011AABBCCDD EEFFEEFFAABBAABB EEFF0011

BBCCDD EEFFEEFFAABBAABB AABBAABBEEFF0011 AABBCCDD EEFF0011AABBCCDD EEFFEEFFAABBAABBEEFF0011

00000

F

F

3 0 3 0 3 0 3 0 3 0 3

P 7

A

[5]

[6]

Half-Rate Read (Non Burst-Aligned Address)

Figure 17–7. Half-Rate Read Operation for HPC II—Non Burst-Aligned Address

phy_clk



local_read_reqlocal_rdata[31:0]local_rdata_valid

local_be[3:0]


afi_cs_n[3:0]AFI Command[2:0]

afi_dm[3:0]afi_dqs_burst[0]afi_dqs_burst[1]



mem_cke[1:0]


Controller - AFI

Local Interface

mem_clkmem_ba[2:0]




00000 00001 00003 00005 00000

2

AA

AA

00000 10004 00000 20008 00000 3000C 00000 40010 00000 50014 00000 60018

B F B F B F B F B F B

NOP NOPNOPNOPNOPNOPNOP RD RD RD RD RD RD

3 0 3 0 3 0 3 0 3 0 3

00

0

0000 0004 0000 0008 0000 000C 0000 0010 0000 0014 0000 0018

NOP NOP NOP NOP NOP NOP NORD RD RD RD RD RD

AADD BBCC 00 FF EE11 AADD BBCC ADD BBCC00 FF EE1100 00 00 00 00

[1] [2] [3]

[4]

17–16Chapter 17:

Timing Diagram

s for ALTMEM


ance Controller II

External Mem




aterial

0000000

FNOP

F 0

D0 3

0010 0000

NOPWR

00 DD CC BB AA 00 11 00 FF EE

Half-Rate Write (Non Burst-Aligned Address)

Figure 17–8. Half-Rate Write Operation for HPC II—Non Burst-Aligned Address




local_wdata[31:0]


afi_cs_n[3:0]AFI Command[2:0]

afi_dm[3:0]afi_wlat[4:0]

afi_dqs_burst[0]afi_dqs_burst[1]afi_wdata[31:0]


mem_cke[1:0]mem_clk


mem_cs_n[0]Mem Command[2:0]

mem_dqsmem_dm


phy_clk

0000001 00000032

0000001 0000003 0000005

AABBCCDD EEFF0011 AABBCCDD EEFF0011

0010004 0000000 0020008 0000000 003000C 0000000 0040010

B F B F B F BWR NOP NOP NOPWR WR WR

0 F 0 F 0

AABBCCDD EEFF0011 AABBCCD3 0 3 0 3

0004 0000 0008 0000 000C 0000

WR NOP WR NOP WR NOP

DD CC BB AA 00 11 00 FF EE

Local Interface

Controller - AFI


[5][4]

[1] [2] [3]



1. The user logic asserts the first local_write_req signal with a size of 2 and an address of 0×000001. The local_ready signal is asserted along with the local_write_req signal, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle. If the local_ready signal was not asserted, the user logic must keep the write request, size, and address signals asserted until the local_ready signal is registered high. The local address 0x000001 is mapped to the following memory address in half-rate mode:



17–18Chapter 17:

Timing Diagram

s for ALTMEM


ance Controller II

External Mem




aterial

00000000

00000000

0 3 0 3

Half-Rate Read With Gaps

Figure 17–9. Half-Rate Read Operation for HPC II—With Gaps





local_be[3:0]

afi_addr[27:0]

Controller - AFI






mem_cke[1:0]


mem_clkmem_ba[2:0]




0000912

2

0000810 0000A14

5101440 0004001 000000000000000000000 4121048 0004001 0000000 4141050 0000000

00 24 00 09 00 09 12 2D 00 09 00 09 12 00 12

F B F B F B F B F B F

NOP NOP NOP NOPRD ACT RD ACT RD

FF

0 3 0 3 0 3

0 3

7 0 1 0 1 2 0 2

0000 0001 0000 1440 0001 0000 1048 0001 0000 1050

ACT RD NOP ACT RD NOP ACT RD NOP ACT RD NOP

00 00 00 00 00 00 00 00

phy_clk

[1] [2] [3] [4] [5]

17–20 Chapter 17: Timing Diagrams for ALTMEMPHY IPDDR3 High-Performance Controller II


1. The user logic asserts a local_write_req signal with a size of 2 and an address of 0×0000F1C.





6. For transactions with a local size of two, the local_write_req and local_ready signals must be high for two clock cycles so that all the write data can be transferred to the controller.

Half-Rate Write Operation (Merging Writes)

Figure 17–11. Write Operation for HPC II—Merging Writes

local_address[25:0]

Local Interface


local_burstbeginlocal_be[3:0]

local_write_reqlocal_wdata[31:0]

afi_addr[27:0]Controller - AFI



afi_wlat[4:0]afi_dqs_burst[0]afi_dqs_burst[1]afi_wdata[31:0]


mem_ckeAFI Memory Interface

mem_clkmem_ba[2:0]




00000010000000 0000002 0000003

22222222 3333333300000000 00000000

0000000 4001000 0000000 4021008 0000000

F B F B F B FACT NOP

NOPACT

NOP NOPWR WR0

00000000 22222222 33333333 000000003 0 3

1000 0000 1008 0000

WR NOP WR NOP

00 22 33 00

phy_clk

[2][1] [5] [4] [6][3]

External Memory Interface Handbook November 2012 Altera CorporationVolume 3: Reference Material



1. The user logic asserts the first local_write_req signal with a size of 1 and an address of 0×000000. The local_ready signal is asserted along with the local_write_req signal, which indicates that the controller has accepted this request, and the user logic can request another read or write in the following clock cycle. If the local_ready signal was not asserted, the user logic must keep the write request, size, and address signals asserted until the local_ready signal is registered high. The local address 0x000000 is mapped to the following memory address in half-rate mode:



17–22Chapter 17:

Timing Diagram

s for ALTMEM


ance Controller II

External Mem




aterial

00000000 00000010

0

3

00000000 000000100 3

0 0018

NOP

WR

10 1800 00

[13]

[12]

Write-Read-Write-Read Operation

Figure 17–12. Write-Read Sequential Operation for HPC II

Local Interface



local_read_reqlocal_rdata[31:0]local_rdata_valid


local_wdata[31:0]

afi_addr[27:0]

Controller - AFI



afi_wlat[4:0]afi_wdata[31:0]

afi_doing_rd[1:0]afi_wdata_valid[1:0]


afi_rdata[31:0]afi_rdata_valid[1:0]

mem_cke[1:0]


mem_clkmem_ba[2:0]




0000002 0000004 0000006

0000000000000000 00000008

00000008 00000010 00000018

0040010 0040010 00600180000000 0020008 00200080000000 0000000 0000000 0000000

F B F B F B F B F B

F 0 F 0 F

00000000 00000008 00000010

00 3 0 30 3 0 3 0

0000000000000000 000000080 3

0000 0008 0000 0008 0000 0010 0000 0010 000

NOP WR NOP RD

NOP WR WR WRNOP NOP NOP NOPRD RD

NOP NOP NOPWR RD

00 08 1008 00 00 00 00 00 00

phy_clk

[1] [2] [3] [4] [5] [8] [9]

[6][7][10] [11]



1. The user logic requests the first write by asserting the local_write_req signal, and the size and address for this write. In this example, the request is a burst length of 1 to a local address 0x000002. This local address is mapped to the following memory address in half-rate mode:



17–24 Chapter 17: Timing Diagrams for ALTMEMPHY IPDocument Revision History

13. The controller returns the first read data to the user by asserting the local_rdata_valid signal when there is valid read data on the local_rdata bus. If the ECC logic is disabled, there is no delay between the afi_rdata and the local_rdata buses. If there is ECC logic in the controller, there is one or three clock cycles of delay between the afi_rdata and local_rdata buses.

Document Revision HistoryTable 17–1 lists the revision history for this document.

Table 17–1. Document Revision History

Date Version Changes

November 2012 1.3 Changed chapter number from 15 to 17.

June 2012 1.2 Added Feedback icon.

November 2011 1.1Consolidated timing diagrams from 11.0 version DDR and DDR2 SDRAM Controller with ALTMEMPHY IP User Guide and DDR3 SDRAM Controller with ALTMEMPHY IP User Guide.

External Memory Interface Handbook November 2012 Altera CorporationVolume 3: Reference Material

17. Timing Diagrams for ALTMEMPHY IPDDR and DDR2 High-Performance Controllers IIHalf-Rate ReadHalf-Rate WriteFull-Rate ReadFull-Rate Write

DDR3 High-Performance Controller IIHalf-Rate Read (Burst-Aligned Address)Half-Rate Write (Burst-Aligned Address)Half-Rate Read (Non Burst-Aligned Address)Half-Rate Write (Non Burst-Aligned Address)Half-Rate Read With GapsHalf-Rate Write With GapsHalf-Rate Write Operation (Merging Writes)Write-Read-Write-Read Operation

Document Revision History

17. timing diagrams for altmemphy ip · 2020. 10. 1. · chapter 17: timing diagrams for altmemphy...

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