2013 wwk6 counter 1 (design of counters)_portal_vg3

8/10/2019 2013 Wwk6 Counter 1 (Design of Counters)_portal_vg3

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Sequential Logic

(Chapter 2: Counters)

EMT 235 Digital Electronic Principles II


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Counter Countera group of flip-flopsthat are connected togetherto perform

counting operations.

Counters are categorized into two categories based on the way they

are clocked:

Asynchronous counter (or known as ripple counters)

the first flip-flop is clocked by the external clock pulse and then each

successive flip-flop is clocked by the output of the preceding flip-flop

do not have a common clock pulse

flip-flops within the counter do no change states at exactly the same

time

Synchronous counter

the clock input is connected to all the flip-flops so that they are

clocked simultaneously by a common clock pulse


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Asynchronous counters


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2 bit asynchronous binary counter

Clk no Clk Q0 /Q0 Q1

- 0 1 0

1 1 0 0

2 0 1 1

3 1 0 1

4 0 1 0

CLK is applied to the clock input (C) of the first flip-flop, FF0. FF0 is

always the least significant bit (LSB).

The Q0output of FF0 is connected to the clock input of FF1. Due to the propagation delay of the flip-flop, a transition of the input clock

pulse (CLK) and Q0output can never occur simultaneously asynchronous

Since it goes through abinary

sequence, it is called abinary counter

LSB

Assume the FFs are

initially RESET


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2 bit asynchronous binary counter cont

The positive-going edge of CLK1 (clock pulse 1) causes the Q0output of

FF0 to go HIGH and /Q0to go LOW but this has no effect on FF1 because

positive-going transition must occur to trigger FF1. (Q0= 1, Q1= 0)

The positive-going transition of CLK2 causes Q0to go LOW. The output

/Q0goes HIGH and triggers FF1, causing Q1to go HIGH. (Q0= 0, Q1= 1)

The positive-going edge of CLK3 caused Q0to go HIGH. The output /Q0

goes LOW and this has no effect on FF1 (Q0= 1, Q1= 1)

The positive-going edge of CLK4 causes Q0to go LOW. The output /Q0goes HIGH and triggers FF1, causing Q1to go LOW. (Q0= 0, Q1= 0)


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No. Clk Q0 /Q0 Q1 /Q1 Q2

0 - 0 1 0 1 0

1 1 0 0 1 0

2 0 1 1 0 0

3 1 0 1 0 0

4 0 1 0 1 1

5 1 0 0 1 1

6 0 1 1 0 1

7 1 0 1 0 1

8 0 1 0 1 0

Assume the FFs are initially RESET


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Clk no. Clk Q0 Q1 Q2 Q3

0 - 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 04 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

Clk no. Clk Q0 Q1 Q2 Q3

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 113 1 0 1 1

14 0 1 1 1

15 1 1 1 1

16 0 0 0 0

Assume the FFs

are initially

RESET


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4 bit asynchronous binary counter cont


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Asynchronous countersare known as ripple countersbecause the effect of

the input clock pulse does not affect all the outputs of the flip-flops

simultaneously but ripples through the counter due to propagation delay.

Propagation delay

Q1is delayed by 1 delay Q2is delayed by 2 delays Q3is delayed by 3 delays


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Propagation delay cont The cumulative delayof an asynchronous counter is a major disadvantage

especially in high speed applicationsbecause it limits the rateat which the

counter can be clockedand creates decoding problems.

The maximum cumulative delayin a counter must be lessthan theperiodof

the clock waveform


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Modulus of a counter modulus of a counternumber of unique statesthrough which the counter

will sequence

maximum modulusthe maximum possible of statesof a counter is 2n,where nis the number of flip-flops in the counter

truncated sequencethe number of stateswith a sequence less than themaximum of 2n

decade countera counter with ten statesin their sequence (MOD10). Acommon modulus for counters

binary coded decimal (BCD) decade countera decade counter with a count

sequence of zero (0000) through (1001). The ten-state sequence produce theBDC code

to obtain a truncated sequence, it is necessary to force the counter to recyclebefore going through all its possible states (e.g. a BCD counter must recycle

back to 0000 after 1001 state)


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4 bit asynchronous decade counter

Q1

and Q3

are connected to a

NAND gate inputs to decode

the count of ten (1010)

because non of the other states

(zero through nine) have Q1

and Q3HIGH at the same time When counter goes into count

ten (1010), the output of the

NAND gate goes LOW and

resets all the flip-flops

Clk pulse CLK Q0 Q1 Q2 Q3 /CLR

0 - 0 0 0 0 0

1 1 0 0 0 0

2 0 1 0 0 0

3 1 1 0 0 0

4 0 0 1 0 0

5 1 0 1 0 0

6 0 1 1 0 07 1 1 1 0 0

8 0 0 0 1 0

9 1 0 0 1 0

10 0 1 0 1 1

10 0 0 0 0 0

Assume the FFs are initially RESET


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4 bit asynchronous decade counter cont ..

A glitch on Q1waveform because Q1must first go HIGH before the count of

ten can be decoded. When the counter goes into the count of ten (1010), the

output of the NAND gate goes LOW.

Thus, the counter is in the 1010 state for a short time before it is RESET to

0000, thus producing a glitch on Q1and /CLR line.

Show how an asynchronous counter can be implemented having a modulus

of 14 with a straight binary sequence from 0000 through 1101.

glitch

glitch


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AnswerAn asynchronous counter having a modulus of 14 with a

straight binary sequence from 0000 through 1101.


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74LS93 asynchronous binary counter consists of a single flip-flop and a 3-bit asynchronous counter.

can be used as a divide-by-2 device if only the single flip-flop is used, or it

can be used as a modulus-8 counter if only the 3-bit counter portion is used.

RO(1)andRO(2)- gated reset inputs. When both of these inputs are HIGH,the counter is reset to the 0000 state/CLR.

modulus-8 counter

divide-by-2 device

Logic diagram


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74LS93 asynchronous binary counter cont The 74LS93 can be used as a 4-bit modulus-16 counter (counts 0 through

15) by connecting the Q0output to the CLK B input as shown in (a).

It can also be configured as a decade counter (counts 0 through 9) withasynchronous recycling by using the gated reset inputs for partial decoding

of count ten (1010), as shown in (b)

Immediately after the counter goes to count 10 (1010), it is reset to 0000.

The recycling, however, results in a glitch on Q1because the counter mustgo into the 1010 state for several nanoseconds before recycling.

(a) (b)

Question: How do you connect the 74LS93 as a modulus-14 counter ?

Q3= MSB

Q0= LSB


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Answer


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Synchronous counters


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2-bit synchronous binary counter The flip-flops are initially RESET.

When the clock triggers the flip-

flops, there is a propagation delaybefore the output of the flip-flopsmake a transition.

counter

Timing details


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2-bit synchronous binary counter cont 2. Put the counter in an

arbitrary state; then determine

the inputs for this state.

3. Use the new inputs

to determine the next

state:

4. Set up the next

group of inputs from

the current output.

1. Determine

the flip-flop

input equations

No Clk Outputs Flip-flops inputs At the next clock pulse

Q1 Q0 J1= K1= Q0 J0= K0 =1 J1= K1 J0= K0

0 0 0 1 NC Toggle

1 0 1 1 1 Toggle Toggle

2 1 0 0 1 NC Toggle

3 1 1 1 1 Toggle Toggle

4 0 0 0 1 NC Toggle

Timing diagram

3 bit h bi t


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3-bit synchronous binary counter

Timing diagram

Counter

4 bit h bi t


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4 bit synchronous binary counter

No. Outputs Flip-flops inputs

Q0 Q1 Q2 Q3 J0= K0= 1 J1= K1= Q0 J2= K2= Q0Q1 J2= K2= Q0Q1Q2

0 0 0 0 1 0 0 0

1 1 0 0 0 1 1 0 0

2 0 1 0 0 1 0 0 0

3 1 1 0 0 1 1 1 0

4 0 0 1 0 1 0 0 0

2. Put the counter in anarbitrary state; then determine


3. Use the new inputsto determine the next

state:

4. Set up the nextgroup of inputs from

the current output.

1. Determinethe flip-flop

input equations

flip-flop input equations

4 bit h bi t t


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4 bit synchronous binary counter cont

No. Outputs Flip-flops inputs

Q0 Q1 Q2 Q3 J0= K0= 1 J1= K1= Q0 J2= K2= Q0Q1 J2= K2= Q0Q1Q2

5 1 0 1 0 1 1 0 0

6 0 1 1 0 1 0 0 0

7 1 1 1 0 1 1 1 18 0 0 0 1 1 0 0 0

9 1 0 0 1 1 1 0 0

10 0 1 0 1 1 0 0 0

11 1 1 0 1 1 1 1 0

12 0 0 1 1 1 0 0 0

13 1 0 1 1 1 1 0 0

14 0 1 1 1 1 0 0 0

15 1 1 1 1 1 1 1 1

16 0 0 0 0

2. Put the counter in an

arbitrary state; then determine




state:

4. Set up the next


the current output.

1. Determine

the flip-flop

input equations

4 i i


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4 bit synchronous binary counter cont

4 bit h d d t t


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Clk Outputs Flip-flops inputs

Q0 Q1 Q2 Q3 J0= K0= 1 J1= K1= Q0Q3 J2= K2= Q0Q1 J2= K2=

Q0Q1Q2 +Q0Q3

B4 0 0 0 0 1 0 0 01 1 0 0 0 1 1 0 0

2 0 1 0 0 1 0 0 0

3 1 1 0 0 1 1 1 0

4 0 0 1 0 1 0 0 0

5 1 0 1 0 1 1 0 0

4 bit synchronous decade counter cont Detects the occurrence of 1001 and causes the

counter to recycle on the next clock pulse

4 bit h d d t t


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4 bit synchronous decade counter cont

Clk Outputs Flip-flops inputs

Q0 Q1 Q2 Q3 J0= K0= 1 J1= K1= Q0Q3 J2= K2= Q0Q1 J2= K2=

Q0Q1Q2 +Q0Q3

6 0 1 1 0 1 0 0 0

7 1 1 1 0 1 1 1 1

8 0 0 0 1 1 0 0 0

9 1 0 0 1 1 0 0 1

10 0 0 0 0 1 0 0 0

No glitchis observed

in Q1waveform for

the synchronousdecade counter

4 bit s nchrono s decade co nter cont


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4 bit synchronous decade counter cont

FF0 (Q0) toggles on each clock

pulse, so J0= K0= 1.

FF1 (Q1) changes on the next

clock pulse each time Q0= 1

and Q3= 0, so J1= K1= Q1Q3.


clock pulse each time both Q0=

1 and Q1= 1, so J2= K2= Q0Q1.


clock pulse each time both Q0=

1, Q1= 1 and Q2= 1 or when Q0

= 1 and Q3= 1, so J2= K2=

Q0Q1Q2 +Q0Q3.

74HC163 synchronous binary counter


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74HC163 synchronous binary counter This counter can be synchronously preset to any 4-bit binary number by applying

the proper levels to the parallel data inputs.

When a LOW is applied to theLOAD input, counter will assume the state of the data

inputs on the next clock pulse. Thus, the counter sequence can start with any 4-bitbinary number.

An active-LOW CLRinput synchronously resetsall four flip-flops in the counter.

The two enable inputs,ENP andENTmust both be HIGH for the counter tosequence through its binary states.

The ripple clock output (RCO) goes HIGH when the counter reaches the last state in

its sequence of fifteen, called the terminal count(TC =15). This output, inconjunction with the enable inputs, allows these counters to be cascaded for highercount sequences.

Question:

How do you connect this counter to

count from 4 to 11?

Timing signal of 74HC163


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D i f h t


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Design of synchronous counters The followings are the general steps used to design a

synchronous counter

1) obtain the state diagramfor the counter

2) obtain the state table (transition table)

3) choose the type of flip-flopsto be used

4) from the state table, obtain the required input for each

flip-flop to produce the next state for the given present

state based on the flip-flop excitation table5) obtain the simplified flip-flop inputequationsand/or

output equationsfrom the Karnaugh maps

6) implement the counter

D i f h t t


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Design of synchronous counters cont Construct the state diagram

Construct the next-state

table

Decide the type of flip-flop to

be used

Obtain the required input for

each flip-flop to produce the

next state for the given

present state

Karnaugh map

implementation to obtain the

flip-flops input equations

Counter implementation

State diagram


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State diagram A graphical representation of theprogression of statesthrough which the

circuit advances when it is clocked

For example, the state diagram for a 3-bit up/down binary counter that

counts from the binary states of 0 to 7 when X (user selection) is HIGH and

counts from binary states of 7 to 0 when X is LOW is

State diagram of a 3-bit up/down binary counter

State (binary number

represents the state of

the flip-flops)

Directed line

(transition from

the present state to

the next state)

Input duringpresent state

(labeled along the

directed line)

St t di t


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State diagram cont A state diagram contains the following elements:

a stateis represented by a circle. The binary numbers inside each circle

identify the state of the flip-flops. a transitionfrom the present state to the next state is represented by a

directed lineconnecting the circles.

input valueduring the present state is labeled along each directed line.

output value

if the output is only dependent on thepresent state, the output islabeled after the present state inside the circle and is preceded by aslash (/) Mealy circuit.

if the outputis dependent on thepresent state and the given inputs,the output is labeled after the input along the directed line between

the states and is preceded by a slash (/) Moore circuit.

state table (transition table)


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state table (transition table) a tabular representation of the functional relationships among thepresent

states, inputs, next statesand outputsof a sequential circuit. Present statethe current state of all the flip-flops at time, t.

Input (X)the value ofXfor each possible present state. Next statethe states of the flip-flops one clock cycle later at time t+1.

Output (Y)the value of Yat time tfor each present state and input condition

In general, a state table can either be written as

or in a two (2) dimensional form as

state table (transition table)


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state table (transition table) The derivation of state table consists of first listing all possible binary combinations

of present states and inputs

For example, the state table for the 3-bit up/down binary counter that counts fromthe binary states from 0 to 7 when X (user selection) is HIGH and counts from 7 to 0when X is LOW is given as

Present state Next state

X = 0 X = 1

Q2 Q1 Q0 Q2+ Q1

+ Q0+ Q2

+ Q1+ Q0

+

0 0 0 1 1 1 0 0 1

0 0 1 0 0 0 0 1 0

0 1 0 0 0 1 0 1 1

0 1 1 0 1 0 1 0 0

1 0 0 0 1 1 1 0 1

1 0 1 1 0 0 1 1 0

1 1 0 1 0 1 1 1 1

1 1 1 1 1 0 0 0 0

S R flip flop


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S-R flip-flop

Qcharacteristics

table

Q S R Q+

0 0 0 0

0 0 1 0

0 1 0 10 1 1 X

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 X

SR

Excitation Table

Q Q+ S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

00 01 11 10

0 0 0 X 1

1 1 0 X 1

State diagram

0

1

10

X0

01

0X

Characteristic equation:

Q+= S + RQ

D flip flop


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D flip-flop

Q

characteristicstable

Q D Q+

0 0 0

0 1 11 0 0

1 1 1

D

Excitation

Table

Q Q+ D

0 0 0

0 1 1

1 0 0

1 1 1

Characteristic equation

Q+= D

State transition

diagram

0

1

0

1

1

0

0 1

0 0 1

1 0 1

The input values are

the same as the next

state values

J-K flip-flop


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J-K flip-flop

Qcharacteristics

table

Q J K Q+

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

00 01 11 10

0 0 0 1 1

1 1 0 0 1

JK

Excitation

Table

Q Q+ J K

0 0 0 X0 1 1 X

1 0 X 1

1 1 X 0

State transition

diagram

0

1

0X

1X

X0

X1

Characteristic equation:

Q

+

= JQ + KQ

T fli fl


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T flip-flop

Q

characteristics

table

Q T Q+

0 0 0

0 1 1

1 0 1

1 1 0

0 1

0 0 1

1 1 0

T

State transition

diagram

Excitation

Table

Q Q+ T

0 0 0

0 1 1

1 1 0

1 0 1

Characteristic equation

Q+= TQ + TQ = T Q

0

1

0

1

0

1

Some common terms


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Some common terms

Characteristics tablea table thatdefines the next state as a function of

present state and inputs

Characteristic equation- a equation that specifies the next-state after a

clock pulse of the flip-flop as a function of the present states and inputs

before the clock pulse

Excitation table - the input value(s) required to obtain each possible nextstate value after the clock pulse, given the present state value before theclock pulse

Summary of flip flop excitation tables


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Summary of flip-flop excitation tables

Example 1: Design of a 3 bit up-down


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Example 1: Design of a 3 bit up-down

synchronous counter

1. State diagram

2. State table

The up-down selection by

the user is represented by a

variable Y

Present state Next stateY = 0 Y = 1

Q2 Q1 Q0 Q2+ Q1

+ Q0+ Q2

+ Q1+ Q0

+

0 0 0 1 1 1 0 0 1

0 0 1 0 0 0 0 1 0

0 1 0 0 0 1 0 1 1

0 1 1 0 1 0 1 0 0

1 0 0 0 1 1 1 0 1

1 0 1 1 0 0 1 1 0

1 1 0 1 0 1 1 1 1

1 1 1 1 1 0 0 0 0

Please change input X Y in Example 1a and 1b for consistency


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Example 1a: Design of a 3 bit up-down

sync. counter using J-K FF cont ...

3. Excitation table of a J-K flip-flop

Excitation Table

Q Q+ J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0



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Example 1a: Design of a 3 bit up down

synchronous counter using J-K FF cont ..

Present state Next state Flip-flop inputsY = 0 Y = 1 Y = 0 Y = 1

Q2 Q1 Q0 Q2+ Q1

+ Q0+ Q2

+ Q1+ Q0

+ J2K2J1K1J0K0 J2K2J1K1J0K0

0 0 0 1 1 1 0 0 1 1X1X1X 0X0X1X

0 0 1 0 0 0 0 1 0 0X0XX1 0X1XX1

0 1 0 0 0 1 0 1 1 0XX11X 0XX01X

0 1 1 0 1 0 1 0 0 0XX0X1 1XX1X1

1 0 0 0 1 1 1 0 1 X11X1X X00X1X

1 0 1 1 0 0 1 1 0 X00XX1 X01XX1

1 1 0 1 0 1 1 1 1 X0X11X X0X01X

1 1 1 1 1 0 0 0 0 X0X0X1 X1X1X1

4. State table for a 3-bit up-down synchronous counter with J-K flip-flops



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synchronous counter using J-K FF cont ...

00 01 11 10

00 1 0 1 0

01 X X X X

11 X X X X

10 1 0 1 0

00 01 11 10

00 1 1 X X

01 1 1 X X

11 1 1 X X

10 1 1 X X

00 01 11 10

00 X X X X

01 1 0 1 0

11 1 0 1 0

10 X X X X

4. Karnaugh maps implementation to obtain the flip-flop input equations

00 01 11 10

00 X X 1 1

01 X X 1 1

11 X X 1 1

10 X X 1 1

00 01 11 10

00 1 0 0 0

01 0 0 1 0

11 X X X X

10 X X X X

00 01 11 10

00 X X X X

01 X X X X

11 0 0 1 0

10 1 0 0 0

Q0

YQ2Q1

J2= Q0Q1Y + Q0Q1Y

K2= Q0Q1Y + Q0Q1Y

J1= Q0Y + Q0Y

K1= Q0Y + Q0Y

J0= 1

K0= 1

Q0Y

Q2Q1

Q0Y

Q2Q1

Q0Y

Q2Q1

Q0YQ2Q1

Q0YQ2Q1



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synchronous counter using J-K FF cont ...

6. Counter implementation

5. Flip-flop input equations

FF2 FF1 FF0

J2= K2= Q0Q1Y + Q0Q1Y J1= K1= Q0Y + Q0Y J0= K0= 1

Example 1b: Design of a 3 bit up-down


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Example 1b: Design of a 3 bit up down

synchronous counter using T FF cont ...

3. Excitationtable of aT flip-flop

Excitation

Table

Q Q+ T

0 0 0

0 1 1

1 1 0

1 0 1



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synchronous counter using T FF cont ...Present state Next state Flip-flop inputs

Y = 0 Y = 1 Y = 0 Y = 1

Q2 Q1 Q0 Q2+ Q1

+ Q0+ Q2

+ Q1+ Q0

+ T2 T1

T0 T2

T1 T0

0 0 0 1 1 1 0 0 1 1 1 1 0 0 1

0 0 1 0 0 0 0 1 0 0 0 1 0 1 1

0 1 0 0 0 1 0 1 1 0 1 1 0 0 1

0 1 1 0 1 0 1 0 0 0 0 1 1 1 1

1 0 0 0 1 1 1 0 1 1 1 1 0 0 1

1 0 1 1 0 0 1 1 0 0 0 1 0 1 11 1 0 1 0 1 1 1 1 0 1 1 0 0 1

1 1 1 1 1 0 0 0 0 0 0 1 1 1 1

4. State table of 3-bit up-down synchronous counter with T flip-flop



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synchronous counter using T FF cont ...

00 01 11 10

00 1 1 1 1

01 1 1 1 1

11 1 1 1 1

10 1 1 1 1

00 01 11 10

00 1 0 1 0

01 1 0 1 0

11 1 0 1 0

10 1 0 1 0

00 01 11 10

00 1 0 0 0

01 0 0 1 0

11 0 0 1 0

10 1 0 0 0

T0= 1 T1= Q0Y+ Q0Y

Q0YQ

2Q

1

Q0Y

Q2Q1

Q0Y

2Q1

T2= Q0Q1Y+ Q0Q1Y

74HC190 up-down counter


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74HC190 up-down counter Logic diagram for the 74HC190, an up/down synchronous decade counter.

The direction of the count is determined by the level of the up/down input.

When this input is HIGH, the counter counts down; when it is LOW, thecounter counts up.

This device can be preset to any desired BCD digit as determined by thestates of the data inputs when theLOAD input is LOW.

TheMAX/MIN output produces a HIGH pulse when the terminal count nine(1001) is reached in the UP mode or when the terminal count zero (0000) is

reached in the DOWN mode. TheMAX/MIN output, the ripple clock output , and the count enable input

are used when cascading counters.



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Binary and gray code representation


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Binary and gray code representation

Gray code

Gray code is an unweighted code

that has a single bit change between

one code word and the next in a

sequence. Gray code is used to

avoid problems in systems where an

error can occur if more than one bit

changes at a time.

0

12

3

4

5

67

8

9

10

11

12

13

14

15

0000

00010010

0011

0100

0101

01100111

1000

1001

1010

1011

1100

1101

1110

1111

Decimal Binary Gray code

0000

00010011

0010

0110

0111

01010100

1100

1101

1111

1110

1010

1011

1001

1000

Newly added

Example 2: Design of a 3 bit synchronous


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Gray code counter Gray codea binary numeral system where two successive values differ

in only one bit. Design procedures:

1. State diagram

Present state Next state

Q2 Q1 Q0 Q2+ Q1

+ Q0+

0 0 0 0 0 10 0 1 0 1 1

0 1 1 0 1 0

0 1 0 1 1 0

1 1 0 1 1 1

1 1 1 1 0 1

1 0 1 1 0 0

1 0 0 0 0 0

2. State table



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Gray code counter using J-K FF cont

3. Excitationtable of a J-Kflip flop

Present

state

Next state Flip-flop inputs

Q2 Q1 Q0 Q2+ Q1

+ Q0+ J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 1 0 X 1 X X 0

0 1 1 0 1 0 0 X X 0 X 1

0 1 0 1 1 0 1 X X 0 0 X1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 1 X 0 X 1 X 0

1 0 1 1 0 0 X 0 0 X X 1

1 0 0 0 0 0 X 1 0 X 0 X

4. State table of 3-bit Gray code counter with J-Kflip-flops

Excitation

Table

Q Q+ J K0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0



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5. Karnaugh maps to obtain the flip-flop input equations



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p e : es g o 3 b sy c o ous



5. Flip-flop input equations

FF2 FF1 FF0

J0= Q

2Q

1 + Q

2Q

1J1= Q

2Q

0J2= Q

1Q

0

K0= Q

2Q

1+ Q

2Q

1 K

1= Q

2Q

0 K

2= Q

1Q

0

Unused states


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In all the previous examples, all the three / four bit combinations wereused in the state assignment.

Withpbits, the number of states,s, that can be coded is 2p-1


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p g y

sequence binary counter

000

001

010

100

101

110

1. State diagram

Present state Next-stateQA QB QC QA

+ QB+ QC

+

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 00 1 1 X X X

1 1 1 X X X

2. Next-state table

dont cares

There are two unused states

i.e. 011 and 111

Example 3: Design of a 3 bit arbitrary


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p g y

sequence counter

Present state Next-state Flip-flop inputs

QA QB QC QA+ QB

+ QC+ DA

DB DC

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 0

0 1 0 1 0 0 1 0 0

1 0 0 1 0 1 1 0 1

1 0 1 1 1 0 1 1 01 1 0 0 0 0 0 0 0

0 1 1 X X X X X X

1 1 1 X X X X X X

4. State table of 3-bit arbitrary sequence counter

with D flip-flops

3. Excitationtable of a

D flip-flop

The input values of

D flip-flops are the

same as the next-

state values

Excitation

Table

Q Q+ D

0 0 00 1 1

1 0 0

1 1 1



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p g y

sequence counter using D FF cont

00 01 11 100 0 1 0 1

1 0 X X 1

00 01 11 10

0 1 0 0 1

1 0 X X 0

00 01 11 10

0 0 0 0 0

1 1 X X 1

QC

QAQB

DA+

= QAQB+ QAQB

QCQAQB

DB

+

=

QC

QC

QAQB

DC+= QBQC

5. Counter implementation4. Karnaugh maps

Verify output for unused states


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Verify output for unused states

2. Put the counter in the

unused state; then determine




state:

4. Set up the next


the current output.

1. Determine

the flip-flop

input equations

Outputs Flip-flop inputs Next state

QA QB QC DA =

QAQB+QAQB

DB =

QC

DC =

QBQC

QA+ QB

+ QC+

0 1 1 1 1 0 1 1 0

1 1 1 0 1 0 0 1 0

The next state is the same as the flip flop inputs for D flip-

flops

Newly added



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p g y

sequence counter using D FF cont

An analysis shows that if the counter, by accident, gets into one of the

invalid states (011 or 111), it will always return to a valid state according tothe following sequences: (011 110) and (111 010)

A complete state diagram of the arbitrary sequence counter including the

unused states are shown below

Example 3b: Design of a 3 bit arbitrary


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p g y

sequence counter

000

001

010

100

101

110

1. State diagram

Present state Next-state

QA QB QC QA+ QB

+ QC+

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 1 0 01 0 0 1 0 1

1 0 1 1 1 0

1 1 0 0 0 0

0 1 1 0 0 0

1 1 1 0 0 0

2. Next-state table

There are two unused states

i.e. 011 and 111

Initialize the unused states with 000 state

Modulus of a counter


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modulus of a counternumber of unique statesthrough which the counterwill sequence

maximum modulusthe maximum possible of statesof a counter is 2n,where nis the number of flip-flops in the counter

truncated sequencethe number of stateswith a sequence less than themaximum of 2n

decade countera counter with ten statesin their sequence (MOD10). Acommon modulus for counters

binary coded decimal (BCD) decade countera decade counter with a count

sequence of zero (0000) through (1001). The ten-state sequence produce theBDC code

to obtain a truncated sequence, it is necessary to force the counter to recyclebefore going through all its possible states (e.g. a BCD counter must recycleback to 0000 after 1001 state)

Example 4a: Design of a modulus 6


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p g

(MOD6) counter using T FF000

001

010

011

100

101

Present state Next-state

QA QB QC QA+ QB

+ QC+

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 10 1 1 1 0 0

1 0 0 1 0 1

1 0 1 0 0 0

1 1 0 X X X1 1 1 X X X

1. State diagram

2. Next-state table

Dont cares (X)

The counter only uses SIX (6) out

of the EIGHT (8) available states.

States 110 and 111 are not used in

the design



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(MOD6) counter using T FF cont


QA QB QC QA+ QB

+ QC+ TA TB TC

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 0 0 0 1 0 1

1 1 0 X X X X X X

1 1 1 X X X X X X

4. State table of a modulus 6 counter with T flip-flop3. Excitationtable of aT flip-flop

Excitation

Table

Q Q+ T

0 0 0

0 1 1

1 1 0

1 0 1



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p g

(MOD6) counter using T FF cont 5. Karnaugh maps

6. Counter implementation If the counter gets into one of the invalid states(110 or 111), it will always return to a valid

state according to the following sequences: (110

111010)

00 01 11 10

0 0 0 X 0

1 0 1 X 1

QC

QAQB

TA

+

=

QA

QC

+ QB

QC

00 01 11 10

0 0 0 X 0

1 1 1 X 0

QC

QAQB

TB+

= QAQC

00 01 11 10

0 1 1 X 1

1 1 1 X 1

QC

QAQB

TC

+

=

1

Example 4b: Design of a modulus 6


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p g

(MOD6) counter using D FF cont


QA QB QC QA+ QB

+ QC+ DA DB DC

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 0

0 1 0 0 1 1 0 1 1

0 1 1 1 0 0 1 0 0

1 0 0 1 0 1 1 0 1

1 0 1 0 0 0 0 0 0

1 1 0 X X X X X X

1 1 1 X X X X X X

4. State table of a modulus 6 counter using D flip-flop3. Excitationtable of a

D flip-flop

Excitation

Table

Q Q+ D

0 0 0

0 1 1

1 0 0

1 1 1

Example 4b: Design of a modulus 6


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p g

(MOD6) counter using D FF cont


5. Karnaugh maps

If the counter gets into one of the invalid

states (110 or 111), it will always return to

a valid state according to the following

sequences: (110111100)

00 01 11 10

0 0 0 X 1

1 0 1 X 0

QC

QAQB

DA+

= QAQC+ QBQC

00 01 11 10

0 0 1 X 0

1 1 0 X 0

QC

QAQB

DB+

= QAQBQC + QBQC

00 01 11 10

0 1 1 X 1

1 0 0 X 0

QC

DC+

= QC

QAQB

Synchronous binary counter cont


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y y An example of a 4 bit binary counter using

J-K flip-flops with a count enable input.

The first stage of A1has its J = K = 1 if thecounter is enabled.

The other J and K inputs are equal to 1 ifall previous lower-order bits are equal to 1

and the count is enabled.

The chain of AND gates generate therequired logic for the J and K inputs ineach stage.

The counter can be extended to anynumber of stages, with each stage havingan additional flip-flop and an AND gatethat gives an output 1 if all previous flip-flops outputs are 1.

Synchronous binary counter cont


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y y An example of a 4 bit binary counter using D flip-flops with a count enable

input. Equivalent circuit

Newly added red dashed box to show the circuit is equivalent

Binary counter with parallel load


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y p

Parallel loads for transferring an

initial binary number into the

counter prior to the countoperation.

An example of a binary counter

using J-K flip-flops with parallel

loads and the corresponding truth

table is given.

Load

Count

Count terminal

(CT)

I0

I1

I2

I3

Q0

Q1

Q2

Q3

CLK

Clear

There was an error in the previous slide

Timing Diagram


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g g

Newly added

MOD 6 counter implementation using


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MOD 6 counter implementation using

the binary counter with parallel load

Both counter counts from 0000 to 0110.

Clear input (asynchronous input) - 0110Load input (synchronous input) - 0101

Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Newly added

Binary counter with parallel load


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This is another example of abinary counter using D flip-flops with parallel loads but

without an asynchronous clearinput

Ignore this slide

Asynchronous cascading


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An example of a 2-bit and a 3-bit ripple counter connected in cascade. The

final output of the modulus-8 counter, Q4, occurs once for every 32 input

clock pulses. The overall modulus of the two cascaded counters is 4 8 =

32; that is, they act as a divide-by-32 counter.

Cascade: arrange (a

number of devices or

objects) in a series or

sequence

Synchronous cascadingh i l ( ) f i d h bl


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The terminal count (TC) output of counter 1 is connected to the count enable

(CTEN) input of counter 2.

TCoutput of counter 1 goes HIGH when counter 1 completed the entire cycle (when

counter 1 reaches its terminal count). This HIGH enables counter 2 that goes from its initial state to its 2ndstate.

Upon completion of the entire second cycle of counter 1 (when counter 1 reaches

terminal count the second time), counter 2 is again enabled and advances to its next

state. This sequence continues.

Since these are decade counters, counter 1 must go through ten complete cyclesbefore counter 2 completes its first cycle i.e., for every ten cycles of counter 1,

counter 2 goes through one cycle.

Thus, counter 2 will complete one cycle after one hundred clock pulses.

The overall modulus of these two cascaded counters is 10 10 = 100.

Synchronous cascading as frequency


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Cascaded counters are often used to divide a high-frequency clock signal to

obtain highly accurate pulse frequencies. Known as countdown chains.

A basic clock frequency of 1 MHz signal is divided by 10, the output is 100

kHz. Then if the 100 kHz signal is divided by 10, the output is 10 kHz.

Another division by 10 produces the 1 kHz frequency. The generalimplementation of this countdown chain is shown below

divider

Cascaded counters with truncated sequences


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a divide-by-40,000 counter (modulus 40,000) counter

The cascaded counter is preset to 25,536 (63C0 in hexadecimal) so that itwill count from 25,536 up to 65,535 on each cycle (40,000 states).

TheRCO output of the right-most counter is inverted and applied to theinput of each 4-bit counter.

Each time the count reaches its terminal value of 65,535, which is1111111111111111,RCO goes HIGH and causes the number on the paralleldata inputs (63C016) to be synchronously loaded into the counter with the

clock pulse. With this technique any modulus can be achieved by synchronous loading of

the counter to the appropriate initial state on each cycle.

Counter decoding


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To decode a binary state 6 (110) of a 3-bit binary counter, the outputs of Q2,

Q1, and Q0 are connected to the input of a AND gate.

A HIGH appears on the output of the decoding gate, indicating that thecounter is at state 6. This is called active-HIGH decoding.

Replacing the AND gate with a NAND gate provides active-LOW decoding.

Question: How do you connect the circuit to decode a binary state 5 and 0?

Counter applications


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Digital clock

Automobile parking

Parallel-to-Serial Data Conversion (Multiplexing)

Digital clock


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Digital clock cont


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g An example of a simplified logic diagram of a digital clock that displays

seconds, minutes, and hours.

A 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform anddivided down to a 1 Hz pulse waveform by a divide-by-60 counter.

The divide-by-60 counter is formed by a divide-by-10 counter followed by a

divide-by-6 counter.

Theseconds and minutes counts are also produced by divide-by-60 counters

Digital clock cont


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A divide-by-60 counter

The counter counts from 0 to 59 and then recycle to 0

The divide-by-10 portion is formed with a synchronous decade counter The divide-by-6 portion is formed with a decade counter with a truncatedsequence achieved by using the decoder count 6 to asynchronously clear thecounter.

The terminal count, 59, is also decoded to enable the next counter in thechain.

**Q0= LSB**Q3= MSB

Digital clock cont Th h t i f d ith


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The hours counter is formed with adecade counter and a flip-flop.

The decade counter advancesthrough all of its states from 09

On a clock pulse that recycles thecounter from 9 back to 0, the flip-flop goes to the SET state (J = 1,K= 0) and illuminates a 1 on thetens-of-hours display.

The total count is ten (the decadecounter is in the zero state and the

flip-flop is SET).

When the total hour count advancesto 12, the Q2output of the decadecounter is HIGH, the flip-flop isstill SET, and thus the decode-12gate output is LOW.

This activates the LOAD input of thedecade counter. On the next clock

pulse, the decade counter is preset to0001 from the data inputs, and theflip-flop is RESET (J = 0,K =1).This logic always causes the counterto recycle from 12 back to 1.

Automobile parking


87/90

The use of an up/down counter to monitor the available spaces in a one-

hundred space parking garage and provide for an indication of a full

condition by illuminating a display sign and lowering a gate bar at the

entrance.

The system consists of optoelectronic sensors at the entrance and exit of the

garage, an up/down counter and associated circuitry, and an interface circuit

that uses the counter output to turn the FULL sign on or off as required and

lower or raise the gate bar at the entrance.

Optoelectronic sensors

Up/down counter

Automobile parking cont


88/90

The up/down counteris initially preset to 0 using the parallel data inputs

Each automobile entering the garage activates a light sensor that produces anelectrical pulse (positive pulse).

This electrical pulse SETs the S-R latch. The LOW on the output of the latch putsthe counter in the UP mode. Also, the electrical pulse goes through the NOR gateand clocks the counter on the LOW-to-HIGH transitioncounter is increased by 1

When the one-hundredth automobile enters, the counter goes to its last state (10010).TheMAX/MIN output goes HIGH and activates the interface circuit which lights theFULL sign and lowers the gate bar.

When an automobile exits, the optoelectronic sensor produces a positive pulse,which RESETs the S-R latch and puts the counter in the DOWN mode counter isdecreased by 1

If the garage is full and an automobile leaves, theMAX/MIN output of the countergoes LOW, turning off the FULL sign and raising the gate.

Multiplexerl i l i i f h ll l d bi i l d bi h


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Multiplexingconversion of the parallel data bits to serial data bits on thesingle transmission line.

parallel data - a group of bits appearing simultaneously on parallel lines

serial data - a group of bits appearing on a single line in a time sequence Parallel-to-serial conversion is generally accomplished using a counter to

provide a binary sequence for the data-select inputs of a dataselector/multiplexer.

An example of the Q outputs of the modulus-8 counter connected to the

data-select inputs of an 8-bit multiplexer.

Multiplexer cont


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2013 wwk6 counter 1 (design of counters)_portal_vg3

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