264 ieee transactions on reliability, vol. 67, no. 1...

264 IEEE TRANSACTIONS ON RELIABILITY, VOL. 67, NO. 1, MARCH 2018

Fast Built-In Redundancy Analysis Basedon Sequential Spare Line Allocation

Hayoung Lee, Jooyoung Kim, Keewon Cho, and Sungho Kang , Senior Member, IEEE

Abstract—Built-in redundancy analysis (BIRA) is widely usedfor memory yield improvement. However, increases in fault occur-rence probability inevitably lead to the use of various spare lines toachieve a high repair rate. Generally, it is difficult to apply conven-tional BIRAs for memories with various spare lines because theyfocus on a simple spare structure. Therefore, this study examines aBIRA that focuses on a various spare lines structure. The proposedBIRA achieves a high repair rate through the use of various sparelines. Although long analysis time is typically required due to theuse of various spare lines, the proposed BIRA solves the problemthrough sequential spare line allocation. Additionally, it achieveshardware overhead reduction through a simple analyzer. These ad-vantages of the proposed BIRA are demonstrated experimentally.

Index Terms—Analysis speed, built-in redundancy analysis(BIRA), hardware overhead, memory repair, repair rate, spareallocation, various spare lines.

ACRONYMS AND ABBREVIATIONS

SoC System-on-chip.BIRA Built-in redundancy analysis.BIST Built-in self-test.CRESTA Comprehensive real-time exhaustive search test and

analysis.LRM Local repair-most.ESP Essential spare pivoting.RM Repair-most.ATE Automatic test equipment.IS Intelligent solve.ISF Intelligent solve first.SFCC Selected fail count comparison.CAM Content addressable memory.

NOTATIONS

Rs Number of row-direction spare lines.Cs Number of column-direction spare lines.

Manuscript received May 23, 2017; revised September 15, 2017 and October11, 2017; accepted November 24, 2017. Date of publication January 9, 2018;date of current version March 1, 2018. This research was supported by theMOTIE (Ministry of Trade, Industry & Energy (10052875) and KSRC(KoreaSemiconductor Research Consortium) support program for the development ofthe future semiconductor device. Associate Editor: W.-T. Chien. (Correspondingauthor: Sungho Kang.)

H. Lee, K. Cho, and S. Kang are with the Computer Systems ReliableSOC Laboratory, Department of Electrical and Electronic Engineering, YonseiUniversity, Seoul 120-749, South Korea (e-mail: [email protected];[email protected]; [email protected]).

J. Kim is with the Memory system r&d group, SK Hynix, Inc., Icheon 467-701, South Korea (e-mail: [email protected]).

Digital Object Identifier 10.1109/TR.2017.2778301

I. INTRODUCTION

A S SYSTEM-ON-CHIPS (SoCs) consist of many embed-ded memories, their yield is directly related to that of

embedded memories. However, an increase in the density andcapacity of memories also increases their fault occurrence prob-ability, which causes yield degradation. Hence, a methodologythat replaces faulty cells by using incorporated redundancies inmemories is widely used to improve memory yield. The method-ology is usually implemented as built-in redundancy analysis(BIRA). Generally, BIRA is inserted in memories with a built-inself-test (BIST) to proceed to memory test and repair operations.BIST sends test patterns to the memories, and then receives thetest results. If, through the analysis of test results, BIST detectsthe existence of faults on memories, it sends fault addressesto BIRA. Subsequently, BIRA analyzes the fault addresses todetermine memory repair solutions.

There are three key features in BIRA implementation: repairrate, analysis time, and hardware overhead. A reduction in re-pair rate significantly influences the production of commoditymemories. As repair rate represents a detection probability ofmemory repair solutions, it is defined as the number of repairedmemories divided by the number of tested memories [1]. Anal-ysis time is defined as the total time required to search memoryrepair solutions. It is important because the total test cost signif-icantly increases with the analysis time. Analysis time typicallydepends on the number of faults, the number of spare lines orspare line types, size of memories, and a redundancy analysis(RA) algorithm. Hardware overhead is crucial for BIRA im-plementation in SoCs. If hardware overhead is not suitable forinsertion, then BIRA cannot be used to repair memories. How-ever, a tradeoff exists among the key features; and thus, BIRAshould be designed to obtain the best performance among them.

Several previous studies on BIRA have focused on improvingits key features. Comprehensive real-time exhaustive search testand analysis (CRESTA) [2] was the first BIRA. The total num-ber of cases of incorporated redundancy allocation on memoryfaults can be considered when fault analysis for memory repairproceeds using several subanalyzers. This means that CRESTAcan definitely find at least one solution if the tested memory canbe repaired using incorporated redundancies; thus, it can achievea high repair rate. Furthermore, since many subanalyzers simul-taneously search for memory repair solutions, it requires a lowanalysis time to search for memory repair solutions. However,because the number of subanalyzers for implementing CRESTAis larger than the number of spare lines, it is impossible to applyCRESTA due to a large hardware overhead. Conversely, local

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LEE et al.: FAST BUILT-IN REDUNDANCY ANALYSIS BASED ON SEQUENTIAL SPARE LINE ALLOCATION 265

repair-most (LRM) and essential spare pivoting (ESP) [1] focuson hardware overhead reduction with a low analysis time. LRMwas proposed to implement repair-most (RM) [3] as BIRA. RMcorresponds to an RA algorithm that uses automatic test equip-ment (ATE) to determine memory repair solutions. It requiresa short analysis time for memory repair because of the use of avery simple algorithm. However, it cannot be applied as BIRAbecause of a large hardware overhead caused by its use of a largefailure bitmap in ATE to determine memory repair solutions. Forthis reason, LRM uses a small failure bitmap for application asBIRA. This allows LRM to proceed to the fault analysis witha short analysis time (similar to RM) as BIRA. However, therepair rate of LRM is lower than that of RM and is significantlyinfluenced by the size of the failure bitmap. ESP achieves asmall hardware overhead with a high analysis speed since ituses registers for repair analysis instead of a failure bitmap.It stores fault information by classification into pivot and non-pivot faults. This results in efficient spare allocation with a highanalysis speed. However, ESP exhibits a low repair rate. Intel-ligent solve (IS) and intelligent solve first (ISF) [4] have beenproposed to achieve a high repair rate. IS searches all spareallocation cases by constructing a binary search tree; hence, ifthe memories can be repaired using incorporated redundancies,then IS can definitely repair memories with incorporated redun-dancies. However, it searches all spare allocation cases and usesback-tracking after constructing a binary search tree to deter-mine memory repair solutions; thus, it requires a long analysistime. Although ISF was proposed to reduce the analysis time bygiving up an optimal repair solution of a memory, it still requiresa long analysis time. Furthermore, as it needs a large hardwareoverhead, it is not easily applied as BIRA. To overcome theissues of long analysis time and large hardware overhead, theselected fail count comparison (SFCC) [5] and BRANCH [6]have been proposed. These approaches can repair memorieswith incorporated redundancies if the memories are repairedusing incorporated redundancies, similarly to IS and ISF. How-ever, the aforementioned BIRA improved on the long analysistime and large hardware overhead problems of IS and ISF. First,SFCC and BRANCH use a similar fault-restoring content ad-dressable memory (CAM), which results from improvements inthe fault-restoring method of ESP. However, a difference existsbetween the fault analyzers. SFCC uses a line-based search treeand results in faster fault analysis when compared to IS andISF because the number of spare allocation cases consideredby SFCC is lower than those considered by IS and ISF, due tothe existence of a line-based search tree. Conversely, BRANCHresults in further improvement in analysis time when comparedto SFCC. In addition, BRANCH results in a short analysis timeowing to the use of combinational logic as a fault analysis. How-ever, neither SFCC nor BRANCH can be applied to memorieswith the various spare lines structure for improving the repairrate, because they focus on memories with a simple spare struc-ture. As a result, previous studies have proposed several BIRAapproaches based on a simple spare structure [7]–[9]; however,there is no improvement in repair rate because these cannot beapplied to memories with the various spare lines structure forachieving a high repair rate.

Repair rate improvement is recognized with increases inmemory capacity and density. Therefore, a few studies havefocused on modifying the spare structure to improve the repairrate. A built-in repair scheme based on configurable spares [10]uses a flexible spare structure that configures the same spare to arow spare, a column spare, or a rectangle to fit the failure patternfor memory repair. A flexible spare possesses the same size asthat of a row spare or a column spare in a simple spare struc-ture, although it uses a flexible spare to achieve a higher repairrate than that of the cases using a row spare or a column spare.This is because a flexible spare can be used as various sparetypes based on fault distribution. However, its practical appli-cation is extremely difficult because of complexity. A built-inself-repair technique for multiple repairable embedded RAMs[11] is proposed with an applicable spare structure. It dividesrow and column spares in a traditional simple spare structure. Itcauses a slight improvement in the repair rate by using a trade-off with slight routing and control complicity. However, as itonly improves the repair rate, the repair rate improvement isstill low. Therefore, it is necessary to obtain a repair rate ex-ceeding that of conventional BIRAs by improving BIRA withthe diversification of spare line types.

In contrast, the proposed BIRA achieves a high repair rateby considering multiple memories with the various spare linesstructure. Additionally, as the applicability for memory repair isconsidered, three spare line types are selected for the proposedBIRA: a local spare line, a common spare line, and a globalspare line. Hence, the proposed BIRA proceeds to solutionsearch processes by using the aforementioned three spare linetypes. Furthermore, the diversification of spare line types in-duces an increase in the analysis time for the memory solu-tion search processes. However, the proposed BIRA solves theproblem with the sequential spare line allocation method. Thismethod also simplifies the solution search processes and resultsin a low hardware overhead because of the simplification of thefault analysis.

II. BACKGROUND

A. Various Spare Lines Structure

Conventional BIRAs have been proposed with a simple sparestructure composed of a row spare and a column spare. However,it is inefficient to be adopted for yield improvement because therepair rate improvement is limited as each spare in a simplespare structure can only be used for a corresponding memory.In this study, a various spare lines structure is adopted to achievea high repair rate improvement. As shown in Fig. 1, there arethree spare line types in the various spare lines structure: alocal spare line, a common spare line, and a global spare line.Each spare is composed of a row-direction spare and a column-direction spare. The role of a local spare line is exactly the sameas that of the spare line in a simple spare structure; it is used torepair faults in a corresponding adjacent memory. Conversely,a common spare line is used for faults in either of two adjacentmemories. Generally, the use of a common spare line achievesa higher repair rate than that of a local spare line. A global spareline is used to repair the same row or the same column faults


Fig. 1. Example of memories with various spare lines structure.

Fig. 2. Example of fault occurrence on memories.

for several memories. It is useful when faults occur in the sameword line that does not correspond to a rare case. However, acommon spare line and a global spare line entail higher costswhen compared to a local spare line; therefore, the sophisticatedselection of each number of spare lines is necessary to considerthe tradeoff.

B. Classification of Faults

As the proposed BIRA allocates spare lines based on the gen-erated fault types, a classification of faults is helpful in under-standing the proposed BIRA. In this study, faults are classifiedinto a single fault, a local sparse faulty line, a global sparsefaulty line, and a must-repair faulty line. The single fault isdefined as a fault in which there is no other fault on the samerow line or the same column line, as shown in Fig. 2(a). Gen-erally, it is considered at the last for repair because it can berepaired by one spare line irrespective of the spare line types ordirections. The local sparse faulty line corresponds to a groupof faults that consist of more than one fault in the same rowline or the same column line but can be repaired using row orcolumn-direction spares, as shown in Fig. 2(b). For example,the local sparse faulty line shown in Fig. 2(b) can be repairedby one row-direction spare or two column-direction spares. Theglobal sparse faulty line is similar to a local sparse faulty line,with the difference corresponding to the location of the gener-ated faults. Faults of the local spare faulty line are generated onthe same memory, while those of the global sparse faulty line

Fig. 3. Block diagram of entire test and repair system.

Fig. 4. Structure of fault storing CAM.

are generated on different memories. For example, as shown inFig. 2(c), two faults of the global sparse faulty line are located ontwo different memories. Specifically, if a simple spare structureis used for memory repair, then there is no need to separatelyclassify the local and global sparse faulty lines. However, asthe various spare lines structure is used in this study, the clas-sification of sparse faulty lines is important. The local sparsefaulty line can be repaired with the same number of spares irre-spective of the spare type. Nevertheless, the number of sparesfor repairing the global sparse faulty line differs based on thespare types in need of repair. For example, Fig. 2(c) showsthe repair of one global spare line or two local spare lines. Themust-repair faulty line corresponds to a group of faults that canbe repaired by only one-direction spare line. For example, themust-repair faulty line shown in Fig. 2(d) can be repaired byonly one row-direction spare line because the total number ofcolumn spare lines is lower than that of the faults on a row line.In practice, realistic fault locations generate more confusion as


Fig. 5. Example of fault storing processes of fault storing CAM. (a) Generated faults on memories with various spare lines. (b) Storing pivot faults. (c) Storingnonpivot faults included in the local sparse fault line. (d) Generation of must-repair line. (e) Storing a pivot fault and a nonpivot fault. (f) Storing a nonpivot faultincluded in the global sparse fault line. (g) Storing remaining faults.

compared to that shown in Fig. 2 because several sparse faultylines can overlap. Therefore, an efficient spare line allocation isimportant for achieving a high repair rate.

III. PROPOSED IDEA

A. Overview of the Proposed BIRA

A BIRA for memories with the various spare lines structureis proposed in this study. The entire BIRA block diagram withBIST for memory test and repair is shown in Fig. 3. The pro-posed BIRA consists of a fault storing CAM for storing thefault information of memories, a repair analyzer for finding re-pair solutions for memories, and a solution detector for storingthe final memory repair solution. When BIST commences testsequences to determine faults on memories, the fault storingCAM proceeds by collecting the fault information. WheneverBIST detects a memory fault, it sends fault information to BIRAand the fault storing CAM stores the fault information afterassessing the need to save it. If the test sequence of BIST iscompleted, the repair analyzer begins to analyze the fault in-

formation saved in the fault storing CAM to locate a memoryrepair solution. If a memory repair solution is found after an-alyzing the fault information, then it is stored in the solutiondetector.

B. Fault Storing CAM

The fault storing CAM of the proposed BIRA is based onESP and is similar to the fault storing structure of BRANCH.Faults are classified as pivot faults, which correspond to theprincipal components of the spare line allocation, and nonpivotfaults, which correspond to the partial components that share afault address with the pivot fault address. If newly detected faultinformation is inserted into the fault storing CAM, then the con-troller of the fault storing CAM determines whether the newlydetected fault corresponds to the pivot fault. The newly detectedfault is considered to be the pivot fault if it corresponds to thefirst detected fault or does not possess the same row address orcolumn address as faults that are already considered pivot faults.Otherwise, the newly detected fault is considered a nonpivot


Fig. 6. Block diagram of repair analyzer.

Fig. 7. Flowchart of repair analyzer processes.

fault. As faults are classified into two groups, the fault storingCAM consists of two types of CAMs—the pivot fault addressCAM, which stores pivot faults, and the nonpivot fault addressCAM, which stores nonpivot faults—as shown in Fig. 4. How-ever, the components of each CAM are different. Pivot faultsare more important than nonpivot faults in spare line allocation;therefore, compared to nonpivot faults, more pivot fault infor-mation is stored in the pivot fault address CAM. The pivot faultaddress CAM consists of the following five sections: pivot en-able flag, memory fault location, global sparse faulty line, localsparse faulty line, and must-repair flag. When a new pivot fault issaved in the pivot fault address CAM, the pivot enable flag is setto 1 and the row and column addresses are written in the memoryfault location. When a new nonpivot fault is saved in the non-pivot address CAM, the local sparse faulty line of the pivot faultis set to 1 if the nonpivot address is generated in the same mem-ory as that of a pivot fault; otherwise, the global sparse faultyline of the pivot fault is set to 1. This is important for memoryrepair with various spare lines because the use of global sparelines is decided by considering the global sparse faulty line bitin the pivot fault address CAM when spare allocation processes

are progressed. If a new nonpivot fault generates a must-repairfaulty line, then the must-repair flag of the correspondingpivot fault is set to 1 and the new nonpivot fault is not stored.Additionally, a new nonpivot fault is located on the must-repairfaulty line, and the global sparse faulty line or the local sparsefaulty line is updated and other information of the new nonpivotfault is not saved. The nonpivot fault address CAM consists offour sections: a nonpivot enable flag, a pivot fault address CAMpointer, a nonpivot address descriptor, and an address. Whena new nonpivot fault is stored in the nonpivot address CAM,the nonpivot enable flag is set to 1 and the location of the pivotfault in the pivot fault address CAM is written in the pivot faultaddress CAM pointer. There is no need to save a row or columnaddress of the nonpivot fault because the nonpivot fault has thesame row or column address as that of a pivot fault. Thus, thenonpivot fault is saved with just one-direction address, whichneed not be shared with a pivot fault, and the direction of thestored address is written in the nonpivot address descriptor. Thesize of the pivot fault address CAM corresponds to the sum ofrow-direction spare lines (Rs) and column-direction spare lines(Cs). Additionally, the size of the nonpivot fault address CAMis determined by considering a must-repair condition, such asBRANCH, since the incorporated spare lines are simply clas-sified into row- and column-direction spares such that only thedirection of each spare is considered irrespective of the spare linetypes.

Fig. 5 represents an example of the fault storing processesof the proposed BIRA. These processes are progressed tostore the faults shown in Fig. 5(a) in a fault storing CAM.When the first three faults are detected in the proposed BIRA,they are stored in the pivot fault address CAM, as shown inFig. 5(b). This is because there is no fault that has the samerow address or column address in the pivot fault address CAM;therefore, they are judged as a pivot fault. When the fourth faultis inserted, it is stored in the nonpivot fault address CAM, asshown in Fig. 5(c), because there is a fault that has the same rowaddress in the pivot fault address CAM. When it is stored in thenonpivot fault address CAM, the pointer bit is set to 2 becausethe pivot fault of the fourth fault is the third fault in the pivotfault address CAM. In addition, the local sparse bit of the pivotfault is set to 1 because the fourth fault is located on the samememory as the pivot fault. Additionally, as the pivot fault has thesame row address information, only the column address is storedin the nonpivot fault address CAM. Therefore, the descriptor isset to 1 to represent the fact that the saved address is the columnaddress. When the fifth fault is inserted, a must-repair faulty lineis generated because the number of faults on memory row line4 is larger than the number of available column spares; there-fore, it should be repaired by a row spare. For this reason, amust-repair flag is set to 1 for representing a must-repair faultyline and a nonpivot fault located on the must-repair faulty lineis eliminated in the nonpivot fault address CAM, as shown inFig. 5(d). Fig. 5(e) shows the state after the sixth and seventhfaults are stored in each CAM following similar storing rulesas those for the previously stored faults. The eighth fault hasthe same row address as that of the first fault in the pivot faultaddress CAM, but is located on a different memory to the pivot


Fig. 8. Example of spare allocation processes of the proposed repair analyzer. (a) State of fault storing CAM after the end of test sequence. (b) Check of globalsparse faulty line. (c) Global spare line allocation for global sparse faulty lines. (d) Conversion of a nonpivot fault to a pivot fault. (e) Check of local sparse faultyline. (f) Local spare line allocation for local sparse faulty lines. (g) Local spare line allocation for remaining faults. (h) Common spare line allocation for remainingfaults.

fault. Therefore, a global sparse flag is set to 1 and the eighthfault is stored in the nonpivot fault address CAM, as shownin Fig. 5(f). Finally, after the last three faults are inserted andstored, the fault storing processes of the fault storing CAM arecompleted as shown in Fig. 5(g).

C. Repair Analyzer

All faults are stored in the fault storing CAM if the testsequence of BIST is completed. Subsequently, the proposedrepair analyzer proceeds with spare line allocation processes.The repair analyzer consists of five components, as shown inFig. 6. The global spare allocation module, the common spare

allocation module, and the local spare allocation module pro-ceed with each spare line allocation. The role of the nonpivotconverting module involves converting nonpivot faults to pivotfaults when pivot faults with the same row address or columnaddress are allocated by global spare lines, although a nonpivotfault that is not allocated by global spare lines exists. Addi-tionally, an analyzer controller is inserted to control the totalrepair analyzer. Furthermore, it receives fault information fromthe fault storing CAM and sends memory repair solutions to thesolution detector. The flowchart of repair analyzer processes isshown in Fig. 7. Initially, the repair analyzer allocates globalspare lines by considering the global sparse faulty line bitsin the pivot fault address CAM to repair global sparse faulty


lines. The first allocation of the global sparse faulty line byglobal spare lines reduces the used spare lines. If a global spareline is not used for a global sparse faulty line, several otherspare lines are needed to repair the global sparse faulty line.There are two cases that should be considered when the globalspare line allocation proceeds. If the number of available globalspare lines exceeds that of global sparse faulty lines, then allglobal sparse faulty lines are allocated by global spare lines andthe remaining global spare lines are used in the last spare al-location for the remaining faults. In contrast, if the number ofavailable global spare lines is lower than that of global sparsefaulty lines, then global spare lines are allocated by two formu-lae. The first formula involves initially allocating pivot faultswith both row- and column-direction global sparse faulty lines.This aids in the reduction of global sparse faulty lines followingglobal spare line allocation. The second formula holds when aglobal spare line decides the allocation on the pivot fault withboth row- and column-direction global sparse faulty lines; then,a global spare line is allocated on the direction of memory thatincludes the highest number of faults after comparing the num-ber of generated faults in each memory. Following the globalspare line allocation, it is possible to generate faults that arerequired to change the nonpivot to the pivot. For example, ifthe number of global spare lines is lower than that of globalsparse faulty lines, then global sparse faulty lines not allocatedby global spare lines should be allocated by local spare linesor common spare lines for repair. This means that the globalsparse faulty lines not allocated by global spare lines shouldbe changed to several local sparse faulty lines or single faultsin each memory following the global spare line allocation pro-cesses because local spare lines and common spare lines cannotbe used to repair the same row or the same column faults forseveral memories like global spare lines. Additionally, when afault with both row- and column-direction global sparse faultylines is allocated by a global spare line, nonpivot faults can losepivot faults after the global spare line allocation. Therefore, oneof the nonpivot faults should be changed to a pivot fault to berepaired by local spare lines or common spare lines. At the endof the conversion, the local spare line allocation on local sparsefaulty lines proceeds. Subsequently, the local spare line alloca-tion, the common spare line allocation, and the remaining globalspare line allocation sequentially proceed to repair the remain-ing faults. This is because of the allocation range of each spare.As previously mentioned, local spare lines can be used for a cor-responding memory. Furthermore, common spare lines can beused for two corresponding memories. Conversely, global sparelines can be used to repair all memories. Therefore, it is reason-able to initially use local spare lines and finally use the remainingglobal spare lines because this aids in achieving a high repairrate. An example of spare allocation processes of the proposedrepair analyzer is shown in Fig. 8. Fig. 8(a) shows the storedfault information in the fault storing CAM after the test sequenceof BIST. Initially, global sparse faulty lines are checked for theglobal spare line allocation. Although there are three globalsparse faulty lines, a fault with both row- and column-directionglobal sparse faulty lines exists as shown in Fig. 8(b). Therefore,global spare lines are allocated by considering two formulae be-

Fig. 9. Replacement example of the various spare lines structure.

TABLE IREPAIR RATE COMPARISON DEPENDING ON SPARE LINE STRUCTURES

# of faults 3 4 5 6 7 8 9

Simple spare line structure 100 100 99.9 99.7 98.3 97.5 93.7Various spare line structure 100 100 100 100 100 100 100

# of faults 10 11 12 13 14 15 16

Simple spare line structure 88.8 82.6 74.8 65.6 56.2 45.7 36.3Various spare line structure 100 99.7 99.4 98.7 97.4 94.4 90.8

cause there are two global spare lines. Thus, the fault with bothrow- and column-direction global sparse faulty lines is firstconsidered for allocation. When the fault is allocated, a row-direction global spare line is used because the number of faultson the memory located on the right exceeds those on the mem-ory located at the bottom. Subsequently, a global sparse faultyline remains and is allocated by a remaining global spare line,as shown in Fig. 8(c). The global spare allocation is followedby the generation of a nonpivot fault (10, 2) that loses a pivotfault and is converted to a pivot fault, as shown in Fig. 8(d). Thisis followed by consideration of the local sparse faulty line andis allocated by local spare lines, as shown in Fig. 8(e) and (f).Finally, the repair of the remaining fault involves allocating lo-cal spare lines and sequentially allocating common spare lines,as shown in Fig. 8(g) and (h). After the completion of the finalspare allocation, there are no remaining faults on memories andthe memories are repaired.

IV. EXPERIMENTAL RESULTS

As previously mentioned, there are three key features ofBIRA: repair rate, analysis speed, and hardware overhead. Thesefeatures are important for assessing the performance of BIRA.The proposed and conventional BIRAs were designed using Cprogramming to assess their repair rate and analysis speed. Ad-ditionally, the proposed and conventional BIRAs were designedusing Verilog HDL to assess the hardware overhead. In theexperiments, four memories with the various spare lines struc-ture were used, as shown in Fig. 9. Several different spare linestructures were adopted with four memories to ensure accurateexperimental results. Furthermore, various fault distributions[12]–[16] were considered to ensure a fair comparison of perfor-mance. The fault distributions included the Polya–Eggenberger


TABLE IINORMALIZED REPAIR RATE OF THE PROPOSED BIRA ALGORITHM (CASE 1)

Local Common Global # of faults on memories

R C U D L R R C 10 11 12 13 14 15 16 17

1 1 1 1 1 1 1 1 100 100 100 100 99.9 99.7 99.2 96.51 1 1 1 0 0 2 1 100 100 100 100 100 99.0 97.5 91.01 1 0 0 0 0 2 2 100 100 100 100 99.1 98.3 96.5 84.11 1 2 2 1 1 1 0 100 100 100 100 100 99.9 99.6 95.11 1 1 1 2 2 0 1 100 100 100 100 100 100 99.1 96.82 1 1 1 0 0 1 1 100 100 100 100 100 100 97.6 93.81 1 2 2 2 2 0 0 100 100 100 100 100 99.4 94.8 91.12 2 0 0 0 0 1 1 100 100 99.9 99.9 99.8 99.6 98.3 96.9

TABLE IIINORMALIZED REPAIR RATE OF THE PROPOSED BIRA ALGORITHM (CASE 2)

Local Common Global # of faults on memories

R C U D L R R C 13 14 15 16 17 18 19 20

1 1 2 2 2 2 1 1 100 100 99.9 99.9 99.6 98.4 96.4 94.11 1 2 2 1 1 2 1 100 100 99.9 99.7 99.1 98.7 97.2 91.22 1 2 2 0 0 1 1 100 100 100 99.9 98.9 96.0 93.8 92.81 1 2 2 3 3 0 1 100 100 99.9 99.8 99.6 99.6 97.8 92.31 1 1 1 1 1 2 2 100 100 99.9 99.7 99.7 98.0 95.9 91.61 1 1 1 2 2 1 2 100 100 100 99.9 99.6 99.2 99.1 95.01 1 1 1 3 3 0 2 100 100 99.9 99.8 99.7 99.0 96.1 94.42 1 1 1 0 0 2 2 100 100 99.9 99.8 99.5 98.0 96.1 95.1

Fig. 10. Definitions for repair rate experiments of the proposed BIRA.

distribution, which was applied because it is close to a real-istic fault distribution. Each experiment with the same spareline structure and the same number of faults on memories wasperformed 10 000 times.

First, to verify the achievement of a high repair rate when us-ing the various spare lines structure, the repair rate is measuredusing CRESTA. This is because CRESTA can definitely deter-mine a memory repair solution when memories can be repaired,because it searches across all spare allocation cases. Therefore,it is appropriate to compare the repair rate, although it is notpossible to use CRESTA for memory repair in practice becauseof the large hardware overhead. In the experiment, a local spareline is replaced with a common spare line and two local sparelines are replaced with a global spare line, as shown in Fig. 9.This is because the size of a common spare line is similar to thatof a local spare line and the size of a global spare line is similar

to that of two local spare lines. Table I shows the repair ratesobtained using CRESTA with each spare line structure shownin Fig. 9. The experiments proceed by increasing the numberof faults. As shown in Table I, the repair rates with a vari-ous spare line structure are always larger than or equal to thatwith a simple spare line structure. When the number of faultsis low, repair rates with each spare line structure are similar;however, the repair rates with a simple spare line structure startto decrease after five faults. This is because clustered faults canoccur on memories. Since each spare line can be used for only acorresponding memory in a simple spare structure, incorporatedspare lines for repair of other memories cannot be used for amemory that has clustered faults. However, as a various sparelines structure consists of not only a spare line that can be usedfor only a corresponding memory but also spares that can beused for the repair of several memories, the repair rate decreaseproblem of a simple spare line structure can be solved. Besides,if the number of faults on memories increases, the repair rateswith a simple spare line structure greatly decrease, but thosewith a various spare lines structure remain high.

Next, the repair rate of the proposed BIRA algorithm is mea-sured to verify the performance of the proposed BIRA. A totalof 16 various spare lines structures are used to ensure accurateexperimental data. Tables II and III show the normalized repairrate of the proposed BIRA, as compared to CRESTA, for eachspare line structure. In each table, the spare line structures whichwere expressed as the number of spare lines per each spare linetype, indicated on the left side. The local R and the local Crepresent the local row spare line and local column spare line,


TABLE IVANALYSIS TIME COMPARISON BETWEEN THE PROPOSED BIRA AND AN EXHAUSTIVE SEARCH ALGORITHM

Local Common Global Analysis time (Clock cycles)

R C U D L R R C Exhaustive search Multi-BRANCH Proposed BIRA

1 1 1 1 1 1 1 1 8.72E + 10 160 085 761 1 1 1 0 0 2 1 3.11E + 09 159 110 721 1 0 0 0 0 2 2 1.20E + 08 157 367 681 1 2 2 1 1 1 0 3.27E + 11 162 983 801 1 1 1 2 2 0 1 3.27E + 11 163 815 802 1 1 1 0 0 1 1 1.31E + 12 156 612 841 1 2 2 2 2 0 0 1.31E + 12 165 810 842 2 0 0 0 0 1 1 2.50E + 13 154 891 921 1 2 2 2 2 1 1 4.00E + 14 24 138 705 921 1 2 2 1 1 2 1 4.45E + 13 24 116 326 882 1 2 2 0 0 1 1 1.00E + 14 23 820 416 921 1 2 2 3 3 0 1 8.45E + 14 24 102 654 961 1 1 1 1 1 2 2 5.23E + 12 24 039 863 841 1 1 1 2 2 1 2 4.45E + 13 24 083 785 881 1 1 1 3 3 0 2 8.89E + 13 24 076 376 922 1 1 1 0 0 2 2 1.00E + 13 23 704 130 92

respectively, in each block of memory, as shown in Fig. 10. Thecommon U, the common D, the common L, and the commonR represent the positions of common spare lines. The com-mon U represents the common spare line between memory “A”and memory “B,” while the common D represents the commonspare line between memory “C” and memory “D,” as shown inFig. 10. Similarly, the common L and the common R representthe common spare line in the memories. The global R and theglobal C represent the global row spare line and global columnspare line, as shown in Fig. 10. For example, the first spare struc-ture (11111111) in Table II represents the spare structure in Fig.10. The number of spare lines per each spare line type is one.On the other hand, the second spare structure (11110021) inTable II has one more “Global: R” spare line than the firststructure in Table II but, there is no “Common: L” and “Com-mon: R.” Likewise, the third structure (11000022) in Table IIconsists of local spare lines and global spare lines without com-mon spare lines. Each memory has one “Local: R” and one“Local: C.” And there are two “Global: R” and two “Global:C.” The following spare structures in Table II and the sparestructures in Table III also consist of various spare lines likeabove. As shown in Tables II and III, repair rates of the pro-posed BIRA are not markedly lower than those of CRESTA.This indicates that the proposed BIRA with the various sparelines structure can achieve a significantly higher repair ratewhen compared to that of CRESTA with a simple spare linestructure. Therefore, the proposed BIRA is highly appropri-ate for memory repair, which is also verified by analysis timeexperiments.

With respect to the analysis time experiments, an exhaustivesearch using the various spare lines structure is used becausethere is no BIRA that can be applied to memory repair with thevarious spare lines structure. This exhaustive search determinesmemory repair solutions by serially considering all spare lineallocation cases. Hence, an exhaustive search cannot be appliedfor memory repair because a long analysis time is needed forsuch an exhaustive search. Also, multi-BRANCH is designed

with a various spare lines structure for a fair comparison. Multi-BRANCH sequentially searches memory repair solutions foreach memory and finds the combination of each memory repairsolution that satisfies the number of incorporated spare lines.Table IV shows the analysis time of the exhaustive search, multi-BRANCH, and the proposed BIRA. As shown in the table, theanalysis time of the proposed BIRA is significantly lower thanthat of the exhaustive search. Additionally, the analysis timeof the proposed BIRA is lower than that of multi-BRANCH.BRANCH was introduced as a fast BIRA, but even BRANCHneeds a relatively long analysis time with various spare linesstructures for memory repair. Therefore, as the proposed BIRAsolves the long analysis time problem with various spare linesstructures, it is appropriate for memory repair and achieving ahigh repair rate with a short analysis time. Additionally, fromTable IV, it can be considered that analysis time is proportionalto the number of spare lines, regardless of spare line type. Thisis because sequential spare line allocations are progressed in theproposed BIRA; moreover, similar fault information is consid-ered whenever a spare is allocated and each spare is allocatedwith similar allocation rules.

Finally, the hardware overhead of the proposed BIRA is mea-sured to assess applicability. Initially, the hardware overhead ofthe fault storing CAM is easily compared with that of BRANCH.BRANCH possesses a low hardware overhead, although it can-not be applied to memories with the various spare lines structure.The fault storing CAM of the proposed BIRA is similar to thatof BRANCH. A slight difference between the two fault storingCAMs is observed only in the pivot CAM (4-bit × the number ofavailable spares). Therefore, a fault storing CAM also includesa small hardware overhead similar to BRANCH. Subsequently,to verify the low hardware overhead of the repair analyzer,the proposed BIRA hardware module was synthesized usingthe 45 nm NAND gate open-source library for the experiments.The target spare line structure consists of two local spare linesin each memory, four common spare lines, and two global sparelines. Table V shows the hardware overhead of the total pro-


TABLE VHARDWARE OVERHEAD OF THE PROPOSED BIRA

Module name Hardware overhead(Gate count)

Ratio (%)

Fault storingCAM

Pivot fault addressCAM

970 46%

Nonpivot faultaddress CAM

638 30%

Controller andSolution detector

167 8%

Repair analyzer 335 16%Total hardware overhead 2110 100%

posed BIRA as an equivalent NAND gate count and hardwareoverhead ratio. As shown in Table V, the gate count in the repairanalyzer is markedly lower than the sum of the gate count in thefault storing CAM. In other words, the fault storing CAM cor-responds to 84% of the total BIRA and the repair analyzer onlycorresponds to 16% of the total proposed BIRA. This indicatesthat the fault storing CAM dominates the hardware overhead ofthe proposed BIRA. Therefore, it is verified that the proposedBIRA has a small hardware overhead since the fault storingCAM has a low hardware overhead similar to that of BRANCH.

V. CONCLUSION

It is necessary to achieve a high repair rate due to the re-quirements of capacity as well as increases in memory density.Therefore, this study focuses on examining a BIRA with the var-ious spare lines structure. The results indicate that the proposedBIRA achieves a repair rate that exceeds those of conventionalBIRAs with a simple spare structure. Additionally, as sequen-tial spare line allocation is used, the long analysis time problemby which there are many spare allocation cases on memoryfaults is solved. Furthermore, a low fault storing CAM and asimple repair analyzer that is smaller than the low fault storingCAM are used. Therefore, it is reasonable to apply the pro-posed BIRA, which provides a practical solution for memoryrepair.

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Hayoung Lee received the B.S. degree in electrical and electronic engineeringin 2016 from Yonsei University, Seoul, South Korea, where he is currentlyworking toward the combined Ph.D. degree with the subject of memory test andrepair.

His current research interests include built-in self-repair, built-in self-testing,built-in redundancy analysis, redundancy analysis algorithms, reliability, andVLSI design.

Jooyoung Kim received the B.S. degree in electrical and electronic engineeringin 2015 and the M.S. degree in 2017 from Yonsei University, Seoul, SouthKorea. The subject of his M.S. degree is memory test and repair. He is currentlyworking at the Memory system r&d group, SK Hynix, Inc.

Keewon Cho received the B.S. degree in electrical and electronic engineering in2013 from Yonsei University, Seoul, South Korea, where he is currently workingtoward the combined Ph.D. degree with the subject of memory test and repair.

His current research interests include built-in self-repair, built-in self-testing,built-in redundancy analysis, redundancy analysis algorithms, reliability, andVLSI design.

Sungho Kang (M’89–SM’15) received the B.S. degree in control and instru-mentation engineering from Seoul National University, Seoul, South Korea, in1986, and the M.S. and Ph.D. degrees in electrical and computer engineeringfrom the University of Texas at Austin, Austin, TX, USA, in 1988 and 1992,respectively.

He was a Research Scientist with the Schlumberger Laboratory for ComputerScience, Schlumberger, Inc., Austin, and a Senior Staff Engineer with Semicon-ductor Systems Design Technology, Motorola, Inc., Austin. Since 1994, he hasbeen a Professor with the Department of Electrical and Electronic Engineering,Yonsei University, Seoul. His current research interests include VLSI/SOC de-sign and testing, design for testability, design for manufacturability, and faulttolerant computing.

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