2pad digital architecture
DESCRIPTION
2PAD Digital Architecture. Chris Shenton – JBCA - Oct 2009. 2-PAD Simplified System Overview. Multi Channel ADC (Casper Hardware). Digital Beamformer (Casper Hardware). “Back-End” Processing. LNA & Analogue Signal Transport. Multi Channel ADC (Custom). Digital Beamformer - PowerPoint PPT PresentationTRANSCRIPT
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2PAD Digital Architecture
Chris Shenton – JBCA - Oct 2009
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MANSKADS4 - 14th Mar 2008 2
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“Back-End”Processing
2-PAD Simplified System Overview
MultiChannelADC
(Custom)
DigitalBeamformer(Software)
LNA&
AnalogueSignal
Transport
DigitalBeamformer
(CasperHardware)
MultiChannelADC
(CasperHardware)
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2PAD Design Aims (Digital)
• Provide a modular platform for exploration of digital systems architectures for SKA
• All major subsystems implemented successfully– Multi Channel Digitiser… done– Clock Distribution Subsystem… done– Channeliser… multiple options in progress– Beamformer… multiple options done with continued development in progress– Back-end data processing… multiple options in progress– Management Subsystem… done– Infrastructure… done
• System Integration Ongoing
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Digitizer• 3 Main Elements;
• DAQ Board – Dual Channel ADC + FPGA
• Mid-Plane
• Clock Distribution
• Signal Conditioning Module
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ADC Performance• Characterisation of the ADC and DAQ ‘front end’
• Tests carried out using RF signal generator including Signal Conditioning Module in signal path.
• Linearity and S/N figures for the DAQ/SCM combination under development… We need to
understand how much we are degrading the analogue signal ‘quality’ through the digitiser.
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Progress in SKADS
• Digitiser subsystem – implemented and characterised– Work continuing in area of optimised frequency channelization– Bringup of more acquisition channels– Clock subsystem implemented and characterised– Fine grain control of acquisition timing & deskew
• Instrument Management Subsystem implemented and in use. – Supports TCL scripting– Speedup of interface planned
• Data transport using standards based approach– currently XGMII over CX4 (simplification from original Aurora design)– Support for 10GbE via iBOB… Work to implement native Tx Only 10GbE in progress.
• Software beamformer based on IBM Cyclops multi core processor– Hardware not at JBO but still available remotely at IBM location– Not Real Time but still meaningful
• Hardware beamformer & channelizer built using CASPER Hardware (See KZA talk)
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2PAD into PrepSKA• Modular approach allows “plug and play” of alternative implementations…
… we can plug things together…
… and play with it…
• Inherent capability provides ‘room’ for meaningful exploration of RTL structures (essential for ASIC migration)– Channelisation– Beamforming (Casper, Uniboard, COTS, Other)– Non-Imaging processors (Uniboard)– RFI mitigation techniques (Uniboard)– Power Analysis at RTL Level – RTL prototyping
• Continuation of multi core software techniques in collaboration with IBM based on knowledge acquired during SKADS
– Can use 2PAD Digitiser subsystem to acquire high quality data sets for offline processing using software techniques
– Can model quasi-real time behaviour using block data approach
• Interface into eMerlin– Validation of phase transfer activities in AA context.– Understanding of the wider system timing hierarchy
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Summary
• 2PAD Meets (exceeds) its SKADS design aims but is not yet fully integrated.
• Still requires further development to fully exploit the investment – it is at the beginning of its useful life and is not fully developed
• Has the modularity, capacity and flexibility required to develop next generation hardware structures
• Can be extended and improved incrementally while maximising the value of SKADS investment