3d tsv without limits webinar - semi. · pdf file3d tsv without limits webinar 3d integration...

3D TSV Without Limits Webinar

Moderated by Francoise von TrappQueen of 3D

3D InCites

This free Webinar is brought to you by:

European 3D TSV SummitJan 20‐22, 2014 – Grenoble, France

European 3D TSV Summit

• 25 presentations of executives and experts• 2 Panel discussions with audience• Pre‐summit symposium on TSV for MEMS• Exhibition at the heart of the venue• One on one business meeting service• CEA‐LETI 300mm TSV line tour• Cocktails and Networking dinner

3D TSV Without Limits Webinar

3D Integration Drivers and RoadmapEric BeyneProgram Director 3D System Integrationimec

3D Photonics Convergence for Very High Bandwidth Chip to Chip CommunicationHerve RibotHead of 3D IntegrationCEA‐LETI

3D Wafer Level System Integration – Fraunhofer ApproachJurgen WolfDepartment head of HDI WLP /ASSIDFraunhofer‐IZM

ModeratorFrancoise von TrappQueen of 3D3D InCites

3D Integration Drivers and Roadmap

Eric BeyneDirector 3D System Integration program

imec

Key application drivers

Wide I/O memory on SOC

logic

3D‐SOC Analog‐logic partitioned stacks

Multi‐die Memory stack

(with logic I/O circuit )

Eric Beyne – imec 3D System Integration Program

Key application drivers

Wide I/O memory on SOC

logic

3D‐SOC Analog‐logic partitioned stacks

Multi‐die Memory stack

(with logic I/O circuit )

DRAM Logic DRAM Logic I/O

High power devices: 3D integrationusing a Si Interposer

Focus on die‐to‐die or die‐to‐wafer 3D stacking


Via Middle Through‐Si‐Via Process "Via‐middle": fabrication TSV’s after FEOL device fabricationprocessing but before BEOL interconnect.

Si

Si

imec POR process: o 5 µm diameter;o 50 µm deep;o Aspect ratio 10


3D‐ TSV Scaling roadmap

5µm Ø, 50µm deepAR 10:1

POR TSVToday


10µm Ø, 100µm deep,

AR 10:1Ø AR Depth

Reverse scaling for interposer applications

Return toPOR 5x50µm(driven by cost reduction, ability to assemble on thin interposers & active interposer applications)



POR TSVToday


10µm Ø, 100µm deep,

AR 10:1Ø AR Depth

Reverse scaling for interposer applications

Return toPOR 5x50µm(driven by cost reduction, ability to assemble on thin interposers & active interposer applications)



Ø AR Depth

Extended scaling

Integrated inadvanced device nodes

3µm Ø,50µm deepAR 17:1

Ø ARDepth

Scaling for 3D‐ICapplications


POR TSVToday


3D System Integration Technology

FEOL process

BEOL processVia middle TSVFEOL process

BEOL processVia middle TSV



FEOL process



Wafe to carrierBonding

& Wafer thinning

Backside TSV reveal & backside

passivation

Semi‐additive RDL, µbump & Cu pillar

processes


processes

DebondingThin wafer from

carrier



FEOL process



Wafe to carrierBonding

& Wafer thinning

Backside TSV reveal & backside

passivation

3D Stacking(D2D; D2W;

W2W)

3D Stacking(D2D; D2W;

W2W)


processes


processes

3D StackPackaging3D StackPackaging

DebondingThin wafer from

carrier


Wafer thinning (50µm); Backside Passivation and Cu‐nail exposure

53

52

51

50

49

48

470 50 100 150

Si t

hick

ness

(µm

)

Radial position on wafer (mm)

< 2 µm TTV

TSV Cu

BacksidePassivation

TSVliner


Downscaling µbump‐pitch: 20 µm Pitch chip‐to‐chip interconnects

20μm

12.5μm 7.5μm

5μm

5μm

4μm

Cu pad

Cu

SnNi

Cu pad

Cu

Sn10μm

12.5μm 7.5μm


Backside revealed Cu TSV as µbump

20µm5µm

TSV Cu

BacksidePassivation

TSVliner


Direct Cu‐TSV to Cu pad die stacking 20 µm pitch


3D‐SIC Stacking Capabilities

High Bandwidth Interconnect at low power

Main Limitation: Thermal

may require the use of a Si‐interposer solution


Si InterposerTSV

MIM

damascene Cu/oxide 2µm thick Cu

PWR/GND planes + MIM capacitor

TSV: 10 µm Ø, 100 µm deep

Si Interposer Technology


NEXT STEP BEYOND 3D‐SIC STACKING


SOC partitioning in 3D heterogeneous technology nodes: 3D‐SOC

SOC Node N

Digital Logic, SRAM

Analog functionality

I/O drivers



SOC Node N

Digital Logic, SRAM


I/O drivers

Node N+1 • Digital logic takes full advantage of scaling

• Efficient use wafer area



SOC Node N

Digital Logic, SRAM


I/O drivers

Node N+1 • Digital logic takes full advantage of scaling

• Efficient use wafer area

Node N

• Mixed node, heterogeneous technology• Wafer‐to‐Wafer bonding• Cu/dielectric‐Cu/dielectric hybrid bonding


3D System Integration TechnologiesMain Barriers for wider adoption:

Technology readiness : carrier systems, test,...

Availability of wide‐I/O memory die

Cost of ownership: Focus on cost reduction: reduced process complexity, in particular for thinning and 3D stacking and test.


imec at European 3D TSV Summit

• Session 3: COST DRIVERS – CoO IMPROVEMENT FOR HVM

January 21st, 2014 – 2.30pm

Cost analysis 2.5D and 3D System IntegrationEric Beyne, Program Director 3D System Integrationimec

3D and Photonics Convergence for VeryHigh Bandwidth Chip to Chip

CommunicationH. RIBOT‐CEA LETI‐ 18/11/2013

Computer Com Data Com Telecom

Chip to Chip

in SiP

SiP to SiP

On board In rack Interack LAN Access Metro

Core

1cm 10cm 1m 10m 100m 1km 10km 100km

Data transmissions and NetworksElectrical versus Optical & Roadmap for Energy efficiency

OpticalElectrical (Single Mode fiber) Optical(Multi Mode fiber)

$/Gbps cross-over point e/o

HPC requirements

2013 2016 2019

Aggregate BW 80 Pbps 640 Pbps 5.12 Ebps

Energy/bit 75 pJ/bit 11 pJ/bit 1,7pJ/bit

Cost 6 $/GBps 1$/Gbps 0,16 $/Gbps

From M. Zuffada, STm, EDA workshop May 2013

3D effectively reduces power consumption while increasing bandwidth…

2

• TSV’s : Ø 10 μm, AR 8, Pitch 40 μm, Number 1016

• Chip to Chip Cu Pillars : Ø20 μm, Height 20 μm, Pitch 40 μm, Number 1016

• SoC to Substrate Cu Pillars : Ø55 μm, Height 40 μm, Pitch >200 μm, Number 933

Si - Wide I/O Memory

TSV80µm

Si -SoC

Cu Pillar

Wide IO : 4X power reduction

Dutoit et al., VLSI Circuits 2013

Overall contribution of vertical/horizontal interconnections

Courtesy of STM Crolles

first

From G. Parès - Green IT workshop – Leti Days 2013

5

Interconnect copper line BW limitation

From G. Parès - Green IT workshop – Leti Days 2013

Bit rate (Gbps) ≈ 10E7 A/L2 A = 5 μm X 2 μm

≈ 1 Gbps

Energy dissipation E = ½ CV2

C = 2 pF/cm and V = 1V

≈ 2 pJ/b

L = 1 cm

4.5 cm

Large interposer

| 31

Low loss RF transmission lines in Back-End-Of-Line

(BEOL)

RF Cu pillars + die flip-chip

Low loss electrical: High yield, mature technology, via-last or via-middle technology

2nd Level interconnects

3D and vertical interconnection for short distanceInterconnection …and photonics for long distance (>1mm?)

Light source not detailled

Light source or input

PhotonicsTransistors

Integration Scheme of Photonics and Electronics ?

Monolithic integration Very low parasitics

Custom SOI, specific libraries

process co‐integration

Size and cost of photonics

3D integration, chip‐to‐wafer Higher (but reasonable) parasitics

No change in CMOS Front‐End

Separate processes

Chip size doesn’t matter

Transistors

Photonics

| 33

Energy efficiency expectation Passive electrical/photonics Si interposer

| 34

We are not “there” yet…: Photonics becomes interesting for many-core systemPhotonic links still require significant improvement in energy efficiencyOptical functions roadmap: from 10pJ/bit in 2010 to 100 fJ/bit in 2020

Photonic Silicon Interposer withhybridized CMOS chips @ Leti (in progress)

• FEOL optical components: modulators, W guides, PD in SOI substrate• BEOL high band width interconnection with damascene copper technology• Heterogeneous integration CMOS chips flip‐chip stacking with µbumps

technology (+ Laser source)• Assembly on package TSV, back side RDL and solder bumps for vertical

interconnections to substrate From G. Parès - Green IT workshop – Leti Days 2013

| 35

RAMComputing Cores

Si‐Pho. Interposer

Tx/Rx Integr. Rx/Tx

Substrate

photodiode modul

Laser

ThroughSilicon Via

RF Cu pillars

Power Power Power Power

Modulated waveguides Light source

Primary I/OCu pillars

Digital Cu pillars& proximity lines

Thermal Dissipation

Thermal Dissipation

SignalSignal

Thermal control

Conclusion• Increasing needs for data processing stimulates:

– Multi core system architecture (chip size limit) – Increasing number of chip I/Os– Increasing off‐chip BW– Reduction of SOC power consumption

• 2.5D Silicon interposer for HBW computing is limited by horizontal electrical connections over 2‐3 Gbps due to high attenuation in narrow (< 5 µm)/long (> 1 mm) copper lines and high power consumption penalty

• Green IT targets including X50 required improvement in energy efficiency Introduction of photonics in addition to 3D IC and 3D heterogeneous integration

• Further reduction of Photonics functions power consumption is still a MUST to meet The HPC roadmap.

“Application ready” TSV summit: An opportunity for R&D institutes like CEA LETI to explore with industrial partners how 3D/Si Photonics/ MEMS technologies

available NOW, can be leveraged to create PRODUCTS in 2‐3 years timeframe.

| 36

CEA‐LETI at European 3D TSV Summit

• Session 6: APPLICATIONS & PRODUCTSJanuary 22nd, 2014 – 2.30pm

Novel 3D Architectures for Imaging and High Performance Energy Efficient ComputingHerve Ribot, Head of 3DCEA‐LETI

3D Wafer Level System IntegrationFraunhofer Approach

M. Juergen WolfFraunhofer IZM‐ASSID, Germany

Motivation for3D System Integration

PerformanceMultifunctionalityFormfactorCost reduction

Heterogeneous Integration:Driving Forces

Integration densitySignal propagation timePartitioningPower densityMulti Device IntegrationSensor, Transceiver, MPU, GPU, Memory

Mobile CommunicationID cards

APPLICATION

Application Fields

Requires …own technology pathspecific solutionstimelineinfrastructure

Fraunhofer Cluster3D Integration

Design

Technology

AnalyticsSimulation Reliability

3D System Integration: Key Enabling Technologies• 3D SiP Architecture

• Design - electrical, thermal, mechanical (DfT, DfM, DfR)

• TSV Formation (via first, middle, last (from BS)

• Interposer with TSV and multilayer RDL (FS/BS)

• Passive Device Integration

• Interconnect Formation (electrical, optical)

• Thin Wafer Handling

• Temporary and permanent Wafer Bonding

• Assembly & 3D Stack Formation

• Heterogeneous Device Integration (MEMS, sensor)

• Metrology, Analytic

3D Integration @ Fraunhofer

Wolf

Design

Technology



Wolf

Chip‐Package‐Board‐Co‐Design

Cost optimization under consideration of electrical and physical properties and package

Fraunhofer IIS-EAS

Modeling Concepts for Physics‐/Multi‐Physics‐ Analysis

FE model (ANSYS)

+

Modular building blocks

Thermal simulation of entire 3D stack

Thermal behavioral model

Model orderreduction

(Electro-)Thermal system simulation

63

63.2

63.4

63.6

63.8

0.01 0.015 0.02 0.025 0.03 0.035 0.04

t [s]

T [°

C]

t_q1t_q2t_asict_mem1t_mem2

Detailed analysis of individual or critical parts with 3D-FEM analysis

Development of models at higher abstraction levels to handle system complexity

Interfaces between different toolsFraunhofer IiS-EAS

Design

Technology



Fraunhofer IZM-ASSID Core Competencies

Fraunhofer IZM_ASSID

3D Wafer Level System Integration Line

TSV Geometry - Landscape

5 µm

Diameter

10 µm

20 µm

40 µm

250 µm

160 µm

80 µm

10 µm 20 µm 50 µm 100 µm 200 µm 400 µm 700 µm

InterposerActive Devices (BEOL)

Active Circuits (FEOL)

special apps

Depth

Image Sensorstapered TSV

TSV- Formation @ Fraunhofer IZM - ASSID TSV-Etch: DRIE process for 20μm/100μm

(AR5) 10μm/120μm (AR12)and 5μm/60μm+ (AR12+).

TSV-Isolation: thermal oxide or deposition of SA-CVD/ PE-CVD-TEOS liner

Adhesion-/ Barrier-/ Seed Layer: Deposition of metal layer by high ionized PVD and/ or MOCVD, AR12

TSV-Fill: Cu - ECD with „Bottom-up“ fill characteristic TSV-filling up to AR12.

TSV-CMP: Removal of Cu-overburden with stop in oxide liner.

Developoment of improved/ alternate technologies for TSV formation

TSV Via Last Integration

Thin Wafer HandlingTemporary Bonding / De-BondingTechnology:

• UV / Laser

• Thermal slide

• Solvent

• Mechanical peel-off

Challenges:• Process compatibility

• TTV uniformity

• High topology

• Temperature and chemical stability

• Easy de-bonding (room temperature)

• Low / less residues, cleaning

Support Wafer

Support Wafer

TSV-Wafer

TSV-Wafer

Support Wafer

Support Wafer

Support Wafer

Support Wafer

Support Wafer

Support Wafer

K. ZoschkeFraunhofer IZM

Thin Wafer HandlingTemporary Bonding / De-Bonding

Chip Interconnection / Assembly(D2D, D2W, D2IP, IP2P)Technology:

• Solder, IMC, Cu-Cu, Nano-Interconnects

• Bonding (reflow, TC, diffusion)

• Stacking (D2W, D2W, W2W)

• Interconnect structure (Cu, ...)

• (Self assembly)

Challenges:• Low temperature bonding

• Topography, alignment

• Bonding on carrier vs. wafer

• Test, repair, reliability

• Productivity, throughput, yield

Wolf

3D Chip Stack with Cu-TSV

Fraunhofer IZM-ASSID

Interposer Generations - Performance

G1 Interposer TSV, multilayer redistribution (RDL) top/bottem side, w/o 2nd level interconnect

G2 Interposer + integrated passive devicesG3 Interposer + embedded active devices and /or MEMSG4 Interposer + integrated optical & electrical interconnectsG5 Interposer + active cooling (e.g. fluid channels)

Interposer will convert from single carrier substrateto an integrated active multifunctional packaged device

Integrated Interposer Wafer Level Package

Passive Interposerfor Hermetic MEMS Packaging

Fraunhofer IZM

MEMS-Electronic Direct IntegrationAdaption of Processes regarding application

Through silicon/glass vias (TSV/TGV) by dry/wet etching, LASER, sand blasting

Choice of bonding technique

Metallization via PVD, CVD, ECD, conductive pastes

Fraunhofer ENAS

Processes for 3D MEMS-Electronic Integration Development of low-temp processes

Account for material compatibilities (e.g. Cu-based technologies)

Conformal Metallization of HAR-TSVs (low stress, lower process complexity)

220nm 100%

215nm 98%

220nm 100%

CVD-Seed layer (AR=8)

TSV metallization using CVD and ECD

Cu ECD 400 µm deep TSVs

420 µm

80 µm

Cu-CuInterface

Wafer 1 Wafer 2

5 μm

Cu-Cu Thermo compression bonding

Wafer Level Bonding

2 mmWafer Thinning by Grinding, Spin Etch, CMP

AFM/REM afterFine Grinding (Ra=14 nm)

down to 50µm

Wafer Bonding by Reactive Multilayers

Fraunhofer ENAS

Process Readiness for 3D TSVIntegration

Wolf

Design

Technology



• Materials compatibility for 2.5D‐ and 3D‐integration

• Effect of global and local mechanical stress on performance and reliability

• Determination of multi‐scale materials parameters for a database (input for simulation)

• Model validation based on local strain measurements in active devices

• Analytical techniques for process development, process control and quality control

• Physical failure analysisFraunhofer IZFP

Materials and Reliability

Scallops

Advanced in-depth analysis based on FEM simulation: Damage & Fracture Mechanics

Fraunhofer ENAS

Damage propagationcharacterization by FEA

Damage mechanics

max. norm. ERR vs Crack Length

0,00

0,20

0,40

0,60

0,80

1,00

1,20

1,40

0 20 40 60 80 100 120crack length [µm]

norm

. G

margin 51 µm to crack-stop-structure


w/o crack-stop-structure

max. norm. ERR vs Crack Length

0,00

0,20

0,40

0,60

0,80

1,00

1,20

1,40

0 20 40 60 80 100 120crack length [µm]

norm

. G



w/o crack-stop-structure

Fracture mechanics

BEoL3D FE‐model

Assessment of thermo-mechanical risks for

Reliability and Yield of TSV and BEoL structures

Failure analysis at 3D TSV structures: SEM image of FIB cross-section after nano-XCT study

Fraunhofer IZFP

FIB Channeling Contrast

Monitoring of fill material (voids, grain structure, impurities ....)

Both 4 and 5um TSV show Copper is extruded and with de‐lamination at the wall

3D TSV Reliability: “pop-up” – Quantitative Analysis

Cooperation with Lay Wai Kong and Alain Diebold, College of Nanoscale Science and Engineering at the University at Albany/NY, Lay Wai Kong et al., 3D IC Metrology Workshop @ Semicon West 2010

Fraunhofer IZFP

„3D Integration - Key enabling technology “

Presentations contains results from projects of the Fraunhofer Institutes IZM, IIS-EAS, ENAS, IZFP

Design

Technology


www.3D-Integration.fraunhofer.de

Summary

Fraunhofer‐IZM @ European 3D TSV Summit

• Session 5: LATEST TECHNOLOGIES ACHIEVEMENTSJanuary 22nd, 2014 – 8.45am

3D Technology as a Holistic Approach: Quo Vadis?M. Juergen Wolf, head of dept. WLSI, Mgmt. ASSIDFraunhofer IZM

A Word about 3D InCites

• Since 2009, 3D InCites has been the only online resource devoted exclusively to 3D integration technologies.

• A place to learn, share, engage and collaborate with fellow 2.5D and 3D IC enthusiasts.

• Supported by an advisory board of 3D IC technology experts representing R&D, manufacturing, market research, design and test.

• Creator of the 3D InCites Awards

3D InCites Awards 2014

• Established in 2013 to recognize achievements that further the commercialization of 2.5D and 3D IC technologies.

• The 2014 Awards Program will be launched at the European 3D TSV Summit

• Sponsorships are available. Proceeds to benefit:– Frances B Hugle Engineering Scholarship– 3D InCites SEMI High Tech U Scholarship

This free Webinar was brought to you by:

European 3D TSV SummitJan 20‐22, 2014 – Grenoble, France

Event organizer contact:Yann GuillouSEMI Europe Grenoble [email protected]+33 4 38 78 39 71

3d tsv without limits webinar - semi. · pdf file3d tsv without limits webinar 3d integration...

Documents