4 december 2002, itrs 2002 update conference metrology roadmap 2002 update europeulrich mantz...

4 December 2002, ITRS 2002 Update Conference

Metrology RoadmapMetrology Roadmap2002 Update2002 Update

EuropeEurope Ulrich Mantz (Infineon)Ulrich Mantz (Infineon)Alec Reader (Philips Analytical)Alec Reader (Philips Analytical)Mauro Vasconi (ST)Mauro Vasconi (ST)

JapanJapan Masahiko Ikeno (Mitsubishi)Masahiko Ikeno (Mitsubishi)Fumio Mizuno (Meisei University)Fumio Mizuno (Meisei University)Toshihiko Osada (Fujitsu)Toshihiko Osada (Fujitsu)Akira Okamoto (SONY)Akira Okamoto (SONY)Yuichiro Yamazaki (Toshiba)Yuichiro Yamazaki (Toshiba)

KoreaKorea DH Cho (Samsung)DH Cho (Samsung)

Taiwan Taiwan Henry Ma (EPISIL)Henry Ma (EPISIL)

USUS Steve Knight (NIST)Steve Knight (NIST)Alain Diebold (Int. SEMATECH)Alain Diebold (Int. SEMATECH)


Metrology RoadmapMetrology Roadmap2002 Update2002 Update

USUS John AllgairJohn Allgair MotorolaMotorolaAlain Diebold Alain Diebold Int. SEMATECHInt. SEMATECHDrew EvanDrew Evan CEACEADavid Joy David Joy Univ. of TennUniv. of Tenn

Steve Knight Steve Knight NISTNISTKevin MonahanKevin Monahan KLA-TencorKLA-TencorNoel Poduje ADENoel Poduje ADEHeath PoisHeath Pois ThermawaveThermawaveBhanwar Singh Bhanwar Singh AMDAMDAndras Vladar NISTAndras Vladar NIST

SpeakersSpeakersMichael GosteinMichael Gostein Philips AnalyticalPhilips AnalyticalPY HungPY HungInt. SEMATECHInt. SEMATECHTom KellyTom Kelly AmigoAmigoHeath Pois Heath Pois ThermawaveThermawaveBenzi Sender Benzi Sender Applied MaterialsApplied MaterialsProf. Fred TerryProf. Fred Terry Univ. of MichiganUniv. of Michigan


AGENDAAGENDA

• 2002 ITRS Changes

• Lithography Metrology

• FEP Metrology

• Interconnect Metrology

• Materials Characterization

• Key Challenges


2002 ITRS Changes2002 ITRS ChangesTechnology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm

MPU / ASIC ½ Pitch (nm) 150 90 65 45 32 22MPU Printed Gate Length (nm) 90 53 35 25 18 13MPU Physical Gate Length (nm) 65 37 25 18 13 9

Lithography MetrologyPrinted Gate CD Control (nm)Allowed Litho Variance = 2/3 Total Variance of physical gate length

5.3 3 2 1.5 1.1 0.7

Wafer CD Tool 3 Precision P/T=0.2 for Printed and Physical Isolated Lines

1.1 0.6 0.4 0.3 0.2 0.1

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65

Precision for LER 0.9 0.54 0.36 0.26 0.18 0.13

Interconnect Metrology

Barrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

Void Size for 1% Voiding in Cu Lines 87 52 37 26 18 12

Detection of Killer Pores at (nm) size 6.5 4.5 3.25 2.25 1.6 1.1

Orange = production done w/out meeting ITRS precision specification


2001 2002 2004 2007 2010 2013 2016

Leading ProductionTechnology Node = DRAM ½ Pitch

130 nm 115 nm 90nm 65 nm 45 nm 32 nm 22 nm

MPU / ASIC ½ Pitch (nm) 150 130 90 65 45 32 22

MPU Printed Gate Length (nm) 90 75 53 35 25 18 13

MPU Physical Gate Length (nm) 65 53 37 25 18 13 9

Beta Site 90 nm Node

R&D 65 nm Node

Early R&D 45 nm Node

Metrology TimelineMetrology Timeline

Leading Edge ToolSpecifications set

2003

45 nm Node Metrology R&D Materials available

10 nm structures difficult to obtain


Litho Process part of total CD budgetLitho Process part of total CD budget• Litho Process range - Litho 2/3 Etch 1/3 in 2002

may change in 2003• Use Process Range for Physical (Etched) Gate for both Printed and

Etched Gate• Variances add as sum of squares • Etched Gate

– 90 nm node Process range for 37 nm physical i.e., etched gate, of 3.7 nm 3 (i.e. plus or minus 10%)

– 2/3 of (3.7 nm)2 = 9.12 nm which gives 3 nm 3 for Litho Process Range

– 3 Precision for P/T of 20% is 0.2 x 3 nm = 0.6 nm• Make Precision of Printed gate match that of Etched Gate and Result

is that Printed Gate now requires better precision


CD Potential SolutionsCD Potential Solutions2001 2002 2004 2007 2010 2013 2016

Leading ProductionTechnology Node = DRAM ½ Pitch

130 nm 115 nm 90nm 65 nm 45 nm 32 nm 22 nm Driver

MPU / ASIC ½ Pitch (nm) 150 130 90 65 45 32 22

MPU Printed Gate Length (nm) 90 75 53 35 25 18 13

MPU Physical Gate Length (nm) 65 53 37 25 18 13 9

CD-SEM

High Voltage CD-SEM

Scatterometry

CD-AFM

Point Projection Microscopee - holography

R&D RequiredMeets ITRS Precision

w/o tool matching


3D CD Metrology 3D CD Metrology SEM – Scatterometry – CD-AFMSEM – Scatterometry – CD-AFM

Commercially availableR&D

Software comparison of top

down line scan of edge to golden image

Tilt Beam SEM

Scatterometry

CD-AFM

-480 -400 -320 -240 -160 -80 0 80 1600

100

200

300

400

500

600

5

-480 -400 -320 -240 -160 -80 0 80 1600

100

200

300

400

500

600

5

Software to convert top down image to

3D image


Line Edge Roughness RequirementsLine Edge Roughness RequirementsNow: LWR In or Off-lineNow: LWR In or Off-line

Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-1.0 -0.5 .0 .5 1.0 1.5Log Active Width

LER = 10 nmLER = 3 nm

IL @

500

A/

m Id

Line Width RoughnessCorrelated to

Leakage Current Increase

Patterson, et. al., SPIE 2001

AVE CD = 150 nm

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nmPrinted Gate CD Control (nm)Allowed Litho Variance = 2/3 Total Variance of physical gate length

5.3 3 2 1.5 1.1 0.7

Wafer CD Tool 3 Precision P/T=0.2 for Printed and Physical Isolated Lines

1.1 0.6 0.4 0.3 0.2 0.1

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65

Precision for LER 0.9 0.54 0.36 0.26 0.18 0.13


FEP : High FEP : High Metrology Metrology

0.00E + 00

1.00E -07

2.00E -07

3.00E -07

4.00E -07

5.00E -07

6.00E -07

7.00E -07

8.00E -07

9.00E -07

1.00E -06

-3 -2 -1 0 1 2 3

V g (V )

C (

F/c

m^

2)

Dit= 0

Dit= 1e10

Dit= 1e11

Dit= 1e12

Dit= 1e13

tox = 3nm ,Ns ub= 1e17,Npoly = 1e20

“Out of the Furnace” High Dit

= Error in EOT

polarizeranalyzermonochromator

E

s

p

Polarizationbefore sample

s

p

E(t)

Polarizationafter sample

p

s

p

s

Si

polarizeranalyzermonochromator

E

s

p

Polarizationbefore sample

s

p

E(t)

Polarizationafter sample

p

s

p

s

Si

Light source:(Xe, D2, lasers)

High near UV light absorption

Makes thin interfacial layer difficult to measure

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverFront End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU

Metrology for Ultra-Shallow Junctions at Channel Xj (nm)

26 14.8 10 7.2 5.2 3.6 MPU


Extra reflection from SOI Wafers Impacts Extra reflection from SOI Wafers Impacts Optical Measurements and Light ScatteringOptical Measurements and Light Scattering

SOI WaferSOI Wafer

Si WaferSi Wafer

Gate Dielectric Gate Dielectric on Si Waferon Si Wafer

Gate Dielectric Gate Dielectric on SOI Waferon SOI Wafer

SOI WaferSOI WaferSOI WaferSOI Wafer

Si WaferSi WaferSi WaferSi Wafer





Quantum confinement for sub 20 nm siliconNeed SOI Optical Constants


Metrology & New StructuresMetrology & New Structures

DEVICE RESONANT TUNNELING

DIODE – FET

SINGLE ELECTRON TRANSISTOR

RAPID SINGLE QUANTUM FLUX

LOGIC

QUANTUM CELLULAR AUTOMATA

NANOTUBE DEVICES

MOLECULAR DEVICES

TYPES 3-terminal 3-terminal

Josephson Junction

+inductance loop

-Electronic QCA

-Magnetic QCA FET

2-terminal and 3-terminal

S T O R A G E M E C H A N I S M

B A S E L I N E 2 0 0 2 T E C H N O L O G I E S

M A G N E T I C R A M P H A S E C H A N G E

M E M O R Y N A N O F L O A T I N G

G A T E M E M O R Y

S I N G L E / F E W E L E C T R O N M E M O R I E S

M O L E C U L A R M E M O R I E S

D E V I C E T Y P E S D R A M N O R F L A S H P S E U D O -

S P I N - V A L V E

M A G N E T I C T U N N E L

J U N C T I O N O U M

- E N G I N E E R E D

T U N N E L B A R R I E R - N A N O C R Y S T A L

S E T

- B I S T A B L E S W I T C H

- M O L E C U L A R N E M S

- S P I N B A S E D M O L E C U L A R

D E V I C E S

W O R D B I T

W R n + n + m e m o r y n o d e E n g i n e e r e d b a r r i e r

S i

G a t e

Logic

Memory


Gaps in Interconnect Metrology

• VOID Detection in Copper lines

now based on ½ via diameter

• Killer Pore Detection in Low

• Barrier / Seed Cu on sidewalls

• Control of each new Low

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm



1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

Void Size for 1% Voiding in Cu Lines 87 52 37 26 18 12

Detection of Killer Pores at (nm) size 6.5 4.5 3.25 2.25 1.6 1.1


High Frequency Measurement of High Frequency Measurement of

• NIST’s characterization of for low have shown that is stable

• Industry sees less need for high frequency measurement of for low


Interconnect Clarification for Void Interconnect Clarification for Void Detection in Copper LinesDetection in Copper Lines

• Detection of post deposition and anneal process voids at or exceeding listed size (nm) when these voids constitute 1 % or more of total metal level conductor volume of copper line and 5% of vias. [B]


Barrier –Seed Cu Barrier –Seed Cu Process ToleranceProcess Tolerance

• Flat – horizontal film measurement used to control sidewall thickness

• Lower limit is thinnest film that acts as barrier

• Upper limit is thickest film allowed for resistivity concerns

• Very thin barriers may be digital i.e. there or not


Materials CharacterizationMaterials CharacterizationNeed New Microscopy Methods Need New Microscopy Methods

LEAP is one exampleLEAP is one example

High Voltage

Needle-Shaped Specimen

Imag

e S

creen

LEAPlocal electrode atom probe

Atom by atom 3D profile


Key Metrology Challenges Key Metrology Challenges • Breakthrough microscopy for CD measurement

• Measurement capability for control of interface between high and substrate & gate electrode

• Low killer pore detection and copper void control

• Atom by Atom microscopy for materials characterization


Backup


2001 Metrology Requirements Summary2001 Metrology Requirements Summary

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverLithography MetrologyWafer Gate CD nm post-etch contol 6.5 3.7 2.5 1.8 1.3 0.9 MPU

Wafer CD Tool 3s Precision P/T=0.2 Isolated Lines

1.3 0.75 0.5 0.36 0.26 0.18 MPU

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65 MPU

Precision for LER 0.9 0.54 0.36 0.26 0.18 0.13Overlay Control (nm) (mean +3s ) 45 31 26 18 13 9 MPU

Overlay Metrology Precision (nm) P/T=0.1 4.5 3.1 2.6 1.8 1.3 0.9 MPU

Front End Processes Metrology

Logic Dielectric Thick Precision 3 (nm)0.005 0.004 0.0024 0.0024 0.0016 0.0016

MPU


26 14.8 10 7.2 5.2 3.6 MPU



1320%0.04

1020%0.03

720%0.02

520%0.016

420%0.013

MPU

Void Size for 1% Voiding in Cu Lines 32.5 22.5 16.25 11.25 8 5.5 MPU

Detection of Killer Pores at (nm) size 6.5 4.5 3.25 2.25 1.6 1.1 MPU


New Metrology Need: Standardized New Metrology Need: Standardized Statistics for Discretized DataStatistics for Discretized Data

• Some new methods fit measurement to a discrete set of possible results

• This could result in artificially good precision values that do not really evaluate process control capability

89 nm 89.5 nm 90 nm 90.5 nm 91 nm

0

0.1

0.2

0.3

0.7

0.8

0.9

1

0

0.1

0.2

0.3

0.7

0.8

0.9

1

0

0.1

0.2

0.3

0.7

0.8

0.9

1


2001 Metrology Requirements Summary2001 Metrology Requirements SummaryTechnology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm Driver

Lithography MetrologyWafer Gate CD nm post-etch contol 6.5 3.7 2.5 1.8 1.3 0.9 MPU

Wafer CD Tool 3 Precision P/T=0.2 Isolated Lines

1.3 0.75 0.5 0.36 0.26 0.18 MPU

Line Edge Roughness (nm) 4.5 2.7 1.8 1.3 0.9 0.65 MPU

Line Edge Roughness Precision 3 (nm) 0.9 0.54 0.36 0.26 0.18 0.13 MPU

Overlay Control (nm) (mean +3 ) 45 31 26 18 13 9 MPU

Overlay Metrology Precision (nm) P/T=0.1 4.5 3.1 2.6 1.8 1.3 0.9 MPU

Front End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU

Capacitor Thickness Precision 3 (nm) 0.05 0.05 0.11 0.11 0.09 0.07 DRAM


26 14.8 10 7.2 5.2 3.6 MPU

Interconnect MetrologyBarrier layer thick (nm) process range (±3 ) Precision 1 (nm)

1820%0.06

1120%0.036

820%0.027

720%0.023

520%0.017

420%0.01

MPU

Void size for 1 % Voiding in Copper Lines 32.5 22.5 16.25 11.25 8 5.5 MPU

Detection of Killer Pore at (nm) Size 6.5 4.5 3.25 2.25 1.6 1.1 MPU


Novel Methods for FEM controlNovel Methods for FEM control

SL

e.g.150 nm lines300 nm pitch

Optical CD using Overlay System

Automatic cross-sectioning,

imaging and metrology from all sites of the

FEM

Dose Fo

cus

Dualbeam FIBFEI


Status of Potential Status of Potential Solutions for CDSolutions for CD

• Single tool remove matching precision loss• CD-SEM supplier community expresses

confidence enhancements can extend traditional approach

• Real Time Scatterometry replaces library approach

• Scatterometry may require VUV • CD-AFM tip technology limits dense line and

contact measurement


CD-SEM Possibilities CD-SEM Possibilities

Conventional Imaging

HolographyLow

EnergyHigh

Energy

The

CD-SEM

(1)

The High Energy CD-SEM

(2)

The Point Projection

Microscope

(3)

The

CD-TEM

(4)

MODE ENERGY


Leakage Current correlated to Leakage Current correlated to Line Edge RoughnessLine Edge Roughness

-8.0

-7.5

-7.0

-6.5

-6.0

-5.5

-5.0

-1.0 -0.5 .0 .5 1.0 1.5Log Active Width

LER = 10 nmLER = 3 nm

IL @

500

A/

m Id

Center of data at 150 nm channel

length with drive current of 500 A/m

Leakage plotted versus active width

of transistor

The two lines show the dependence

for the case of low and high line edge

roughness.

Units for leakage current are A/m,

plotted on a logrithimic scalePatterson, et. al., SPIE 2001

Thanks to ITRS Litho TWG - Harry Levinson / Mauro Vasconi


CD-SEM a Potential Solution CD-SEM a Potential Solution for for Wafer and Mask / R&D + ProductionWafer and Mask / R&D + Production

Sato and Mizuno, EIPBN 2000, Palm Springs, CA

Barriers and Solutions

193 & 157 nm Resist Damage» lower dose images

Lineshape » tilt beam SEM vs software

Precision Improvements» new nano-tip source

Depth of Focus» new SEM concept needed

Ultimate Limit of CD-SEM» ~ 5 nm for etched poly Si Gate


Gaps in FEP Metrology

• Physical Metrology for high k gate stack– Optical Models for next High k (beyond HfO2)– Interfacial control for interface between high k

and silicon

• Electrical Metrology for high k gate stack– Application of Non-contact C-V to next High k

(beyond HfO2)– Comparison of non-contact electrical to C-V

Technology Node 130 nm 90nm 65 nm 45 nm 32 nm 22 nm DriverFront End Processes MetrologyLogic Dielectric Thick Precision 3 (nm) 0.005 0.004 0.0024 0.0024 0.0016 0.0016 MPU


26 14.8 10 7.2 5.2 3.6 MPU


FEP Metrology FEP Metrology

• Optical and Electrical measurement of High can be done for development but needs to be robust for manufacturing

• Metrology for interface below High needs R&D

• USJ Metrology needs development for < 65 nm

• FERAM needs fatigue testing for 1016 read/write cycles


Voids in CopperVoids in CopperPore Size/Killer Pores in Low kPore Size/Killer Pores in Low k

• Random isolated void detection in copper lines may be used in development at levels

above the < 1% metric

• <1% may not be measurable


Interconnect Metrology SolutionsInterconnect Metrology SolutionsBarrier/Seed Cu FilmsBarrier/Seed Cu Films

ZY

X

Wafer Positioning Stage

Sample

Detector

Aperture

Lens

Probe Laser

Excitation Laser

Neutral Density (ND) Filters

Phase Masks (PM)

Lens

Lens

20x 90 mm Spot Size

~1-2 seconds/point (measurement + data analysis + stage motion)

Excitation LaserDiode-Pumped, Pulsed, Frequency-Doubled Nd:YAG microchip laser. 600 ps Pulse

AlGaAs Diode Laser

5 Potential Solutions 5 Potential Solutions all expected to meet precision requirementsall expected to meet precision requirements

some are extendable to patterned waferssome are extendable to patterned wafers

Objective lens

GenerationlaserProbe laser

Beam splitter

Visionsystem

Detector

Detail inwafer

Junction

Beam

Excess carriers

X-Ray Tube

Thin-Film Sample

Monochromator

Spatially ResolvingX-Ray Sensor

0.15 mm 1psec

Pulsed Laser(200 fsec; 90 MHz) 800nm

Servo delay

Lens

FrequencyDoubler

photocell

Wafer

WavelengthSelector

Acoustic ISTSPicosecond acoustics

X-ray reflectivityX-ray fluorescence

Non-contact resistivity


2001 Grand Challenges2001 Grand Challenges

• Development of Metrology tools in time. • Rapid non-destructive metrology for

CD, overlay, defect detection and line edge roughness that meets ITRS timing and technology requirements.


Will Market Risks allow for innovation?Will Market Risks allow for innovation?

Metrology RoadmapMetrology Roadmap

Metrology Timing Metrology Timing vsvsInfrastructure CapabilitiesInfrastructure Capabilities

Process Tool Supplier Development

Pilot Line FAB Startup & Volume Manufacture

Volume Sales of Metrology Tools

Need for Process Tool

Qualification/Preproduction

Development Underway

Typical Potential Solutions Time Line for Process Tool

Research Required

Need for Metrology Tool

Gap in long term R&D Gap in long term R&D Spending + Development Spending + Development Funding ModelFunding Model

4 december 2002, itrs 2002 update conference metrology roadmap 2002 update europeulrich mantz...

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