4 kpca 2011(sslee)

High Layer Count PCB

Technology Trends in KOREA

April, 21 2011April, 21 2011

Sang Soo LEESang Soo LEE

ISUPETASYS

22Contents

Definition of High Layer Count PCB

Core Technology TrendsCore Technology Trends

High Layer Count PCB Technology Drivers

Interconnection Reliability

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441. Definition of High Layer Count PCB

With the popularization of the Internet, wireless data system and mobile communication,

Hi h l t PCB i i d t t it d t

High Layer Count PCB

High layer count PCB is required to transmit data rapidly and fulfill the need to process data with high speed

Application

Line Card, Backplane for Communication Network High-End Router, Server, Storage

General Specification

g , , g Workstation, Super Computer.

Layer Count : +18L Thickness :

552. Market Characteristics & Trends

Relatively conservative purchasing than consumer product PCB

Market Characteristics Relatively conservative purchasing than consumer product PCB Prefer to highly experienced PCB supplier Listing on the OEM Vendor List EMS has no independent authority to select PCB supplier Without almost perfect internal QA sys Higher Claim charge (Ave USD $4~5 000/pcs) Without almost perfect internal QA sys, Higher Claim charge (Ave USD $4~5,000/pcs) No merit at all, without almost perfect inner layer process yield rate (see the below)

11 of 12 = 91.6% 11 of 12 = 91.6% yield, 3~4 coresyield, 3~4 cores 0%, 8 + cores0%, 8 + coresyield, 3 4 coresyield, 3 4 cores

662. Market Characteristics & Trends

Changing Traditional Trends

Giant industrial OEM rushing toward ASIAN PCB SHOPS. WHY?

router. server. supercomputer. Aero space., etc

Conventionally strong U.S/ Europe pcb shopsClosed local factories since IT Bubble or transit SHOPS in Southeast Asia.

Unlike Asian, reluctant to invest aggressively new manufacturing facilities Unlike Asian, reluctant to invest aggressively new manufacturing facilities

Brought to long term delivery (8~10 weeks)

Asia PCB Suppliers surprisingly playing well doing job with Asia PCB Suppliers surprisingly playing well doing job with

Excellent technology and brand new facility Low PPM level of Defect Delivery responsivenessDelivery responsiveness

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Reliability

881. Top Stage- Core technology Trends

Increasing traffic density across internet data storage are need for higher volume

Industrial technology driver

Increasing traffic density across internet, data storage are need for higher volumedata throughput

The next generation of back planes will require serial data rates of 10Gbps whilethe emerging. Intermediate back plane products will employ 6.25 Gbps serial data rates. 5/6.25 Gbps => 10Gbps

High volume data throughput & High speed signal requiring pcbHigh volume data throughput & High speed signal requiring pcbTo design circuit with total signal integrity such as highly accurate impedancecontrol, time delay, signal loss, skin effect, skew etc.

Product Technology 2009 2010 2011 2012

System Roadmap

gyRouter Band Width 10Gbps 20Gbps 40Gbps

Serial Data Rate 6.25Gbps 10Gbps 20Gbps

S Clock Speed 2Gh 2 5Gh 3 5GhServer Clock Speed 2Ghz 2.5Ghz 3.5Ghz

992. Middle Stage Core Technology Trends

Core technology for High Layer Count PCB

Higher Volume data throughput & clock speed put dramatically impact onPCB Design. Manufacturing. Reliability and Environmental issue

2 SignalInt

Routing Density- HDI (Blind & Buried Via)- VIP (Via in Pad)

1.RoutingDensity

2.SignalIntegrity - Reduction for Layer Count, Line width

High Speed Signal Integrity- Electrical Simulation

Higher Data Rate & Clock Speed

- Buried Capacitance & Resistance- Material & Design (Ultra Low Dk/Df)

Environmental Regulation

3.Environmental Regulation

4.Interconnection Reliability

p- Lead Free- ROHS

Interconnection Reliability- IST- CAF

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Reliability

11111. High Layer Count PCB Technology Drivers 1

Core driver 1. Material

What is a markets needs for material?

Guaranteed same electrical performance (Dk/Df) with lead free compatible material.

Guaranteed thermal reliability after lead free assembly.

Supply a low cost lead free compatible material Supply a low cost lead free compatible material.

Markets Market s Needs

Low Cost


Tier 3~5 laminates are gaining an increasing share of the market for high-speed applications (Low Dk / Low Df)

Source by IPC


What is a difference?

Should use a lead free alloys instead of Sn/Pb alloys.y y

SAC Solder need more higher reflow temperatures. Up to 20C higher

Reflow Type Solder Type Solder Melting Point Peak Reflow Temperature

Sn/Pb Reflow Eutectic Solder 183 210~240

Lead-Free Reflow SAC (96.5Sn/3.0Ag/0.5Cu) Solder 217 240~260Lead Free Reflow SAC (96.5Sn/3.0Ag/0.5Cu) Solder 217 240 260

JEDEC Profile(J-STD-020C)

Upper line: Lead free ReflowLower line: Sn/Pb Reflow


What we are considering

Comparison of thermal properties for laminate

Test Items Dicy Cured 170 Non-Dicy Cured 170 Low Dk/Df 200

Test Vehicle Laminate (Double Side) Laminate (Double Side) Laminate (Double Side)

CTE 3.7% 3.0% 3.5%

TMA (Tg) 170.0 170.0 170.0

TGA (Td) 325.0 350.0 365.0

T260 4min ~ 8min Over 60min Over 30minT260 4min 8min Over 60min Over 30min

T288 2min Over 10min Over 10min


Test Items Dicy Cured 170 Non-Dicy Cured 170 Low Dk/Df 200

1) Comparison of thermal properties for 16L Board

Layer Count 16L 16L 16L

Overall Thickness 2.38mm (9.4mil) 2.38mm (9.4mil) 2.38mm (9.4mil)

CTEBGA Area 3.31% 3.52% 2.88%

TMA TgBGA Area 176.6 176.2 200.6 T260-Clad 3.5 min Over 20 min Over 20 min

T288-Clad 0 min 3.58 min 1.63 min

Test Items Dicy Cured170 Non-Dicy Cured 170 Low Dk/Df 200Layer Count 28L 28L 28L

2) Comparison of thermal properties for 28L Board

Layer Count 28L 28L 28L

Overall Thickness 3.0mm (118mil) 3.0mm(118mil) 3.0mm(118mil)

CTEBGA Area 3.83% 3.65% 3.35%

TMATgBGA Area 163 4 161 0 177 4 TMATgBGA Area 163.4 161.0 177.4 TGA (Td) 312.5 328.0 338.8 T260-Clad 3.2 min Over 20 min 12.85 min

T288-Clad 0 min 2.2 min 0 minT288 Clad 0 min 2.2 min 0 min

Lead-Free Reflow 5X Fail Pass Fail


What we are considering

Lead Free Reflow Test

Dicy Cured 170C Low Dk/Df 200CNon dicy cured 170C

Lead Free Reflow Test Lead free reflow test is necessary to confirm the evaluation result. You can find de-lamination in black spot area.

Dicy Cured 170 C Low Dk/Df 200 CNon-dicy cured 170 C

X-Section Dicy Cured 170C X-Section Low Dk/Df 200C Evaluation report shows a little bit difference between raw material and PCBs Evaluation report shows a little bit difference between raw material and PCBs. Basically, Thermal reliability is affected by board design (Layer Count,Thickness)


Core driver 2. Routing Density

2 1 Routing Density : Finer line width & Layer Count increasing2-1. Routing Density : Finer line width & Layer Count increasingRequired : Layer counts 18~22L 24~30L / Line width 5mil 4mil 3mil

Key Point 2 Finer line widthKey Point 1. (layer count increasing)

Handle thin Coreless 100um in process Registration Control

High Aspect Ratio of plating

Key Point 2. Finer line width

Signal line width tolerance 10% 7% Signal line width 3/3 mil will cause drastic

Yield drop High Aspect Ratio of plating p

2011 2012Road MapRoad Map

Internal Lines & SpacesExternal Lines & Spaces

3 / 4 mil 3/3mil

3.5/4 mil

BGA Ball Pitch (Goal)

1.0mm 3 lines 0.8mm 2 lines


2-2. Routing Density : Drill to Metal

Required : Ball Pitch of BGA & CCGA are smaller design as 0.4 & 0.5mm from 0.8 &1.0mm pitchR i d R ti D it i hi h b t d t d Required : Routing Density is higher between pad to pad

What is Drill to Metal?

Spacing between drill edge to around signal traceKey Point

U i S ll t D ill i 6 10 ilSpacing between drill edge to around signal trace Spacing between drill edge to around Anti-padedge

Using Smallest Drill size as 6~10mil Keep upgrade Registration Capability

Prepreg

Signal D2M 2011 2012Signal D2M

Annular ring + Spacing 7mil 6mil

Pattern

ThinCoreDrill

9mil 8mil 7mil

2011 2012Plane D2M22mil 20mil

Prepreg

Anti pad Size26mil 24mil 22mil

22mil 20mil

Plane Anti pad D2M


2-3. Routing Density : HDI

Required : HDI design is required for Line Card to reduceBuried Via

Staggered Via (1~3L)

Layer count

Layer Count : 14~26 Board Thickness : 2.0~2.8t

Buried Via Hole (2~25L)

Buried Via Core (13~14L)

Micro Via : 127um, 200um Type : 1-2/2-3 Staggered via, 1-3 Skip via Min. Via : 200um Prepreg used for Micro Via holes

Key Point

Registration within 3mil- PEP, Registration Validation Coupon Plated inner layer yield control

Standard glass Spread glass

Plated inner layer yield control Control copper thickness on plated signal layers Laser drilling- Remove smear with normal prepreg

The fixed energy can not Exactly fit the poor area (arrow1) & the glass rich area (arrow2) at the same time


2-4.Routing Density : Via in Pad

What is VIP?What is VIP?VIP stands for Via In pad and its structure hasplugged with via epoxy and topside is capped with plating

It was used to increase routing density and attach the

Smaller components

Merits Provides a flat coplanar surface Provides a flat coplanar surface Make routing easier and more traces on PCB Increase component density

Potential EMI. SI benefits Help thermal management A l t & i k f ld i bl A lower cost & risk of soldering problem


2-4. Routing Density : Via in Pad Application : Surface mounting BGA pad

Smallest BGA & CCGA designSmallest BGA & CCGA design

Layer Count : 14~28 Board Thickness : 2 0~3 2t Board Thickness : 2.0~3.2t Type : Plugging for Plated and External MicroVia Min. Via : 200um FHS A/R :15:1

Key Point

Pull the wire vertically by using a 50kg load at 10 cm / minute Pull the wire vertically by using a 50kg load at 10 cm / minuteUntil the pad is peeled off and record the load percentage.

Average force of 250 Newtons/Sq.cm [~360 Pounds-force/Sq]

S/N2,Condor #6S/N1,Condor #3 S/N1,Condor #4 ,@20X Magnification@20X Magnification

,@20X Magnification


Via Plugging -Criterion

2-4. Routing Density : Via In pad

Failure Mode

Air pocket in MVH Non filling in PTH DimplePlanarization

Air Pocket Dimple Note Specification

Specification

Under 5%(Via Hole Dimension)

Under 50um Normal

None None Stric (Mil/Areo)

Higher Aspect ratio but more strict criterion


2-5.Routing Density : Via In pad (Paste- Low CTE, High Peel Strength)A B C D

V Type Viscosity Pas/25 35-45 30-40 30-40 35-45

Shelf Life10 90days 90days 60days 90days

5Tg (TMA) 0 141 168 160 170

CTE ppm/ 39 39 32 242 ppm/ 143 105 83 7025 MPa 7200 5200 8600 8500

6200Rate of moisture absorption

(DMA)

100 5800 4300 6200 6700

150 820 2600 4300 5300

200 340 870 2600 1300

250 280 660 2100 700

Absorptance JISC6481 % 0.23 0.16 0.15 0.15

Dill SizeAvg m 4~5 2~3 2~3 3

Max 22.5 15 17.5 17.5

P C k % 100 100 100 100Pan-Cake % 100 100 100 100

UL 94V-0 94V-0 94V-0 94V-0

Peel Strength g/cm 400 670 900 400

14030

Curing Condition min8010

1101015030

PCB1106015030

FCPKG)

1106015030

1106015030


Core driver 3. High Aspect Ratio Plating in Acid Copper

3 1 High Aspect Ratio Trend & Plating Core driver

Trends : Aspect ratio(DHS) which are Conventional boards will be increased about 13:1 in near term. Request : Increasing Layer counts and Routing Density, It is caused for plating capability to enhances high

3-1. High Aspect Ratio Trend & Plating Core driver

Aspect ratio Board Reliability.Aspect Ratio

Trend21:12010~20112012~2016

12:1

15:1

18:1 2008~20092010~2011

2006~2007

- Use RPP and optimize a RPP parameter for thickPlating copper thickness

- Consider a material property for preventing plating void

6:1

9:1

12:1

11:112:1

13:1plating void

(Activation energy are different among raw materials)

- Check the metal ion concentration in the plating Tank for better copper property

2006~2007 2008~2009 2010~2011 2012~2016

3:1

0

10:1- Consider full build electroless copper plating.

It is easy to control plating rate.

IPC International Technologies Roadmap 2006~2007 State of arts boards may have more high aspect ratio (18:1~24:1)


3-2. Desmear Trends : The low Dk/Df Material construction challenge and the fluidity challenge of high aspect ratio hole

To impro e a Signal integrit generall se lo Dk/Df Material- To improve a Signal integrity, generally use low Dk/Df Material

- High Aspect ratio drop the fluidity.

Request : Because of low Dk/Df Material use and high aspect ratio, Desmear process must be setup fornew material.

- Consider plasma machine for de-smear, because gas fluidity is better than liquid and

Have a better etch rate (Positive etch back).

- Keep Improve a swelling process for getting a more etch rate and roughness on hole wall

- Consider new basket design for better fluidity

Positive Etch Back 0.24mil

- Consider new basket design for better fluidity


3-2. Desmear Trends : As required lead free conditions, a raw material of low Dk/Df need a stronger for heat.

Based on this req irements of market lo Dk/Df material added a filler constr ction in resinBased on this requirements of market, low Dk/Df material added a filler construction in resin.


Test Panel Spec.-Nelco4 000-13SI-Layer Count: 28L-Board Thick.:196mil

3-3. Pulse Plating MVH, PTH

Cu plating Capability

-DHS:10.8mil-MVH:8mil-DHS A/R:17.8:1

Cu plating thickness in PTH (DHS 10.8mil)

Min:1.02mil, Max:1.32mil, Avg:1.14mil

C l ti thi k i MVH ( i 8 il)Cu plating thickness in MVH (size:8mil)

Min:1.46mil, Max:1.78mil, Avg:1.57mil

Reliability Thermal Stress (3X,6X)

3X PTH 3X MVH 6X PTH 6X MVHNone None None None1.52 0.6 1.41 0.76Wicking(mil)

ItemDelamination

y ( , )

0.27 - 0.29 -132.4% - 127.8% -None None None None3.4% - 4.7% -Resin Recession(%)

Hole Roughness(mil)Nail Head(%)

Smear

None None None NoneNone None None None

( )Pull away

Copper Crack


Core driver 4. Signal Integrity

4 1 Ultra Low Dk/Df

Required : Low Dk/Df material used for High Speed boardSignal Attenuation

4-1. Ultra Low Dk/Df

Signal Attenuation1Gbps 5Gbps 10Gbps 20Gbps

FR 4 Ultra Low loss < 0 01Mid Low loss: 0 01 0 015

Nelco N4000-13Isola FR408HRPanasonic Megtron4

FR-4

Nelco N4000-6Isola FR406Panasonic R-1766

Ultra Low loss < 0.01

Nelco N4000-13SIIsola IS620/IS640Panasonic Megtron6

Mid Low loss: 0.01-0.015

- Still cost adder- Well defined hole wall process condition for higher Tg/Td matl

Hi h d t t /F t i ti /L li f l b k l

g g

- Higher data rate/Faster rise time /Longer lines of large back planes- Propagation delay. Skin effect. P or S parameter also should be taken into

consideration

29294. High Layer Count PCB Technology Drivers 4 Confidential

4-2.Fiber weave effect (Special Glass weave)

Required : Traditional Glass weave causedDk/Df variation instability for a pairDk/Df variation instability for a pairtransmission on spread out of glass weave.

Highly spread outTreatment #1078

Normal typeNon treatment # 1080

Key Point U i th hi h d it f i l l

Treatment #1078Non treatment # 1080

Using the high density of special glass weaveMake Dk/Df variation instability.

Thickness is thinner because of yarn is spread out

The gap is smaller than normal type

#106, #1080 => #1067,1078


Required : Capacity launches can act as low-pass filter,the effect of which is top rohibit the

4-3.Back Drilling MNC: Must Not-CutLayer

ptransmission of high frequencies (Stub Effect)

The capacitance and the stub are both reduced

StubLength

Key PointKey Point Only incremental improvements on the PCB for

Signal speed increasing Yield and quality control for single & multiple depth Depth tolerance is changed from 254um to 127um 1~4L 4~26L Depth tolerance is changed from 254um to 127um Back drilling positioning

Back-Drill : Multiple Depth

1~4L 4~26L

4~26L

Source: Worldwide High-speed Electronics Tech.& Market Trends For the Years 06~16

Short NG: Drill Position error


4-3-1.Effect of Back Drilling


4-4. Buried Capacitance

Required : ultra thin core thickness 50um 24um 12umP Hi P t T t N f il I/L d fi i h d b d Process : Hi Pot Test : No failure on I/L cores and finished boards

Key Point

How to handle while proceed thinner corebetween inner to press process

C t l Hi t t t diti Incoming InspectionPost Etch Puncher

AOI Control Hi-pot test conditions Registration

I/L PrepAcid Rinse only

(Reverse Treated Foil)

AOI

Hi Pot TestFor Inner-layer Boards

Customer ConditionUltra Flex line

Dry Film LaminationMax. Delay time is 24hr

Ultra Flex DES line

(1mil Core Compatible line)

Horizontal Oxide


l

e

s

t

v

i

H

o

l

e

BC 24um

Imaging with UV Exp.


Lamination &Electrical TestS

m

a

l

a

L

a

r

g

e

H

BC 24um

DES Line(Cupric Acid)

Hi Pot TestFor Finished Boards

Customer Condition


Required : Frequency increasing rapidly, problems of reflection, crosstalk,Power and Ground noise are required signal integrity simulation

4-5.Signal Integrity Simulation

to reduce time and failure cost

Signal impedance matching / Critical Net Return Loss Analysis S parameter Via Hole Return Attenuation K P i t

Port1Port2

Via Hole Return Attenuation Optimized Design for Plating thickness improvement Key Point

Higher accurate single & differential impedance To reduce time and failure cost

- Noise of Crosstalk, Reflection, Power/Ground - EMI Issue / Skew control matters- Group Delay / Jitter control

4-6. Electrical Performance Measurement Required : Real SI testing is one of the Hot Issue!

Particularly signal loss value at real circuit boardPanel edge placed coupon testing is not fully enough

Trace Impedance Insertion Loss S21 / Return Loss S11 Conductor Loss dB/ Dielectric Loss in dB Propagation velocity & Delay/ SPICE Model (RLGC) Crosstalk Jitter Eye-Diagram/ Current Distribution Crosstalk, Jitter, Eye-Diagram/ Current Distribution

S-parameter in frequency domain

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Coredriver 5. Interconnection Reliability

I i R li bili

Required: Highest Interconnection Reliability Concern: Conventional Reliability Test Method has


Concern: Conventional Reliability Test Method has long term and Random selection to verify 5-1. Conventional Thermal stress & Cycling

Key Point

Conventional Reliability Test Method haslong term and Random selection to verify

- Thermal Stress- Thermal Shock

Needs: Want to guarantee Long term Reliability

Conventional Reliability Test Method are changed by electrical test method in easy & high reliability such as

- ISTCAF- CAF


IST : Interconnect Stress TestMonitoring variation of resistance value

5-2. IST

Monitoring variation of resistance valueInside hole wall in real time

Barrel Crack

ICDs

37375. High Layer Count PCB Technology Drivers5

CAF : Conductive Anodic FilamentMonitoring variation of resistance value in real time

C-SAM : C-mode Scanning Acoustic MicroscopeNon destructive Internal Inspection for

5-4. CAF 5-5. C-SAM

Monitoring variation of resistance value in real time( hole to hole, hole to trace, trace to trace, layer to layer)

Non destructive Internal Inspection forDetecting De-lamination

Possible CAF growth Observed betweenHole to Trace.

3838Conclusion

Future Challenges

High speed serial link electrical packaging challenges due to Increasing data rates

Special Impedance Connectors(7% ~ 5%)p p ( )

Back drilling of vias at the PTH connectors will be challenge

Common mode noise due to phase skew between differential pairs and Connectors Common mode noise due to phase skew between differential pairs and Connectors

Predict Fiber weave effect in simulation

Simulate Resin content effect

Low loss material Vs. Crosstalk Vs. reflection

4 kpca 2011(sslee)

Documents

product technology

excellent technology

asian pcb shops

gbps serial data rates

internet data storage

stage core technology

weeks asia pcb suppliers

wireless data system