5 - 1 texas instruments incorporated module 5 : event manager c28x 32-bit-digital signal controller...

5 - 5 - 11

Texas Instruments IncorporatedTexas Instruments Incorporated

Module 5 : Event Manager C28xModule 5 : Event Manager C28x

32-Bit-Digital Signal Controller32-Bit-Digital Signal ControllerTMS320F2812TMS320F2812

5 - 5 - 22

Event Manager Block Diagram Event Manager Block Diagram (EVA)(EVA)

PWM CircuitsPWM Circuits



Output LogicOutput Logic



GP Timer 1 CompareGP Timer 1 Compare

GP Timer 1GP Timer 1



Compare Unit 1Compare Unit 1



Capture UnitsCapture Units

MUXMUXQEPQEP

CircuitCircuit



EV Control Registers / LogicEV Control Registers / Logic

ResetReset PIEPIE

TCLKINA / TDIRATCLKINA / TDIRA//22

ADC StartADC Start

Dat

a B

us

Dat

a B

us

••

CLKCLK

DIRDIR

••••

T1PWM_T1CMPT1PWM_T1CMP


PWM1PWM1PWM2PWM2PWM3PWM3PWM4PWM4PWM5PWM5PWM6PWM6

CAP1/QEP1CAP1/QEP1CAP2/QEP2CAP2/QEP2CAP3/QEPI1CAP3/QEPI1••

5 - 5 - 33

General-Purpose Timers General-Purpose Timers (EVA)(EVA)















MUXMUXQEPQEP

CircuitCircuit




ResetReset PIEPIE


ADC StartADC Start

Dat

a B

us

Dat

a B

us

••

CLKCLK

DIRDIR

••••





5 - 5 - 44

General-Purpose Timer Block Diagram General-Purpose Timer Block Diagram (EVA)(EVA)

16 - Bit Timer16 - Bit TimerCounterCounter

TxCMPR . 15 - 0TxCMPR . 15 - 0

GPTCONAGPTCONATxCNT . 15 - 0TxCNT . 15 - 0

CompareCompareLogicLogic

ClockClockPrescalerPrescaler

OutputOutputLogicLogic

TPS 2-0TPS 2-0

TxCON . 10 - 8TxCON . 10 - 8

PeriodPeriodRegisterRegister

ShadowedShadowed

CompareCompareRegisterRegister

ShadowedShadowed

TxPR . 15 - 0TxPR . 15 - 0

ExternalExternal

InternalInternal(HSPCLK)(HSPCLK)

TCLKS 1-0TCLKS 1-0

TxCON . 5 - 4TxCON . 5 - 4

TxPWM_TxPWM_TxCMPTxCMP

Note: x = 1 or 2Note: x = 1 or 2

QEPQEP

MMUUXX

5 - 5 - 55

Continuous-Up Counting ModeContinuous-Up Counting Mode

This example:This example:TxCON.3-2 = 00 (reload TxCMPR on underflow)TxCON.3-2 = 00 (reload TxCMPR on underflow)TxPR = 3TxPR = 3TxCMPR = 1 (initially)TxCMPR = 1 (initially)Prescale = 1Prescale = 1

0011

2233

0011

2233

0011

22

CPUCLKCPUCLK

TxCNT Reg.TxCNT Reg.

33

00

CPU writes a 2 to CPU writes a 2 to compare reg. buffercompare reg. buffer

anytime hereanytime here TxCMPR=2 is loaded hereTxCMPR=2 is loaded here

TxPWM/TxCMPTxPWM/TxCMP(active high)(active high)

(Used for Asymmetric PWM Waveforms)(Used for Asymmetric PWM Waveforms)

Seamless counting continuesSeamless counting continues Up count period is TxPR+1Up count period is TxPR+1

5 - 5 - 66

Continuous-Up/Down Counting ModeContinuous-Up/Down Counting Mode

CPUCLKCPUCLK

0011

2233

TxCNT Reg.TxCNT Reg.

2211

0011

22

00

3322

11

TxPWM/TxCMPTxPWM/TxCMP(active high)(active high)

This example:This example:TxCON.3-2 = 01 (reload TxCMPR on underflow or period match)TxCON.3-2 = 01 (reload TxCMPR on underflow or period match)TxPR = 3TxPR = 3TxCMPR = 1 (initially)TxCMPR = 1 (initially)Prescale = 1Prescale = 1

TxCMPR loadsTxCMPR loadswith a 1with a 1



(Used for Symmetric PWM Waveforms)(Used for Symmetric PWM Waveforms)

Seamless up/down repetitionSeamless up/down repetition Up/down count period is 2*TxPRUp/down count period is 2*TxPR

5 - 5 - 77

Generated Outputs and InterruptsGenerated Outputs and Interrupts

TxCMP/TxPWMTxCMP/TxPWM(active high)(active high)

Compare IntsCompare Ints

Period IntsPeriod Ints

Underflow IntsUnderflow Ints

PWM period #2PWM period #2T

imer

Cou

nte

r T

imer

Cou

nte

r V

alu

eV

alu

e

PWM period #1PWM period #1

CompComp11

Comp2Comp2

CPU Changes CPU Changes Period Reg. BufferPeriod Reg. Buffer

anytime hereanytime here

New Period is New Period is Auto-loaded on Auto-loaded on Underflow hereUnderflow here

TxCMP/TxPWMTxCMP/TxPWM(active low)(active low)

5 - 5 - 88

RegisterRegister AddressAddress DescriptionDescriptionGPTCONA 0x007400 General Purpose Timer Control Register A

T1CNT 0x007401 Timer 1 Counter Register

T1CMPR 0x007402 Timer 1 Compare Register Buffer

T1PR 0x007403 Timer 1 Period Register Buffer

T1CON 0x007404 Timer 1 Control Register




T2CON 0x007408 Timer 2 Control RegisterGPTCONB 0x007500 General Purpose Timer Control Register B









EVAEVA

EVBEVB

GP Timer RegistersGP Timer Registers

EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control RegisterEXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control Register

5 - 5 - 99

GP Timer Control Register A GP Timer Control Register A (EVA)(EVA)GPTCONA @ 0x007400GPTCONA @ 0x007400

1515 1414 1313 1212 10-910-9 8-78-7

T2STATT2STAT T1STATT1STAT T2TOADCT2TOADC T1TOADCT1TOADC

GP Timer Status (read-only)GP Timer Status (read-only)0 = counting down0 = counting down1 = counting up1 = counting up

ADC start by event of GP Timer xADC start by event of GP Timer x00: no event starts ADC00: no event starts ADC01: setting of underflow interrupt flag01: setting of underflow interrupt flag10: setting of period interrupt flag10: setting of period interrupt flag11: setting of compare interrupt11: setting of compare interrupt

reserved

Upper Byte:Upper Byte:

RESERVEDRESERVED RESERVEDRESERVED

1111

Timer 2 Compare Trip EnableTimer 2 Compare Trip EnableT2CTRIPET2CTRIPE (if EXTCONA[0]=1)(if EXTCONA[0]=1)

0 = disable0 = disable1 = enable1 = enable

Timer 1 Compare Trip EnableTimer 1 Compare Trip EnableT1CTRIPET1CTRIPE (if EXTCONA[0]=1)(if EXTCONA[0]=1)


5 - 5 - 1010

GP Timer Control Register A GP Timer Control Register A (EVA)(EVA)GPTCONA @ 0x007400GPTCONA @ 0x007400

44 3-23-2 1-01-0

T2PINT2PIN T1PINT1PIN

Compare Output EnableCompare Output Enable(reserved when EXTCONA[0]=1)(reserved when EXTCONA[0]=1)

0 = all disable (hi-impedance)0 = all disable (hi-impedance)1 = all enable1 = all enable

TxPWM/TxCMP Output Pin ConditioningTxPWM/TxCMP Output Pin Conditioning00: forced low00: forced low01: active low01: active low10: active high10: active high11: forced high11: forced high

RESERVEDRESERVED

Lower Byte:Lower Byte:

66

TCOMPOETCOMPOE RESERVEDRESERVED

55

Timer 2 Compare Output EnableTimer 2 Compare Output EnableT2CMPOET2CMPOE (if EXTCONA[0]=1)(if EXTCONA[0]=1)

0 = disable (hi-Z)0 = disable (hi-Z)1 = enable1 = enable

Timer 1 Compare Output EnableTimer 1 Compare Output EnableT1CMPOET1CMPOE (if EXTCONA[0]=1)(if EXTCONA[0]=1)

0 = disable (hi-Z)0 = disable (hi-Z)1 = enable1 = enable

5 - 5 - 1111

Timer Control Register Timer Control Register (EVA)(EVA)T1CON @ 0x007404 / T2CON @ 0x007408T1CON @ 0x007404 / T2CON @ 0x007408

FREEFREE

1515 1414 1313 1212 1010 88

SOFTSOFT TMODE0TMODE0 TPS0TPS0TPS1TPS1TPS2TPS2

991111

Timer Clock PrescaleTimer Clock Prescale

000: 000: 1 1 100: 100: 16 16001: 001: 2 2 101: 101: 32 32010: 010: 4 4 110: 110: 64 64011: 011: 8 8 111: 111: 128 128


Count Mode SelectCount Mode Select00 = stop/hold00 = stop/hold01 = continuous-up/down01 = continuous-up/down10 = continuous-up10 = continuous-up11 = directional-up/down11 = directional-up/down

reserved

Emulation Halt BehaviorEmulation Halt Behavior00 = stop immediately00 = stop immediately01 = stop at end of period01 = stop at end of period1x = free run (do not stop)1x = free run (do not stop)

TMODE1TMODE1

5 - 5 - 1212

Timer Control Register Timer Control Register (EVA)(EVA)T1CON @ 0x007404 / T2CON @ 0x007408T1CON @ 0x007404 / T2CON @ 0x007408

T2SWT1T2SWT1

77 66 55 44 22 00

TENABLETENABLE TCLKS1TCLKS1 TCLKS0TCLKS0 TCLD1TCLD1 SELT1PRSELT1PRTECMPRTECMPRTCLD0TCLD0

1133


Start with Timer 1Start with Timer 1

0 = use own TENABLE0 = use own TENABLE1 = use Timer 1 TENABLE1 = use Timer 1 TENABLE

(bit reserved in T1CON)(bit reserved in T1CON)

Timer EnableTimer Enable

0 = timer disable0 = timer disable1 = timer enable1 = timer enable

Timer Clock SourceTimer Clock Source

00 = internal (HSPCLK)00 = internal (HSPCLK)01 = external TCLKIN pin01 = external TCLKIN pin10 = reserved10 = reserved11 = QEP11 = QEP

Compare Register Reload ConditionCompare Register Reload Condition

00 = when counter equals zero (underflow)00 = when counter equals zero (underflow)01 = when counter equals zero or period reg01 = when counter equals zero or period reg10 = immediately10 = immediately11 = reserved11 = reserved

Timer Compare Operation EnableTimer Compare Operation Enable


Period Register SelectPeriod Register Select

0 = use own per. reg.0 = use own per. reg.1 = use Timer 1 per. reg1 = use Timer 1 per. reg (bit reserved in T1CON)(bit reserved in T1CON)

5 - 5 - 1313

Extension Control Register A Extension Control Register A (EVA)(EVA)EXTCONA @ 0x007409EXTCONA @ 0x007409

INDCOEQEPIQUALQEPIEEVSOCEreserved

11 00223315-415-4

Independent CompareIndependent CompareOutput Enable ModeOutput Enable Mode


QEP Index Enable0 = disable1 = enable

CAP3/QEPI IndexQualification Mode

0 = off1 = on

EV Start-of-Conversion Output Enable

0 = disable1 = enable

5 - 5 - 1414

GP Timer Compare PWM ExerciseGP Timer Compare PWM Exercise

Symmetric PWM is to be generated as follows:Symmetric PWM is to be generated as follows: 50 kHz carrier frequency50 kHz carrier frequency Timer counter clocked by 30 MHz external clockTimer counter clocked by 30 MHz external clock PLL multiply by 10/2PLL multiply by 10/2 HSPCLK : divide by 2HSPCLK : divide by 2 Use the Use the 1 prescale option1 prescale option 25% duty cycle initially25% duty cycle initially Use GP Timer Compare 1 with PWM output active highUse GP Timer Compare 1 with PWM output active high T2PWM/T2CMP pins forced lowT2PWM/T2CMP pins forced low

Determine the initialization values needed in the GPTCONA, Determine the initialization values needed in the GPTCONA, T1CON, T1PR, and T1CMPR registersT1CON, T1PR, and T1CMPR registers

5 - 5 - 1515

GP Timer Compare PWM Exercise SolutionGP Timer Compare PWM Exercise Solution

GPTCONA = GPTCONA = (xxx0000001000010)b (xxx0000001000010)b = = 0x00420x0042

T1CON =T1CON = (xx00100001000010)b = 0x0842 (xx00100001000010)b = 0x0842all x’s assigned all x’s assigned a value of 0a value of 0

T1CMPR = (100% - duty cycle)*T1PR = 0.75*750 = 563T1CMPR = (100% - duty cycle)*T1PR = 0.75*750 = 563

T1PR =T1PR =carrier periodcarrier period

timer periodtimer period 22221111

13.34 ns13.34 ns20 20 ss.... = 750= 750==

PLLCR = 0x0APLLCR = 0x0A

HISPCP = 1HISPCP = 1

5 - 5 - 1616

EVAIMRA Register EVAIMRA Register @ 0x742C@ 0x742C

--

1515 1414 1313 1212 1010 88

-- -- -- -- T1CINTT1CINTT1UFINTT1UFINTT1OFINTT1OFINT

991111

Interrupt Mask BitsInterrupt Mask Bits

0 = disable interrupt0 = disable interrupt

1 = enable interrupt1 = enable interrupt

BitBit EventEvent

10:10: Timer 1 OverflowTimer 1 Overflow9:9: Timer 1 UnderflowTimer 1 Underflow8:8: Timer 1 Compare matchTimer 1 Compare match7:7: Timer 1 Period matchTimer 1 Period match3:3: Compare Unit 3, Compare matchCompare Unit 3, Compare match2:2: Compare Unit 2, Compare match Compare Unit 2, Compare match 1:1: Compare Unit 1, Compare matchCompare Unit 1, Compare match0:0: Power Drive Protect input, EVAPower Drive Protect input, EVA

T1PINTT1PINT

77 66 55 44 22 00

-- -- -- CMP3INTCMP3INT PDPINTPDPINTCMP1INTCMP1INTCMP2INTCMP2INT

1133

5 - 5 - 1717

EVAIMRB Register EVAIMRB Register @ 0x742D@ 0x742D

--

1515 1414 1313 1212 1010 88

-- -- -- -- ------

991111




BitBit EventEvent

3:3: Timer 2 Overflow Timer 2 Overflow 2:2: Timer 2 Underflow Timer 2 Underflow 1:1: Timer 2 Compare matchTimer 2 Compare match0:0: Timer 2 Period matchTimer 2 Period match

--

77 66 55 44 22 00

-- -- -- T2OFINTT2OFINT T2PINTT2PINTT2CINTT2CINTT2UFINTT2UFINT

1133

5 - 5 - 1818

EVAIMRC Register EVAIMRC Register @ 0x742E@ 0x742E

--

1515 1414 1313 1212 1010 88

-- -- -- -- ------

991111




BitBit EventEvent2:2: Capture Unit 3 input Capture Unit 3 input1:1: Capture Unit 2 input Capture Unit 2 input0:0: Capture Unit 1 input Capture Unit 1 input

--

77 66 55 44 22 00

-- -- -- -- CAP1INTCAP1INTCAP2INTCAP2INTCAP3INTCAP3INT

1133

5 - 5 - 1919

EVAIFRx RegisterEVAIFRx Register

--

1515 1414 1313 1212 1010 88

-- -- -- -- ------

991111

Read:Read:0 = no event0 = no event1 = flag set1 = flag set

--

77 66 55 44 22 00

-- -- -- -- CAP1INTCAP1INTCAP2INTCAP2INTCAP3INTCAP3INT

1133

--

1515 1414 1313 1212 1010 88

-- -- -- -- ------

991111

--

77 66 55 44 22 00

-- -- -- T2OFINTT2OFINT T2PINTT2PINTT2CINTT2CINTT2UFINTT2UFINT

1133

--

1515 1414 1313 1212 1010 88

-- -- -- -- T1CINTT1CINTT1UFINTT1UFINTT1OFINTT1OFINT

991111

T1PINTT1PINT

77 66 55 44 22 00

-- -- -- CMP3INTCMP3INT PDPINTPDPINTCMP1INTCMP1INTCMP2INTCMP2INT

1133

EVAIFRAEVAIFRA@@ 0x742F0x742F

EVAIFRAEVAIFRA@@ 0x74310x7431

EVAIFRBEVAIFRB@@ 0x74300x7430

Write:Write:0 = no effect0 = no effect1 = reset flag1 = reset flag

5 - 5 - 2020

Lab 5: Let’s play a tune !Lab 5: Let’s play a tune !

Aim:Aim:• Exercise with Event Manager A General Purpose Timer 1• Use Lab 4 as a starting point. In Lab 4 we initialised Core

Timer 0 to request an interrupt every 50 ms. We can use this ISR to load the next note to T1PWM.

• Timer1 output ‘T1PWM’ is connected to a loudspeaker

Basic Tune Frequencies:Basic Tune Frequencies: c1 : 264 Hz d : 297 Hz e : 330 Hz f : 352 Hz g : 396 Hz a : 440 Hz h : 495 Hz c2 : 528 Hz

5 - 5 - 2121

New Registers involved in Lab 5:New Registers involved in Lab 5:• General Purpose Timer Control A : GPTCONA• Timer 1 Control Register : T1CON• Timer 1 Period Register : T1PR• Timer 1 Compare Register : T1CMPR• Timer 1 Counter Register : T1CNT• EV- Manager A Interrupt Flag A : EVAIFRA• EV- Manager A Interrupt Flag B : EVAIFRB• EV-Manager A Interrupt Flag C : EVAIFRC• EV- Manager A Interrupt Mask A : EVAIMRA• EV- Manager A Interrupt Mask B : EVAIMRB• EV- Manager A Interrupt Mask C : EVAIMRC• Interrupt Flag Register : IFR• Interrupt Enable Register : IER

5 - 5 - 2222

Compare Units Compare Units (EVA)(EVA)















MUXMUXQEPQEP

CircuitCircuit




ResetReset PIEPIE


ADC StartADC Start

Dat

a B

us

Dat

a B

us

••

CLKCLK

DIRDIR

••••





5 - 5 - 2323

What is Pulse Width Modulation? What is Pulse Width Modulation?

PWM is a scheme to represent a signal as a PWM is a scheme to represent a signal as a sequence of pulsessequence of pulses fixed carrier frequencyfixed carrier frequency fixed pulse amplitudefixed pulse amplitude pulse width proportional to instantaneous pulse width proportional to instantaneous

signal amplitudesignal amplitude PWM energy PWM energy original signal energy original signal energy

Differs from PAM (Pulse Amplitude Differs from PAM (Pulse Amplitude Modulation)Modulation) fixed width, variable amplitudefixed width, variable amplitude

5 - 5 - 2424

Tt

PWM representationPWM representation PAM representationPAM representationT

t

tOriginal SignalOriginal Signal

PWM Signal RepresentationPWM Signal Representation

same areas (energy)same areas (energy)

5 - 5 - 2525

Why Use PWM in Digital Motor Control?Why Use PWM in Digital Motor Control?

Desired motor phase currents or voltages are knownDesired motor phase currents or voltages are known Power switching devices are transistorsPower switching devices are transistors

Difficult to control in proportional regionDifficult to control in proportional region Easy to control in saturated regionEasy to control in saturated region

PWM is a digital signal PWM is a digital signal easy for DSP to output easy for DSP to output

PWM approx.PWM approx.of desired of desired signalsignal

DC SupplyDC Supply

DesiredDesiredsignal tosignal tomotor phasemotor phase

??

DC SupplyDC Supply

Unknown Gate SignalUnknown Gate Signal Gate Signal Known with PWMGate Signal Known with PWM

PWMPWM

5 - 5 - 2626

Asymmetric PWM WaveformAsymmetric PWM Waveform

CounterCounter

PeriodPeriod

CompareCompare

TTpwmpwm / T / Tcmp cmp PinPin

(active high)(active high) Caused by Period matchCaused by Period match(toggle output in Asym mode only)(toggle output in Asym mode only)

Caused by Compare matchCaused by Compare match

TTPWMPWM

5 - 5 - 2727

Symmetric PWM WaveformSymmetric PWM Waveform

CounterCounter

CompareCompare

PeriodPeriod

TTPWMPWM

TTPWMPWM /T /TCMPCMP Pin Pin

(active high)(active high)

InterruptsInterrupts

PeriodCompareCounter

General Purpose Timer

TPWM/TCMP Pin

CompareCompareCompare

Full Compare UnitsPWM1PWM2PWM3PWM4PWM5PWM6

5 - 5 - 2828

PowerSwitchingDevices

Three phaseoutputs which go to the motorterminals

Upper & lowerdevices can notbe turned on simultaneously(dead band)

PWM signal isapplied betweengate and source

DC bus capacitor

Voltage source inverter componentsVoltage source inverter components

5 - 5 - 2929

Compare Units Block Diagram Compare Units Block Diagram (EVA)(EVA)

GP Timer 1GP Timer 1CounterCounter

ACTRA . 11 - 0ACTRA . 11 - 0

T1CNT . 15 - 0T1CNT . 15 - 0

CompareCompareLogicLogic

OutputOutputLogicLogic

FCOMPOEFCOMPOECOMCONA . 9COMCONA . 9

Dead BandDead BandUnitsUnits

ShadowedShadowed

CompareCompareAction ControlAction Control

RegisterRegister

ShadowedShadowed

CMPRx . 15 - 0CMPRx . 15 - 0

PWMy, y+1PWMy, y+1

CompareCompareRegisterRegister

DBTCONA . 11 - 2DBTCONA . 11 - 2

Note: x = 1, 2, 3; y = 1, 3, 5Note: x = 1, 2, 3; y = 1, 3, 5

5 - 5 - 3030

Compare Unit Registers Compare Unit Registers

COMCONACOMCONA 0x0074110x007411 Compare Control Register ACompare Control Register A

ACTRAACTRA 0x0074130x007413 Compare Action Control Register ACompare Action Control Register A

DBTCONADBTCONA 0x0074150x007415 Dead-Band Timer Control Register A Dead-Band Timer Control Register A

CMPR1CMPR1 0x0074170x007417 Compare Register 1Compare Register 1



RegisterRegister AddressAddress DescriptionDescription

COMCONBCOMCONB 0x0075110x007511 Compare Control Register BCompare Control Register B

ACTRBACTRB 0x0075130x007513 Compare Action Control Register BCompare Action Control Register B

DBTCONBDBTCONB 0x0075150x007515 Dead-Band Timer Control Register B Dead-Band Timer Control Register B




EVAEVA

EVBEVB

EXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control RegisterEXTCONA 0x007409 / EXTCONB 0x007509 ;Extension Control Register

5 - 5 - 3131

Compare Control Register Compare Control Register (EVA)(EVA)COMCONA @ 0x007411COMCONA @ 0x007411

CENABLECENABLE

1515 1414 1313 1212 1010 88

CLD1CLD1 CLD0CLD0 SVENABLE ACTRLD1ACTRLD1 PDPINTAPDPINTAFCOMPOEFCOMPOEACTRLD0ACTRLD0

991111

Compare EnableCompare Enable

0 = disable0 = disable 1 = enable1 = enable

CMPRx reload conditionCMPRx reload condition

00 = when T1CNT = 000 = when T1CNT = 001 = when T1CNT = 0 or T1PR01 = when T1CNT = 0 or T1PR10 = immediately10 = immediately11 = reserved11 = reserved

Space Vector PWM 0 = SV disable 1 = SV enable

ACTRA reload conditionACTRA reload condition

00 = when T1CNT = 000 = when T1CNT = 001 = when T1CNT = 0 or T1PR01 = when T1CNT = 0 or T1PR10 = immediately10 = immediately11 = reserved11 = reserved


PDPINT StatusPDPINT Status

0 = low0 = low1 = high1 = high

Full Compare Output EnableFull Compare Output Enable(reserved when EXTCONA[0]=1)(reserved when EXTCONA[0]=1)

0 = all disable (hi-impedance)0 = all disable (hi-impedance)1 = all enable1 = all enable

5 - 5 - 3232

Compare Control Register Compare Control Register (EVA)(EVA)COMCONA @ 0x007411 COMCONA @ 0x007411

77 66 55 44 22 1133


reserved RESERVEDRESERVED RESERVEDRESERVED RESERVEDRESERVEDRESERVEDRESERVED RESERVEDRESERVED RESERVEDRESERVED reserved

00

Full Compare 1Full Compare 1 Trip EnableTrip Enable C1TRIPEC1TRIPE

(if EXTCONA[0]=1)(if EXTCONA[0]=1)


Full Compare 2Full Compare 2 Trip EnableTrip Enable C2TRIPEC2TRIPE(if EXTCONA[0]=1)(if EXTCONA[0]=1)


Full Compare 3Full Compare 3 Trip EnableTrip Enable C3TRIPEC3TRIPE(if EXTCONA[0]=1)(if EXTCONA[0]=1)


Full Compare 1Full Compare 1 Output EnableOutput Enable FCMP1OEFCMP1OE(if EXTCONA[0]=1)(if EXTCONA[0]=1)






5 - 5 - 3333



11 00223315-415-4

Independent CompareOutput Enable Mode




0 = off1 = on



5 - 5 - 3434

Compare Action Control Register Compare Action Control Register (EVA)(EVA)ACTRA @ 0x007413ACTRA @ 0x007413

CMP4ACT1

7 6 5 4 2 0

CMP4ACT0 CMP3ACT1 CMP3ACT0 CMP2ACT1 CMP1ACT0CMP1ACT1CMP2ACT0

13

Pin Action on Compare: CMPyACT1-0

00 force low 01 active low 10 active high 11 forced high

SVRDIR

15 14 13 12 10 8

D2 D1 D0 CMP6ACT1 CMP5ACT0CMP5ACT1CMP6ACT0

911

Basic Space Vector Bitscan write as 0 when SV not in use

SV Rotation Directioncan write as 0 when SV not in use

5 - 5 - 3535

Motivation for Dead-BandMotivation for Dead-Band

to motor phase

supply rail

Gate Signals areComplementary PWM

Transistor gates turn on faster than they shut off Short circuit if both gates are on at same time!

5 - 5 - 3636

Dead-Band Functionality Dead-Band Functionality (EVA)(EVA)

PHx

DT

dead time

Clock

DTPHx

Asymmetric PWM Example

DTPHx_

4-bit period

Prescaler

4-bitCounter

ENA

reset

HSPCLK

comparator

DTPHx

DTPHx_

PHx

DT

edgedetect

DBTCONA . 4 - 2

DBTCONA . 11 - 8

5 - 5 - 3737

Dead-Band Timer Control Register Dead-Band Timer Control Register (EVA)(EVA)DBTCONA @ 0x007415DBTCONA @ 0x007415

EDBT3

7 6 5 4 2 0

EDBT2 EDBT1 DBTPS2 DBTPS1 reservedreserved

13

15 14 13 12 10 8

DBT3 DBT0DBT1DBT2

911

DB Timer Enable0 = disable1 = enable

DB Timer Prescaler

000 = 1 100 = 16001 = 2 101 = 32

010 = 4 110 = 32 011 = 8 111 = 32

DB Timer Period

dead time = DB period * DB prescaler * CPUCLK period

reserved reserved reserved reserved

DBTPS0

5 - 5 - 3838

Capture Units Capture Units (EVA)(EVA)

PWM Circuits

PWM Circuits

PWM Circuits

Output Logic

Output Logic

Output Logic

GP Timer 1 Compare

GP Timer 1

GP Timer 2 Compare

GP Timer 2

Compare Unit 1

Compare Unit 2

Compare Unit 3

Capture Units

MUXQEP

Circuit

Output Logic

Output Logic

EV Control Registers / Logic

Reset PIE

TCLKINA / TDIRA/2

ADC Start

Dat

a B

us

•

CLK

DIR

••

T1PWM_T1CMP

T2PWM_T2CMP

PWM1PWM2PWM3PWM4PWM5PWM6

CAP1/QEP1CAP2/QEP2CAP3/QEPI1•

5 - 5 - 3939


Capture units timestamp transitions on Capture units timestamp transitions on capture input pinscapture input pins

Three capture units (per event manager) - Three capture units (per event manager) - each associated with a capture input pineach associated with a capture input pin

Timer

TimestampValues

Trigger .

5 - 5 - 4040

Some Uses for the Capture UnitsSome Uses for the Capture Units

Synchronized ADC start with capture event

Problem: At low speeds, calculation of speed based on a measured position change at fixed time intervals produces large estimate errorsAlternative: Estimate the speed using a measured time interval at fixed position intervals

Signal from oneQuadratureEncoder Channel

Low speed velocity estimation from incr. encoder:

Measure the time width of a pulse

vk x

tk - tk-1

vk txk - xk-1

x

5 - 5 - 4141

Capture Units Block Diagram Capture Units Block Diagram (EVA)(EVA)

Can latch on:• rising edge• falling edge• both

TTL Signalmin. valid width:2 CPUCLK lo2 CPUCLK hi

GP Timer 1Counter

T1CNT . 15 - 0

EdgeDetect

CAP3TOADC

CAP1,2,3

MUX

GP Timer 2Counter

T2CNT . 15 - 0

CAPCONA . 10 - 9Enable

CAPCONA . 14 -12

2-Level DeepFIFO

/ 3

.CAPCONA . 8

Edge Select

CAPCONA . 7 - 2

CAPCONA . 15CAPRESET

ADC Start(CAP 3)

CAPFIFOA . 13 - 8

CAPxFIFO Status

RS

5 - 5 - 4242

Capture Units RegistersCapture Units RegistersRegister Address DescriptionCAPCONA 0x007420 Capture Control Register A

CAPFIFOA 0x007422 Capture FIFO Status Register A

CAP1FIFO 0x007423 Two-Level Deep FIFO 1 Stack



CAP1FBOT 0x007427 Bottom Register of FIFO 1


CAP3FBOT 0x007429 Bottom Register of FIFO 3CAPCONB 0x007520 Capture Control Register B

CAPFIFOB 0x007522 Capture FIFO Status Register B







EVA

EVB

EXTCONA 0x007409 / EXTCONB 0x007509 ;Ext. Cntrl Reg.

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Capture Control Register Capture Control Register (EVA)(EVA)CAPCONA @ 0x007420CAPCONA @ 0x007420

14-13 12 10 891115

CAP3EN reserved CAP3TSEL CAP3TOADCCAP12TSELCAPRES CAPQEPN

Capture Reset (not latched) 0 = clear all result FIFO’s and

CAPFIFO register 1 = no action

Unit 1 & 2 Control00 = disable01 = enable for capture10 = reserved11 = enable for QEP

Unit 3 Control 0 = disable 1 = enable

Timer Select0 = GP Timer 21 = GP Timer 1

ADC Start0 = no action1 = CAP3INT flag

5-4 1-03-27-6

CAP1EDGE CAP2EDGE CAP3EDGE reserved

Edge Detection Control

00 = no detection 10 = falling edge01 = rising edge 11 = both edges

5 - 5 - 4444

reserved

Capture FIFO Status Register Capture FIFO Status Register (EVA)(EVA)CAPFIFOA @ 0x007422CAPFIFOA @ 0x007422

13-12 9-811-10

CAP3FIFO CAP2FIFO CAP1FIFO

FIFOx Status:00 = empty01 = one entry 10 = two entries11 = three entries attempted,

1st entry lost

CAPxFIFO bits are automatically adjusted on a capture or FIFO read

15-14

reserved

7-0

5 - 5 - 4545

What is an Incremental Quadrature What is an Incremental Quadrature Encoder?Encoder?

A digital (angular) position sensorA digital (angular) position sensor

slots spaced deg. apart

photo sensors spaced /4 deg. apart

light source (LED)

shaft rotation

Ch. A

Ch. B

Quadrature Output from Photo Sensors

/4

Incremental Optical Encoder

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Quadrature Encoder Pulse Quadrature Encoder Pulse (EVA)(EVA)

PWM Circuits

PWM Circuits

PWM Circuits

Output Logic

Output Logic

Output Logic

GP Timer 1 Compare

GP Timer 1

GP Timer 2 Compare

GP Timer 2

Compare Unit 1

Compare Unit 2

Compare Unit 3

Capture Units

MUXQEP

Circuit

Output Logic

Output Logic

EV Control Registers / Logic

Reset PIE

TCLKINA / TDIRA/2

ADC Start

Dat

a B

us

•

CLK

DIR

••

T1PWM_T1CMP

T2PWM_T2CMP

PWM1PWM2PWM3PWM4PWM5PWM6

CAP1/QEP1CAP2/QEP2CAP3/QEPI1•

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How is Position Determined from How is Position Determined from Quadrature Signals?Quadrature Signals?

Ch. A

Ch. B

(00) (11)(10) (01)

(A,B) =

00

01

11

10

QuadratureDecoder

State Machine

incrementcounter

decrementcounter

Position resolution is /4 degrees.

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Incremental Encoder Connections (EVA)Incremental Encoder Connections (EVA)

GP Timer 2 selected as GP Timer 2 selected as pulse counterpulse counter

Timer Prescaler bypassed Timer Prescaler bypassed (i.e. Prescale always 1)(i.e. Prescale always 1)

Ch. A

Ch. BCAP1/QEP1

CAP2/QEP2

QEPdecoder

logic

GP Timer 2

CLK DIR

..

Index

CA

P3/

QE

PI

QEPIE

QEPIQUAL

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1 02315-4

Independent CompareOutput Enable Mode




0 = off1 = on



5 - 1 texas instruments incorporated module 5 : event manager c28x 32-bit-digital signal controller...

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