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Input / Output

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Program-Controlled I/O

Keyboard Buffer Register

DATAIN Status Flag

SIN

Display Buffer Register

DATAOUT Status Flag

SOUT

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Program-Controlled I/O

Bus

Processor

Keyboard

DATAIN

SIN

Display

DATAOUT

SOUT

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Memory-Mapped I/O

Memory addresses used to refer to peripheral device buffer registers DATAIN DATAOUT

Device status registers INSTATUS

SIN OUTSTATUS

SOUT

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Program-Controlled I/O

Move #LOC,R0READ TestBit #3,INSTATUS Branch=0 READ MoveByte DATAIN,(R0)ECHO TestBit #3,OUTSTATUS Branch=0 ECHO MoveByte (R0),DATAOUT Compare #CR,(R0)+ Branch≠0 READ

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I/O Interface (Input)

Address LinesData LinesControl Lines

Bus

AddressDecoder

ControlCircuits

Data & StatusRegisters I/O Interface

Input Device

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I/O Interface

STATUS DIRQ KIRQ SOUT SIN

CONTROL

DATAOUT

DATAIN

DEN KEN

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Interrupts

Interrupt-request line Interrupt-request signal Interrupt-acknowledge signal

Interrupt-service routine Similar to subroutine May have no relationship to program being executed at

time of interrupt Program info must be saved Interrupt latency

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Handling Interrupts

Many situations where the processor should ignore interrupt requests Interrupt-disable Interrupt-enable

Typical scenario Device raises interrupt request Processor interrupts program being executed Processor disables interrupts and acknowledges interrupt Interrupt-service routine executed Interrupts enabled and program execution resumed

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Handling Multiple Devices

How can the processor recognize the device requesting an interrupt?

How can the processor obtain the starting address of the appropriate interrupt-service routine?

Should a device be allowed to interrupt the processor while another interrupt is being serviced?

How should two or more simultaneous interrupt requests be handled?

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Handling Multiple Devices

Polling Interrupt-service routine checks IRQ bits

DIRQ, KIRQ Appropriate subroutine called to provide requested service

Vectored Interrupts Device requesting interrupt may identify itself directly to

the processor Special code over bus Code represents part of address for interrupt-service

routine Interrupt vector

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Interrupt Priority

Multi-level priority organization During execution of interrupt-service routine

Disable interrupts from devices at the same level priority or lower

Continue to accept interrupt requests from higher priority devices

Privileged instructions executed in supervisor mode Controlling device requests

Interrupt-enable KEN, DEN

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Interrupt Priority Schemes

Proc

esso

r

Device 1 Device 2 Device p

Priority arbitrationcircuit

...INTA1

INTR1 INTRp

INTApINTA2

INTR2Pr

oces

sor

Device 1 Device 2 Device p...INTA

INTR

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Interrupt Priority Groups

Proc

esso

r

Device Device

Priority arbitrationcircuit

INTA1

INTR1

INTRp

INTAp

.

.

.

Device Device...

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Exceptions

Any event that causes an interrupt Recovery from errors

Illegal instructions Divide by zero

Debugging Trace mode Breakpoints

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Operating Systems

Coordinate all activities within a computer Make extensive use of interrupts

Perform (coordinate) I/O Communicate with user programs Control execution of user programs

Assign priorities Switch between programs (multi-tasking) Implement security and protection

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68000 Interrupt Structure

8 interrupt priority levels 7 highest (non-maskable interrupt)

Priority groups (similar to Fig 4.8b) Interrupt saves PC and PS to processor stack 256 interrupt vectors

32-bit address of interrupt-service routine

T S X N Z V CPS

Trace

Supervisor

InterruptPriority

ConditionCodes

15 13 10 8 4 3 2 1 0

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Direct Memory Access (DMA)

Polling or interrupt driven I/O incurs considerable overhead Multiple program instructions Saving program state Incrementing memory addresses Keeping track of word count

DMA Transfer large blocks of data directly between an

external device and memory Without continuous intervention by the processor

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DMA Controller

Part of the I/O device interface DMA Channels

Performs functions that would normally be carried out by the processor Provides memory address Bus signals that control transfer Keeps track of number of transfers

Under control of the processor

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DMA Transfer

Processor sends Starting address Number of words in block Direction of transfer

DMA controller Performs requested operation Interrupts processor when done

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Example System

Processor MainMemory

Disk/DMAController

DMAController Printer Keyboard

Disk Disk NetworkInterface

System Bus

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Access Priority

DMA devices given higher priority than processor DMA controller “steals” cycles from processor

Top priority given to high-speed peripherals Disk Network interface Graphics display

DMA controller can be given exclusive access to transfer block of data without interruption Block (burst) mode

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Data Buffers

Most DMA controllers incorporate data storage buffers

Network interface example DMA controller reads block of data from main memory

Burst mode Stored in data buffer Data transmitted from buffer over the network

Network speed

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Bus Arbitration

Resolves conflicts when multiple controllers try to use the bus at the same time

Bus Master Device that currently has use of the bus

Centralized arbitration Single entity controls bus access

Distributed arbitration All devices participate in selection of next bus master

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Centralized Arbitration

Daisy Chain Bus-Request (BR) Bus-Grant (BGi) Bus-Busy (BBSY)

Processor

DMAController

1

DMAController

2BG1 BG2

BR

BBSY

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Centralized Arbitration

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Questions?