555 Timer

Monostable & Astable operations

Suchendranath Popuri

Internal Diagram of 555 timer

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Functions

■ The voltage divider has three equal 5K resistors. It divides the input

voltage (Vcc) into three equal parts.

■ The two comparators are op-amps which compare the voltages at

their inputs and saturate depending upon which is greater.

■ The flip-flop is a bi-stable device. It generates two values, a “high”

value equal to Vcc and a “low” value equal to 0V.

■ The transistor is being used as a switch, it connects pin 7 (discharge)

to ground when it is closed

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Astable operation

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Astable Mode

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Astable Mode

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Steps

■ Assume output(Q) is initially ‘1’

■ This means,Qbar=0 and transistor Q14 is OFF

■ Capacitor C will charge towards Vcc through Ra and Rb

■ When C voltage crosses Vcc/3,S=0.this however has NO effect on the output since S-0,R=0 maintains the previous state.

■ But when C voltage crosses 2Vcc/3,output of upper comparator becomes ‘1’,resetting the flip flop.

■ Thus output(Q) becomes ‘0’,Qbar =1 which turns ON Q14

■ Now,C has a path to discharge through Rb (through Q14)(current from Vcc also flows through Ra and Q14 to GND)

■ C voltage decreases exponentially till it becomes just below Vcc/3.At this instant,Lower comparator is triggered and FF is set(S=1)

■ Hence output(Q) becomes high again.Qbar becomes ‘0’ which turns OFF Q14.Hence Capacitor cannot discharge,but starts charing towards Vcc through Ra and Rb. Cycle repeats

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Astable-Time period

Charging Interval: TH RA RB C ln 2

Discharging Interval: TL RBC ln 2

Period of Oscillation: TH TL RA 2RB C ln 2

Frequency of Oscillation: 1

T

1

RA 2RB C ln 2

Duty Cycle: d =TH

T100%

RA RB

RA 2RB100%

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Monostable Operation

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Monostable mode

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Monostable mode

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Steps

■ Initially 555 is reset,Q=‘0’, Qb=‘1’.Hence output(Q)=‘0’

■ Pin no.6 is almost at GND since Qb turns ON Transistor Q14 and drives it to saturation

■ Trigger input(Pin no2) is held at some positive value > Vcc/3,say 2 V

■ Hence S=0,R=0 and the circuit is stable at output logic ‘0’(0 volts)

■ When a negative trigger is applied at 2,S becomes logc ‘1’.FF is set,i.e output(pin no3) goes high.

■ Now,Qbar being ‘0’ turns offf Transistor Q14

■ So,capacitor C,being connected to Vcc through R starts charging towards Vcc

■ The moment capacitor voltage > 2Vcc/3,R becomes ‘1’,resetting the FF.Hence output(Q) becomes ‘0’.

■ Qbar becomes ‘1’ which quickly tutns ON the transistor and discharges the capacitor voltage

■ Circuit stays in ‘0’ untill a trigger comes again

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The pulse width of time t, which is the time it takes to charge C to 2/3 of the

supply voltage, is given by

Monostable mode

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RCRCt 1.1)3ln(