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Presentation on Amplifier Design and Performance Testing

Amplifier Design & Performance Testing ��

1

Gaining the Wireless Edge 2000Techniques for RF and High-Frequency Wireless Design

Amplifier Design &Performance Testing

After system design & design partitioning, the next step in our design flow is to create the circuitdesign for the Power Amplifier. We’ll design a PA here with the assistance of two of theDesignGuides (Passive Circuit and Power Amplifier), which are new in ADS 1.3.


2

Agenda

•EDGE Amplifier Specifications

•Step-by-Step Procedure to Design Power Amplifier

•Driver Amplifier Design

•Matching Network Design Simulation Results

•Power Amplifier Design

•Calculating Load-Line Resistance from IV Curves

•Maximize Power: Matching to the Load-Line Impedance

•Simulation: Gain, input Match, and output Load Resistance

•Comparison with Measurement Data


3

Synthesis, Utilitiesand Optimization

Synthesis, Utilitiesand Optimization

DESIGN

FEEDBACK

DESIGN

FEEDBACK

Data ProcessingData Processing

System LibrarySystem Library

Vendor LibrariesVendor Libraries

Custom ModelsCustom Models

SupportingInfrastructure

INSTRUMENTATION

INSTRUMENTATION

Logical Design

Physical DesignManufacturingManufacturing

System DesignSystem Design

Circuit DesignCircuit Design

LayoutLayout

ConceptConcept

EM Visualization &Optimization

EM Visualization &Optimization

Design Flow Steps Illustrated in this Module

EM-SimulationEM-Simulation

Design LibrariesDesign Libraries

Transmission Line ModelsTransmission Line Models

Simulation DeliverableHardware Deliverable

CustomersCustomers

Foundry LibrariesFoundry Libraries

Layout FootprintsLayout Footprints

During this module, we’ll be focusing on taking a design from the System Level and thespecifications allocated and create a circuit design. The particular parts of the design flowhighlighted will be addressed in this paper.


4

EDGE Power Amplifier Specifications

• Frequency 1850 -1910 MHz

• Nominal Gain 23 dB

• Output Noise Power 140 dBm/Hz

• Input Impedance VSWR<2:1 (50 ohms)

• Stability (Loaded VSWR<2:1)

• All Spurious < -70 dBc

• Harmonics <30 dBc for 2fo and 3fo

• Pmax @ 1dB GC 800mW or +29 dBm

• PAE at Pmax +6.5V >30%

• EVM 12.5% (RMS) max

• Noise Figure 6 dB max

• Vsupply +/-6.5 VDC

Here are the specifications obtained after the system design partitioning. For this paper, we’regoing to focus on the specifications in italics.

Since we are concerned with getting maximum power from our device, the device will exhibit non-linear characteristics which must be managed to meet specifications, these include PAE &Harmonic levels.


5

PA Design Partitioning

•Overall Gain - 23 dB

•ATF-21170 - Driver Amplifier Stage - 13 dB gain

•MGF-2430A - Power Amplifier Stage - 10 dB gain

DriverStage

PowerStage

DC/Operating Point(Load Pull vs. Load Line)

Matching Networks(Gain, Match, NF, Stability)

Performance Testing(Simulation)

Layout(Build)

Measure(Model Validation)

The design starts with budgeting and device selection to achieve the final goals.

The optimum number of stages are determined for the required gain. The final stage device isselected to achieve the required output power, whereas the preceding stage device is selected todrive the final power stage. If a high degree of linearity is desired, the driver stage should be chosenso that when the final stage is driven into compression, the driver stage is several dB below itscompression point. The proper bias point is selected and impedance matching is then carried out tocomplete the design.

Power amplification in RF frequency bands can be accomplished by using any one of many differentdevices, e.g. Bipolar Junction Transistors (BJT), Metal Oxide Semiconductor Field Effect Transistor(MOSFET), GaAs Metal Semiconductor Field Effect Transistor (MESFET), Hetro Junction BipolarTransistors (HBT), etc. At 1.9 GHz BJT, HBT, and MESFET are good candidates for the requiredgain and output power.

The transistors selected for this design were MESFETs MGF 2430A for the output power stage andATF 21170 for the driving stage. MGF2430A is a good candidate for this amplifier design becauseit is capable of giving +29 dbm output power with +10db gain. ATF21170 MESFET providesmaximum available gain of +13 dB at the required frequency and therefore selected for thisapplication.


6

?

Challenges Using Today’s EDA Software Effectively

•Flexible & comprehensive simulationenvironments are also complex

•Expertise and considerable time isneeded to set up the environment forthe simulation results you want

•While this expertise may exist in yourorganization, it may not be withevery engineer

•Homemade simulation setups,equations, & displays may haveerrors

Now we begin to think about the actual circuit design and the design software we’ll use.

Setting up your simulation environment to get the results you want can be complex. Detaileddesign and simulation knowledge to properly set up the topology and the associated equations forprocessing data. It can also take significant time to validate the setup.

Some organization are fortunate enough to have the expertise to create complex simulation setups,but many do not. And even those that do have a few people with the expertise, not every designerhas the same level of expertise.

Finally, when someone does create their own simulation setups, they usually involve numerousequations with complex data displays, each of them are prone to errors.

Everything in DesignGuides could be duplicated by someone with the right design experience as wellas the right simulation expertise. However, DesignGuides:

- reduce time consuming simulation setup.

- eliminate error-prone experimentation with syntax.

- provide convenience through extensive use of linked variables.


7

APPLICATION CONTENTAPPLICATION CONTENT

DesignGuides

ApplicationsAmplifiersFiltersMixersOscillatorsPassivesSystemMods/DemodsPackagingOthers

Simulation TechnologyLinear

NonlinearCircuit Envelope

Time DomainAgilent PtolemyElectromagnetic

Others

CUSTOMIZATION CUSTOMIZATION

RF IP Encoder

LIBRARIESLIBRARIES

Design Libraries

Bridging the GapBridging the Gap

SYNTHESISSYNTHESIS

RF Compiler/E-Syn/LineCalc

Solution -- Advanced Design System 1.3Unprecedented Productivity

AUTOMATIONAUTOMATION

Layout to HFSS Link

DesignGuides bridge the gap between simulation technology and the specific design need orapplication by providing the design expertise within an application layer that runs within the ADSenvironment.

Test setups are predefined so that the user need only set the appropriate simulation values andconfigure their test circuit.

The data display is set up to present the main circuit performance and specifications. Many circuitsrequire a standard set of performance tests. With DesignGuides there is no need to reinventsimulation setup and data processing.


8

E-Syn or Passive Circuit DesignGuideWhat are the differences?

E-Syn

• Lumped Elements

• Specify order/type, out-of-band performance

Passive Circuit DesignGuide

• Distributed Elements

• microstrip

• Automatically sets up simulation & datadisplay with relevant measurements

DC/Operating Point(Bias Network)


Performance Testing(Match, Gain, & Load Pull)

Layout & Manufacture

Measure

“Design expertise built in”

This is the design flow we will use for designing our PA. It has five stages.

We’ll begin our design flow with the design of the driver stage. And we’ll use a linear S-parametermodel which eliminates the need to focus on DC/Operating Point characteristics of the device. We’llspend more time on this step later when we design the power stage.

For now we’ll focus on designing input & output matching networks for the first device.

We have two choices that will assist in creating these matching networks, E-Syn or the newPassive Circuit DesignGuide.

You may already be familiar with E-Syn, so today we’ll use the DesignGuide.


9

Power Amplifier DesignGuideS-parameter simulations


The first step will be to determine the optimum impedance for maximum gain.

To do this, we’ll use the Power Amplifier DesignGuide.


10

S-Parameters, Noise Figure, & Stability “Design expertise built in”

Series Resistance is used to improve Stability of device

The driver stage can be designed using small signal techniques using DesignGuides. The PowerAmplifier DesignGuide is used to determine maximum available gain, stability factor, simultaneoussource, and load impedance. The Passive Circuit DesignGuide is used to synthesize the input andoutput matching networks.

When designing amplifiers, stability is always a concern. The Power Amplifier DesignGuide allowsanalysis and optimization of amplifier stability. However, this won’t be presented in this paper. Wedid add a series resistive load to stabilize the amplifier, which is necessary to design the matchingnetwork.

*Amplifiers can be unstable when terminated with certain load and source impedances. Thestability problem resulting from drain to gate coupling can be overcome by various well-knowntechniques, but these tricks are generally inappropriate for power amplifiers because of therequirement for greater efficiency. This problem is generally solved through the brute-force methodof degrading the input impedance through use of a resistor at the input to reduce feedback. Inaddition to increasing the stability, this series resistor also improves the input mismatch by makingthe input slightly insensitive to power level. Unfortunately, the side effect of adding a seriesresistance at the input is a reduction in the gain of the amplifier and an increase in noise figure.Therefore, we must be careful to choose a small value of resistance, just enough to meet therequired performance.


11

Simulation Results “Design expertise built in”

Here is the data display that is automatically generated. It has results for various measurements,but we’ll focus on the Matching for Gain area.


12

Design Matching Impedance for Maximum Gain

The DesignGuide tells us that for maximum gain the impedance of the input matching networkneeds to be the Zsource value indicated.


13

Passive Circuit DesignGuide

Control Palette

Matching Network Elements

Next, we’ll use the Passive Circuit DesignGuide to synthesize the input matching network.

We’ll select the control palette which will bring a set of icons for easy operation of theDesignGuide.

We’ll select the matching network icon which brings up a component palette.

We’ll choose a distributed, single stub matching network.


14

Synthesize Input Matching Network “Design expertise built in”

Zsource to Zload (conjugate match)

The single stub matching networks requires that you specify Zin & Zload (the conjugate match ofZsource provided in the data display).

Pressing the Design Icon, the DesignGuide creates a matching network (a shunt open stub followedby a series line).


15

Input Matching Network Performance “Design expertise built in”

Meet Input Match Spec

We can also display the simulation results of the matching network.

At this point, you also have the option to optimize the results to improve performance of thematching network.


16

Completed Driver Amplifier w/Matching Networks

TermTerm1Num=1Z=Z0

sp_hp_ATF-21170_1_19921201SNP1Bias="Fet: Vds=3V Id=20mA"

TermTerm2Num=2Z=Z0

DA_SSMatch2_NF_SP_StabilityDA_SSMatch2Subst="MSub1"F=1.88 GHzZin=22.954+j*36.672 OhmZload=50 Ohm

DA_SSMatch1_NF_SP_StabilityDA_SSMatch1Subst="MSub1"F=1.88 GHzZin=50 OhmZload=16.425-j*46.474

RR1R=20 Ohm

We can now design an output matching network using the same technique and have done so above.We’ve chosen to design the output to 50 ohms, although we could have designed an interstagematch directly to the input of the power stage.

Amplifier gain, input, and output reflection coefficients of this driver amplifier stage are shownabove.


17

S 22

High power

Low power

Next: Power Stage DesignDesigning for maximum output power

•Output impedance varies w/output power

•Ideal impedance exists for each output power

•Two techniques to design output match

•Load-pull technique

•Load-line analysis

DriverStage

PowerStage



Performance Testing(Match, Gain & Load Pull)

Layout & Manufacture

Measure

Designing the output-match network for power amplifiers is different from the complex-conjugate-matching technique used for small-signal linear amplifiers. This is because the output impedance(S22) of power devices varies as a function of output power. In general, an ideal terminationimpedance exists, which maximizes the output power available from the amplifier. The goal of theoutput-matching network is to transform 50 ohms into this ideal impedance. Unlike the conjugatematch technique used to maximize gain, here we trade-off gain for the purpose of achievingmaximum output power.

There are two basic ways to find the ideal output impedance that must be presented to the powerdevice of the amplifier. One is to perform a load-pull analysis (either simulated or with actualmeasurements), and the other is to design a matching network based on the physical model of theoutput device, load-line analysis. Then, the device is terminated with this load impedance and thesource is conjugate matched to provide maximum gain.


18

Designing Power Amplifier for Maximum Power OutputOutput Impedance is a function of output power

• Load-Line Analysis - Cripps Method

• Commonly used for PA Design

• Easy measure

• Simple and accurate

• Load-Pull Method

• Complicated measurement

• Load-Pull Contours easily generatedw/ ADS

• Greatest Accuracy -- Optimum LoadImpedance

Bias Point

Vs Vb (2Vb-Vs)

Imax

Imax/2

RL=2(Vb-Vs)/ImaxPout=Imax(Vb-Vs)/4Imax=1.2 Idss

Power amplifier design requires device characterization for power, efficiency, and reflectioncoefficients as a function of input power level. Bias conditions, output circuit loss, load impedance,and gain are the major design considerations to achieve the required amplifier performance.

To design a power amplifier, many designers use the optimum load impedance data provided by thedevice supplier, but this technique does not allow accurate prediction of measurement such as PAE,Harmonic distortion, Compression point, and of course Gain.

The power amplifier design techniques can be divided into two categories, namely, Load-Pullmethod and Load-Line approximation method (Cripps method).

The load-pull data, typically supplied by the manufacturer, provides the load impedance thatcorresponds to different output power levels. For any output power less than maximum, there is alocus of impedance values that form a closed contour on the output impedance plane. For maximumpower, the contour converges to a single point. From the load contours, a designer can find outoptimum load impedance to design an output matching network for maximum power transfer.

The Cripps method is used to calculate optimum load impedance for maximum power transfer. Theload impedance can be determined by using the DC-IV curves and device operating biasing point.


19

Id

Vds

1.3 Idss

useableregion

VnomVmin

useableregion

Vnom + (Vnom - Vmin) = Vmax

1.3 x Idss = Idmax

Load line = (Vmax - Vmin) 1.3 x Idss

= RL

Cripps Method: Load-Line AnalysisExample

•Determines resistance that gives highest power

•Similar output match as load-pull techniqueRopt= Vds/Idmax

A load-line analysis is a technique for finding the optimum impedance to present to the output stageof the power amplifier. If we look at the I-V curves for a FET, we see that there is a useable regionfor both drain current and drain-to-source voltage. For drain current, we generally use the regionbetween 0 and 1.3 x Idss. To keep the output voltage within the linear region of the FET, we avoidthe steep-sloped areas of the I-V curves.


20

FET Curve Tracer Simulation Setup “Design expertise built in”

We’ll use the Power Amplifier DesignGuide to generate the DC-IV curves for the MGF 2430Atransistor.

To analyzer the operating characteristics for the FET, we’ll use the Power Amplifier DesignGuide>DC & Bias Point Simulations>FET I-V Curves, Class A Power Efficiency, Load, Gm vs. Bias.

This setup will provide us with Rload.


21

FET Biasing Results “Design expertise built in”

The automatically generated data display directly gives the optimum load impedance required formaximum power transfer under class A operation of the device. The DesignGuide also provides userinteractive control to optimize the output power DC to RF efficiency and calculates load resistancefor user defined drain voltage.

We’ll focus on Rload for design of our matching network.


22

Output Matching Network Design

From Datasheet

Cds = 0.75 pF

Ld = 0.2 nH

Ropt= 18.0 Ohm

2.190

794.4m 36.28

18.353

DC-to-RF Efficiency,%

DC PowerConsumptionRload

Output PowerWatts dBm

Marker m1 bias point values, (Assuming Class A, AC current limited to marker m2 value and AC voltage nohigher than VDSmax.)

29.00

Using the DesignGuide, the DC bias analysis is carried out for the MGF 2430A and Rload iscalculated.

The values of Cds and Ld are taken from the device model data.

The next step is to design the output matching network to match the above equivalent circuit to 50ohms.

Various topologies are possible to accomplish the required matching network; however, as thebandwidth is small, a simple matching network can be realized to give required return loss. Thenature of the output impedance and its matching are more critical than the input impedance since italso determines the overall efficiency of operation, whereas the input matching only relates theinput return loss.

The output matching network requires a simple quarter wave transformer design between 18 ohmand 50 ohm. This is synthesized by using the Passive Circuit DesignGuide in a manner similar to thesingle stub network synthesized earlier.


23

Pmax

-1dB

-2dB

-3dB

Constant output power contours versusoutput load impedance (input powerconstant)

X XX X

Inputimpedance

andpower

measurementsystem

Outputimpedance

andpower

measurementsystem

InputTuner

OutputTuner

DUT

Load-Pull measurements can be very expensive and time-intensive

Load-Pull Technique

•Vary magnitude and phase of load presented to circuit

•Power output is measured at each impedance point

The load-pull measurement technique is based on the measured behavior of an amplifier. Detailedunderstanding of the physical models of the devices involved is not necessary. The procedure forperforming a load-pull analysis is to present the output of the amplifier with a variety of loadimpedances while simultaneously measuring the output power. The input match is adjusted eachtime as well to ensure a well-matched condition at the input of the amplifier.

This process is repeated with several different input-power levels. After all of the data is taken,contours of constant output power are plotted on the Smith chart. If the input power presented tothe amplifier was large enough, a single point on the Smith chart appears where the output powerwas at a maximum. This is the impedance that we must present to the output of the amplifier.

The tuners used to vary the input and output matches can be based on mechanical-slug tuners orpin-diode-based electronic tuners. Mechanical tuners excel in high-power applications because oftheir inherent low-loss when it is necessary to characterize an amplifier with highly reflectiveimpedances. Electronic tuners provide very fast and repeatable measurements. (Maury Microwaveis one supplier of such load-pull systems.)

In the majority of cases, designers will typically use either a load-line analysis or a load-pullsimulation.


24

Load-Pull Simulation -- Power Amplifier DesignGuide

The easiest alternative to either a load-line analysis or a load-pull measurement is a load-pullsimulation. Load-pull simulation is easier, faster, and more accurate than the load-line analysis.Load-pull simulation is simpler, quicker, and far less expensive than a load-pull measurementsystem.

For each specific impedance value, the Advanced Design System evaluates the correspondingoutput power level and displays it on the Smith chart.

The Power Amplifier DesignGuide provides the setup and equations to perform a load-pullsimulation.

All you need to do is place your device into the schematic, adjust the bias voltages appropriately,set the power levels, and specify the region on the Smith chart where you’d like the load-pull datafor.


25

DesignGuide Load-Pull Simulation Results

Here are the results for the load-pull simulation.


26

DesignGuide Load-Pull EquationsDetailed & Complex

Let’s take a moment and provide a brief view of some of the design & simulation expertise detailsthat are behind the DesignGuides.

Here we show some of the equations that are used in the DesignGuide just to run the Load-Pullsimulation and to view the results.

The value of the DesignGuides is the ability to run load-pull simulations without having to have thedetailed design & simulation expertise needed to create these equations on your own.


27

Load-Pull Results -- Design Load Match to Peaks

As you can see, the results are similar to the load-line technique. This time though we have aspecific impedance to design to.


28

Output Match Design Impedance

The load-pull simulation gives us the load impedance value with which we should terminate our FET.The model used in the load-pull simulation is the packaged FET model, therefore the resulting loadimpedance includes the parasitics of the FET and package built-in to the analysis.


29

Completed Power StageLoad-Line method w/ microstrip transformer

Power Amplifier Stage

Goal

Here is our completed power stage after designing the input and output matching networks. Thesimulation results show that we are meeting our specifications for this stage.


30

Completed PA w/ Complete Modeling(bias circuitry, library parts, bends/crosses/tees/vias, etc.)

Driver StagePower Stage

Now, let’s build the completed amplifier.

Here is the completed schematic including the bias circuitry, SMT library parts, vias, andappropriate microstrip elements such as bends, tees, etc., to provide a completely accurate modelof the amplifier.

The biasing network was designed along with resistive divider network to drive gate voltage fromavailable –6.5 V. Biasing network design plays an important role in the success of the poweramplifier performance. The DC bypass capacitors value has to be carefully chosen to avoid anyoscillation at low frequencies. The packages dimensions of SMT passive devices can lead toundesired resonance and have to carefully be chosen to shift any resonance to much higher thanoperating frequencies. At this stage, the ideal lumped devices are replaced by passive SMT models,the distributed parasitics were added next along with the discontinuities, and the amplifier wasfurther optimized for the required performance.

Note : Commercially available inverter can be used to generate –6.5 V from available + 6.5 Vsupply.


31

PA Performance TestingOver 40 pre-defined simulations and corresponding data displays


Matching Networks(Gain, Match, Stability)


Layout(Build)



We’ll again use the Power Amplifier DesignGuide, but this time for performance testing. We’ll testonly the specifications that we identified earlier, but you can perform all of the common amplifierperformance tests with the Power Amplifier DesignGuide including two-tone tests.

The Power Amplifier DesignGuide is focused on performance testing of amplifiers. It provides over40 pre-defined simulations and corresponding data displays for the following common performancetests. Simulation topics include:

-DC & Bias Point

-S-Parameter

-1&2 Tone Harmonic Balance

-Matching Circuits


32

Spectrum, Gain, Harmonic Distortion vs. Power (w/PAE) “Design expertise built in”

Here is the simulation setup for Gain, Harmonic Distortion vs. Power, and PAE.


33

Data Display “Design expertise built in”

And the automatically generated data display. We’ll focus just on the boxed results.


34

Gain & Gain Compression “Design expertise built in”

The 1dB gain compression of an amplifier is a power point where the gain of the amplifier reducesby 1 dB. At the power level greater than gain compression point, the amplifier will generate veryhigh harmonic distortion components.

The plot shows gain as a function of input power. The gain meets the specifications of 23 dB.


35

2nd & 3rd Order Harmonics “Design expertise built in”

< 30 dBc Spec

All amplifiers generate undesired multiples of the fundamental frequency at the output calledharmonics, which are caused largely by the nonlinearity of the transistors used in the design ofpower stage. The specification defines the maximum harmonic level the amplifier can produce atthe output and is defined relative to the input power level (dBc). The curves show the output of the2nd and 3rd harmonics in dBc as a function of input power.


36

Power Added Efficiency “Design expertise built in”

Power Added Efficiency is defined as the ratio between the RF gain of the device and DC power.

PAE=(Pout-Pin)/PDC

The above plot shows PAE as a function of input power. Note that the efficiency increases as theinput power increases, up to the 1 dB gain compression point and after that the PAE drops.

Transistor bias in the main determinant of device efficiency. To increase the PAE, the designer mayneed to change the bias, use more stages or select a larger transistor. The efficiency in this case islow because we are operating the device at a relatively low voltage.


37

Power Amplifier Layout




Layout(Build)


Final layout of the amplifier is shown above. The complete design was confined in to a dimension of2 X 1 inch.

This layout was created with ADS using the design synchronization capability.


38

Finished Amplifier

Here is a photograph our finished amplifier.


39

Measured vs. Modeled




Layout(Build)


We did some basic measurements on the amplifier using a network analyzer.


40

Measured vs. Simulated Results

freq (1.850GHz to 1.910GHz)

S(1

,1)

fme

asu

red

am

p..

S(1

,1)

1.85 1.86 1.87 1.88 1.89 1.90 1.91

freq, GHz

2021222324252627282930

dB

(S(2

,1))

dB

(fm

ea

sure

da

mp

..S

(2,1

))

m3freq=1.880GHzdB(fmeasuredamp..S(2,1))=25.553

m3

m4freq=1.880GHzdB(S(2,1))=25.090

m4

m1freq=1.894GHzfmeasuredamp..S(1,1)=0.153 / 130.040impedance = 40.040 + j9.580

m1

m2freq=1.893GHzS(1,1)=0.127 / 139.708impedance = 40.648 + j6.795

m2

Good agreement betweensimulated & measuredresults

Measured

Measured

Simulated

Simulated

MeasuredMeasured

SimulatedSimulated

Here are the measurements of the input match and gain for the amplifier.


41

DesignGuides“Design Expertise Built-In”•Shorten Design Time through “Ease of Design”

•Built-In Expert Simulations & Data Displays

•Current DesignGuides

•PLL

•Oscillator

•Linearizer

•Power Amplifier

•Passive Circuits

•Look for more DesignGuides in the near Future

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