6. DE1-SoC Computer

DE1-SoC Computer

Computer Organization 및 Embedded system 실습을위해서DE1-SoC 교육용개발보드에구현된 computer system

HPS(Hard Processor System) ARM Cortex A9 dual-core processor DDR3 memory port

보드에서 1GB DDR3 memory와연결 a set of peripheral devices

보드에서 LEDG, KEY, G-Sensor가 I/O port에연결 FPGA - computer용 peripheral들과 NIOS II 프로세서가구현됨

two NIOS II processors memory, timer modules, audio in/out, video in/out PS/2, Analog-to-Digital, IrDA(infrared receive/transmit) parallel ports – switch, LED에연결

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DE1-SoC computer Block Diagram

3

HPS

Altera HPS Block Diagram

4

MPCore

HPS

Altera HPS Block Diagram

5

MPCore

L2 Cache

0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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MPCore

L2 Cache

0 GB

1 GB

2 GB

3 GB

4 GB

L3 Interconnect

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

L2 Cache

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

64KB

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

DDR3Chips

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

DDR3Chips

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

On-Chip RAM

DDR3Chips

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

On-Chip RAM

Timers

DDR3Chips

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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Boot ROM

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

13

Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GB

HPS

Altera HPS Block Diagram

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GBPeripherals

Exercise: HPS Peripherals

The program will use the HPS pushbutton and LED

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HPS Pushbutton and LED

Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers

Data, Interrupts, Configuration, etc.

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External Port

…

Data Register

Direction RegisterInterrupt Enable

…

HPS Pushbutton and LED

Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers

Data, Interrupts, Configuration, etc.

Each bit corresponds to a different I/O pin

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External Port

…

Data Register

Direction RegisterInterrupt Enable

…

HPS Pushbutton and LED

Both are attached to the memory-mapped GPIO 1 port Base address: 0xFF709000 16 registers

Data, Interrupts, Configuration, etc.

Each bit corresponds to a different I/O pin LED

Bit 24 Pushbutton

Bit 25

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External Port

…

Data Register

Direction RegisterInterrupt Enable

…

bit 25/24

포인터를사용한메모리접근

포인터를사용한메모리접근 *(char *)1000 1000번지의 8-bit 메모리데이터 *(short *)1000 1000번지의 16-bit 메모리데이터 *(long *)1000 1000번지의 32-bit 메모리데이터

*(int *)1000

int *addr, value; int address, valueaddr = (int *)1000; address = 1000;value = *addr; value = *(int *)address;

1000100110021003

*(char *)1000

*(short *)1000

*(long *)1000

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메모리 mapped I/O

I/O 장치의주소지정 memory mapped I/O : 메모리주소공간에 I/O 장치배치

모든프로세서에서사용가능 I/O mapped I/O, separate I/O : I/O 전용주소공간에 I/O 장치배치

I/O 전용주소공간을제공하는프로세서에서만사용가능 (ex) x386 memory mapped I/O 접근

*(volatile char *)addr addr번지의 8-bit I/O 데이터 *(volatile short *)addr addr번지의 16-bit I/O 데이터 *(volatile long *)addr addr번지의 32-bit I/O 데이터

*(volatile int *)addr volatile 접근수정자

휘발성, 즉, 저장되는내용이보존되지않을수있음을의미 컴파일러는이변수에대해서최적화하지않음 메모리가아닌입출력장치접근에주로사용됨

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메모리와 I/O 접근을위한자료형및매크로정의

자료크기지정을위한자료형정의typedef unsigned char u8;typedef unsigned short u16;typedef unsigned long u32;

메모리접근을위한매크로정의#define mem8(addr) (*(u8 *)(addr))#define mem16(addr) (*(u16 *)(addr))#define mem32(addr) (*(u32 *)(addr))

I/O 접근을위한매크로정의 (메모리 mapped)#define io8(addr) (*(volatile u8 *)(addr))#define io16(addr) (*(volatile u16 *)(addr))#define io32(addr) (*(volatile u32 *)(addr))

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비트조작을위한 C언어

비트단위(bitwise) 연산자 ~ (not) (ex) 1의보수: ~0x4 0xFFFB (11…10112) & (and) (ex) 선택적 clear : a & 0xFFFB a의 bit 2 = 0 | (or) (ex) 선택적 set : a | 0x8 a의 bit 3 = 1 ^ (xor) (ex) 선택적 complement : a ^ 0x10 a의 bit 4 반전

Shift 연산자

Program – Simple I/O using C language

Read the pushbutton and display the value on the LED“hps_gpio.c”

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#define bit_25_pattern 0x02000000 // (1 1); // Set the LEDG to the read value

}}

Step 1: Create a New Project

Create a new project 1. New Project 1.1 Specify a project name & directory 1.2 Specify a system

ARM Cortex-A9 …

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Step 1.3: Select Program Type

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Step 1.4: Add Source File

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Step 1.5: Set Board Connection and Select Processor

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Step 1.6: Leave Default Memory Settings

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Step 2: Compile and Load

Compile your C language program

Load the compiled code into the memory on the DE1-SoC board

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Step 3: Go to the Memory Window

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Step 4: Jump to the GPIO’s Address Range

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Step 5: Why is the Memory Window Blank?

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Step 6: Highlight the First Two Registers of the GPIO Port

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Step 7: Right Click and Read Selected Address Range

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Step 7: Right Click and Read Selected Address Range

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Step 8: Read the GPIO’s External Port

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Step 9: Hold Down the Button and Re-read the Location

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Step 10: Disassembly Window

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Step 11: Jump to Main

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Step 11: Jump to Main

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Step 12: Set a Breakpoint and Run to Main

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Step 13: Single Step or Run

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Step 14: Stop while Holding Down the Pushbutton

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HPS

How About Communication with the FPGA?

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GBPeripheralsFPGA

HPS

There are Several Bridges Between the HPS and FPGA

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

FPGA

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController

Bridges

SDRAMWindow

Boot Region0 GB

1 GB

2 GB

3 GB

4 GBPeripherals

HPS

How About Communication with the FPGA?

46

Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController SDRAM

Window

Boot Region0 GB

1 GB

2 GB

3 GB

4 GBPeripheralsFPGA

HPS

There are Several Bridges Between the HPS and FPGA

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

FPGA

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController

Bridges

SDRAMWindow

Boot Region0 GB

1 GB

2 GB

3 GB

4 GBPeripherals

HPS

HPS-to-FPGA Bridge

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

FPGA

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController

H2F

On-Chip Cores

Ports

LEDRSwitches

Etc.

SDRAMWindow

Boot Region

FPGASlave

Region

0 GB

1 GB

2 GB

3 GB

4 GBPeripherals

FPGAHPS

Lightweight HPS-to-FPGA Bridge

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Boot ROM

Ports

MPCore

On-Chip RAM

GPIO

Timers

DDR3Chips

LEDGKEY

USBEthernet

L2 Cache

SDRAMController

LW H2F

Ports

LEDRSwitches

Etc.

SDRAMWindow

Boot Region

FPGASlave

Region

0 GB

1 GB

2 GB

3 GB

4 GBPeripherals

On-Chip Cores

Exercise: FPGA Peripherals

Circuit must be configured in the FPGA

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Pre-built DE1-SoC Computer System

Download the system onto the DE1-SoC board Can be configured to load on

power-up

Develop programs using the Altera Monitor Program

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Exercise: FPGA Peripherals

We will use the red LEDs, seven-segment display and the slider switches

In the DE1-SoC, they are connecting to the Lightweight HPS-to-FPGA bridge using the Altera Parallel I/O (PIO) component

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PIO Components

Parallel I/O (PIO) Component Depending on the PIO’s settings,

registers are usable or not

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Edgecapture Register

…

Data Register

Direction RegisterInterruptmask Register

PIO Components

Parallel I/O (PIO) Component Depending on the PIO’s settings,

registers are usable or not DE1-SoC Computer

Red LEDs Base address: 0xFF200000

Seven segment displays Base address: 0xFF200020

Slider switches Base address: 0xFF200040

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Edgecapture Register

…

Data Register

Direction RegisterInterruptmask Register

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Program – “fpga_gpio.c”

Read switches and display on LEDs and 7-Segs

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int main(void)(volatile int *LEDs = (int *) 0xFF200000;volatile int *HEX3_HEX0 = (int *) 0xFF200020;volatile int *SW_switch = (int *) 0xFF200040;int hex_conversions[16] = {0x3F, 0x06, 0x5B, 0x4F, 0x66, 0x6D,

0x7D, 0x07, 0x7F, 0x67, 0x77, 0x7C, 0x39, 0x5E, 0x79, 0x71};while(1){

int value = *SW_switch;*LEDs = value;int first_digit = value & 0xF;int second_digit = (value >> 4) & 0xF;int third_digit = (value >> 8) & 0xF;int hex_value = hex_conversions[first_digit];hex_value |= hex_conversions[second_digit]

Step 1: Create a New Project ..

Sets up the Altera Monitor Program Select files to work with Specify target system

Step 1: Create a New Project Step 1.1: Specify name, directory and architecture

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Step 1.2: Select the DE1-SoC Computer System

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Step 1.3: Select Program Type

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Step 1.4: Add Source File

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Step 1.5: Set Board Connection and Select Processor

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Step 1.6: Leave Default Memory Settings

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Step 2: Program the FPGA with the Computer System

Download the DE1-SoC computer into FPGA

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Step 3: Compile and Load

Compile your C language program

Load the compiled code into the memory on the DE1-SoC board

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Step 4: Jump to the FPGA’s Address Range

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Step 5: Read the Switches, LEDs and 7-Segs Locations

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Step 6: Toggle Some Switches and Re-read

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Step 7: Write Some Values to the LEGs and 7-Segs

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Step 8: Go to the Main Function

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Step 9: Set a Breakpoint at the Load from Switches

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Step 10: Toggle Some Switches and then Single Step

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Step 11: Single Step until the LEDs are Set

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Step 12: Single Step or Run

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Exercise: Semihosting

Virtual Operating System

Allows C programs to make system calls I/O functions Time functions File operations

Altera Monitor Program supports a subset printf and scanf to and from the terminal window. Some time functions

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Program – “semihost.c”

Printf, scanf and time functions

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#include #include

int main(void)(char str[64];int age = 0;// Get the initial timestampclock_t start_time = clock();while(1){

printf("What is your name?\n");scanf("%s",str);printf("What is your age?\n");scanf("%d",&age);...

}return 0;

}

Step 1~3: Create a New Project/Compile & Load

Step 1. Create a New Project New project – semihosting Specify target system – DE1-SoC computer Select files to work – C program, semihost.c Terminal device - Semihosting

Step 2. Program the FPGA with the Computer System

Step 3. Compile and Load

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Step 4: Run

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Step 5: Type in your name

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Step 6: Type in your age

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Step 7: See the Result of the Semi-hosting Functions

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