65nm ombudsman - indian statistical institutevlsi2005/keynotes/ted_vucurevich.pdf · ip based soc...

CADENCE CONFIDENTIAL

65nm Ombudsman

Ted VucurevichCTOAdvanced Research and Development


IP based SOC Design:Complexity, Cost, and Risk

Digital IP

Product 2 Product 3Platform 1

Product 1 Product n

System, board, chip optimization

Software, hardware trade-offs

$50-70m@65nmCell libraries Software

Analog IP ProcessorsTesting

Packaging MemoryFoundry


Time to Market (Critical to success)

• Takes longer than expectedto complete >90nm designs, sometimes compromisingdesign objectives

• Time-to-market requirementspreclude the ability to do are-spin.

• Power minimization has become a key metric –especially for >90nm designs in the wireless communications, consumer, etc, segments.

• Manufacturing yields must be considered during design implementation at >90nm

Key Factors in Design (10 Being Most Important)

Feature Size 0.18µm 0.13µm 90nm

Complete On-Time - - 9Chip area 6 to 8 5 to 8 4 to 7 Performance 2 to 8 2 to 8 2 to 8 Power 3 to 8 5 to 8 6 to 8 Manufacturing yields 1 to 2 3 to 5 7 to 9 Ability to ensure 2 to 4 5 to 7 2 to 8

first-time success Source IBS


Less First Silicon Success and the Changing Rate of Failures

• Better– Functional Verification– Noise / SI– Clocking– IR Drops

• Worse– Analog Tuning– Mixed-Signal Interface– DFM (RET)

0%

4%

5%

10%

12%

14%

14%

16%

17%

18%

22%

28%

62%

3%

9%

13%

14%

8%

10%

23%

45%

0% 10% 20% 30% 40% 50% 60% 70%

RET

Other

Mixed-SignalInterface

Firmw are

Yield / Reliability

IR Drops

Analog Tuning

Slow Path

Fast Path

Clocking

Pow er Consumption

Noise / SI

Logic/Functional

2003

2001Collett International Research:

2000, 2002 Functional Verification Studies;2003 Design Closure Study, 01/04

• First silicon success rates declining

– First Silicon OK 48% in 2000 39% in 2002 34% in 2003

– Third Silicon OK>90% in 2000 >70% in 2002 >60% in 2003

Trends are Increasing

Tren

ds a

re D

ecre

asin

g


Design Hand-off Point Complexity

LibrariesRET Rules

Implementation

Sign-Off

IPFirmware App. LibsPlatform

Models

• Historic Design to Manufacturing Hand-Off– GDSII Sign-Off with

DRC/LVS

• Sub-Wavelength DFM Hand-Off– GDSII Sign-Off with

DRC/LVS

– Electrical Sign-Off– Signal and Physical

Integrity

– Design Robustness

– Yield

– Reliability

RTL

• RTL Handoff – Verilog / VHDL

– Vectors

• Platform– IP, SW

– SVP, IVP

System

Manufacturing


Addressing >65nm Design Challenges

Analysis

ModelingOptimization

Synthesis

What is Manufacturable?

Design Rule Complexity

01234

250 nm 180 nm 130 nm 90 nm 65 nm

Node

Normalized Pages

Increasing lithographic complexity is driving increasingly complex design rules.

Source: Mark Mason (TI)

Electrical ComplexityVariability: Process, Thermal

HotSpot

Runtime SW Dependent

Device

Wire

Source: “Models of process variations in device and

interconnect” by Duane Boning, MIT & Sani Nassif,

IBM ARL.

65nm Device Modeling challenges

DistantNeighbors

Near byNeighbors

• Identically drawn devices can be imaged quite differently due toeffect of neighbors

What we used to model

What we must model now

What we need to supportOne model: Many users

• One model for all transistor analysis

Parameter Extraction

Timing Simulation

Signal Integrity

IR Drop

Circuit Simulation

Static Timing Analysis

Electromigration

RF Simulation

Model

Device Modeling Standardization

The Compact Modeling Extensions to Verilog-A/MS

• Allows low level models to be defined in a standardized modeling language

– Device modeling

– Macromodeling

– Interconnect modeling

• Paramsets standardize SPICE .model files

– Vendor independent model files

– Directly supports modeling of variation

Mismatch Example

• Modeling variation across die vs. xy

rho11 rho01

paramset n180nm bsim6;...rho = rhostats.drho/sqrt($m∗$n) + (

(1 – $x)∗(1 – $y)∗rhostats.rho00 + $x∗(1 – $y)∗rhostats.rho10 +(1 – $x)∗$y∗rhostats.rho01 + $x∗$y∗rhostats.rho11

);...

endparamsetrho00

drho

rho10

y

x


Integrated Extraction will be necessary

• Extractors will produce instance based models

– Not just parameters

– Tailored models are more powerful, compact

Parameter Extraction Simulation/AnalysisModels

• Examples

– Interconnect extraction, variability extraction, macromodeling

Mismatch Example

• Extractor passes location and orientation for instantiation

n180nm #( ..., .$x(–2), .$y(4), .$angle(0)) M1 ( ... )n180nm #( ..., .$x(4), .$y(2), .$angle(-90)) M2 ( ... )n180nm #( ..., .$x(2), .$y(–4), .$angle(180)) M3 ( ... )n180nm #( ..., .$x(–4), .$y(–2), .$angle(90)) M4 ( ... )

M1 M2

M3M4

Interconnect Modeling:Process Modeling Complexity

• Resistance

– Non-rectangular wires

– Wire edge effects– Actual wire widths vary depending

on spacing to neighboring wires on each side

– Dishing, slotting

• Capacitance

– Sidewall >> Substrate

– Complex 3d structure

Source: David Overhauser

Net to Extract

Optical Modeling ComplexityRET Corrections not complete

No RET

Lars Liebmann of IBM

RET

POE Modeling:Kernel based techniques

• Example:– φ : 7→ 7

– Shown, projectionsin 3

M1 M2

M4M3

L1L2

L3 L4

L5 L6

V+outV-

out

V-in

V+in

Vbias

• Set of configuration parameters:{W1, L1, Ibias, W3, L3, W/L|mirror, Cload}

• Set of performance parameters:{gain, noise, power, HD2, HD3, Q, Cload}

• Mapping from configuration to performance through simulation

Source: Fernando De Bernardinis

Modeling Variability:Machine Learning

Cross-section view

Aggressor

Net to Extract

Source: David Overhauser

Capacitance models (27 independent parameters)Models exist for 3D structuresX architecture SUPPORT

ML and Experimental Design:NX Architecture and Capacitance Application

Seed +Experimentaldesign

Fieldsolver

Modelgeneration

Training data /test data

Profileconfigurations

Prob. distributionon models

model #

prob

Modelapplication

Profileconfigurations

PredictedcapacitancesProfile

decompositionChip

NX-C EngineExtractiontech. file

RCGen



Analysis


Synthesis


Electrical Verification: Silicon predictability at nanometer geometries

IR-Drop Analysis

case3

case4

case5

clock driver

BUF4

BUF4 x 4

25 points

tpd

500 um

200

um

Delay Calculation

0 200 400 600 800Victim delay pushout (ps)

0

200

400

600

800

Rece

iver

outp

ut dela

y push

out (p

s) Consistent pessimism reduction over hundreds of nets

More pessimism reduction for noisier nets

Crosstalk Analysis

Timing Engine

Statistical Timing Analysis

STA

N worst Case Paths

5 interconnectcorners

Propagation

Symbolic

Monte Carlo

Slow, Nom, FastLibraries

PDF’sCDF’s

Source: Sreeja Raj

Robust Clock Design:Improving design margin

Q DD2

D1D0

D3

-11,+16

-12, +14-8, +16-9, +12-14,+18-10, +20

Variance

3525353Metal5

22165297 Total

5962471Metal45953089Metal35807360Metal2826299Metal1

LengthLayer

Fatal Timing Problems when process variation induces:

Hold Violation: Fast D1, Fast D2, Slow D3Setup Violation: Slow D1, Slow D2, Fast D3


Analysis


Synthesis

Manufacturing Robustness: Via Optimization

Before Optimization After Optimization

Via Optimization ResultsVia Optimization ResultsLayer Before AfterVIA1 67.2% 89.1%VIA2 64.7% 89.3%VIA3 70.3% 96.2%VIA4 73.9% 98.6%Total 67.3% 91.7%

Power Via Optimization ResultsPower Via Optimization Results6,393 Areas for improvement78,262 vias missing and added


Functional Yield Improvement:Design Robustness (variability analysis)

Statistical, Electrically AwareDefect Density

Driven Optimization

Yield = (1 + λ/α)- α

defect densitycritical areafailure rate

λ = ?x()[CA(x)][D(x)]dxA defect causing a short

Yield = (1 + λ/α)- α


λ = ?x()[CA(x)][D(x)]dx


λ = ?x()[CA(x)][D(x)]dxA defect causing a shortA defect causing a short

Yield Improvement for ARM 9 core:Wire Spreading and Tuning Example

Significant Critical Area Reduction

Incremental Extraction and Optimization:Wire Spreading

GeometryEngine

TimingCore RouterExtractor

DelayCalc.

SI

OA-UDM

NetAreaChip

EstimatedMSTGeometry

3D corridor

Reduced network

Timing annotations

ARM Core Spreading DetailBefore Wire Spreading

Example segment at min space of 0.14um

Negative slack for path

After Wire Spreading

Example segment spread to 0.7um

Total Cap for net decreased by 6%

Coupling Cap for net decreased by 9%

Positive slack for path (increase of 44ps)

ARM Core Example: Impact on Parasitics

-11.8%

Less Coupling-Cap. => Total Cap. reduced by ~ 12%


Analysis


Synthesis

Serving the opportunityThe “Everything Closure” problem

• Closure issues extend across multiple design dimensions as well as throughout the design process

– Performance: Area, Speed, Power, Thermal

– Manufacturability: Yield, Reliability

– Test: Cost, Diagnostics

• Must re-architect the entire implementation tool chain to address the resulting consequences.

“Everything Closure”

Mask Handoff

≥ 0.25µ 0.18µ - 0.13µ ≤ 90nm

Yield Optimization

Design

Routing

Finishing

PhysicalVerification

Planning

Placement

SynthesisPBS

RET/OPC

ElectricalSign-Off

PhysicalSynthesis

ChipOptimization

Manf.Optimization

Logic (gates)

Placement

Routing (wires)

Manufacture

Next Generation Core ArchitectureControl and Data “Busses”

DriversComponent Plug-in Component Software Integration mechanism

Control and coordination of the EnginesM

odel

ers

Ana

lyze

rs

Synt

hesi

zers

Verif

iers

Transaction layerOpen Access Unified Persistent Data Model

Thread Safe Run-time Data transactions

Re-entrantHeterogeneous IncrementalHierarchical

Topologically driven, Shape aware Interconnect Synthesis

• Constraint Driven

• Incremental

• Re-entrant

• Threadsafe

• Gridless w/ optional GriddedMode

• Shape-based

Topology &Global Routing

Detail Routing

Corridor Routing

Routing Optimization & Refinement

Manufacturing Aware Interconnect: Model-based topology criteria

Preferred Routing rules such as segment widths, spacings can be further refined. “Printing Rules such as min-jog length and width can also be enforced

Very little rip-up-&-re-route is performed to complete the routing and route optimization – resulting in layout that finishes as the designer predicted in the previous phases

Diagonal “X” interconnectManufacturability Improvement

“X Architecture”Total Wire Length= 128.6Total vias= 17

Traditional:Total Wire length= 171.9Total vias= 62

65 Nanometer Delay TestChallenge & requirements

Resistive bridge defects

Signal required

Delaydefect zone

Proper operation

Logic failure

Transition fa

ilure

Logi

c 1

Logi

c 0

Based on: “Defect-Based Test: A Key Enabler for Successful Migration to Structural Test”, Sanjay Senguptaet al, Intel Technology Journal, 1st quarter 1999

2.5V

2.0V

1.5V Delay Test requires

• High transition fault coverage

• Compact test patterns

• Post-wire timing (True-Time)

1.0V

0.5V

20ns0.0V

2ns 2.2ns 2.4ns 2.6ns 2.8nsStuck-at test capture

Design For Test (DFT) Delay test, compression, & diagnostics

Delay test Diagnostics

• Meet manufacturing cost requirements• Minimum design impact• Diagnostics compatibility

Compression

MIS

R w

/ X m

aski

ng1 0 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1

1 0 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 0

0 0 1 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1

0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 1 1 1

1 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1

1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1

• High transition fault coverage• Compact test patterns• Post-wire timing

• High Callout Defect correlation • Logic and scan chain diagnostics• Diagnostic test generation

Logic 0

Logic 1

Delay defect zone

Successful Nanometer Design

Modeling

Analysis

Synthesis

Optimization

65nm ombudsman - indian statistical institutevlsi2005/keynotes/ted_vucurevich.pdf · ip based soc...

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