6th Annual International Microelectronics Olympiad of Armenian

T E S T

The participants shall select one answer out of 5 possible answers in the answer sheet for each

question (A, B, C, D, E) by crossing lines from the top left corner to the bottom right corner and

form the bottom left corner to the top right corner (as it is shown below).

8. A B C D E

In the case of crossing out more than one answer for the same question or making any other

notes, the answer to that question will be scored 0.

8. A B C D E

Participant _________________________________________________

1. Given an n-input, 1-output combinational circuit C, depending on input variables x1, x2, , xn and

output variable y implementing a function f(x1, x2, , xn), and a combinational circuit C* is given

implementing the function f*(x1, x2, , xn) obtained from C when a fault F (for example, single stuck-

at-0 or stuck-at-1) occurs on its arbitrary line A. The fault F is diagnosable with respect to a class of

faults if

A. The fault F is necessarily detectable B. The fault F is not necessarily detectable C. It is necessary and sufficient that the fault F be detectable D. All the faults from class are necessarily detectable E. All the faults from class are not necessarily detectable

2. For what value of parameter

2 4 1

0 2

1 3 2

M

matrix does not have inverse M-1

?

A. 4/3 B. 1 C. 2 D. 4 E. 3

3. What is a potential well?

A. Energetic state for which a certain minimum energy is required for the particle to escape it B. Dimensional space which the particle can escape if acquires maximum energy C. Limited space where the state energy of the particle is less than its maximum transfer energy D. Limited space from all sides E. All the answers are correct

4. The main limitations to reduce the feature sizes of the nanoscale integrated circuits are:

A. Physical B. Technological C. Thermal D. Statistical E. All the answers are true

5. Which of these elements are used in high level synthesis algorithms: a-Boolean logic elements; b-

multiplexer; c-Flip-Flop; d-transistor; e-register; f-driver?

A. c,d,e,f B. a,c,f C. a,b,e D. a,b,d,f E. b,e,f

6. What does the conductance band difference of the abrupt heterojunction equal to?

A. Difference of output functions B. Difference of dipole moments C. Difference of affinities of semiconductors D. Difference of the bandgaps

E. Difference of the Fermi energies

7. The charge carriers mobility in the double gate MOS transistor is more because

A. Subthreshold transconductance is high B. There exist short channel phenomena C. The effective thickness of the oxide is small D. Intensity of a cross-sectional field in the channel is small E. The channel is far from substrate

8. For different circuit applications, a bipolar transistor is presented in the form of quadrupole,

characterized by two current values 1I and 2I and two voltage values 21,UU .

the following are taken as input parameters for h-parameter system:

A. 21 ,UU

B. 21 , II

C. 12 ,UI

D. 21,UI

E. 21, IU

9. Which are majority carriers in p type semiconductors?

A. Electrons B. Holes C. Ions D. Electrons and holes E. Electrons, holes and ions

10. Consider the following code:

#include

class A

{

public :

A()

{

std::cout

std::cout

3 private:

4 int Wheels;

5

6 public:

7 Car(int wheels = 0)

8 : Wheels(wheels)

9 {

10 }

11

12 int GetWheels()

13 {

14 return Wheels;

15 }

16 };

17 int main()

18 {

19 Car c(4);

20 cout

};

int main()

{

my_class m1, m2;

m1.a() = 5;

m2.a() = m1.a();

std::cout

}

A. In first 1 In second 2 B. In second 1In first 2 C. In first 0 In second 2 D. In second 0 In first 2 E. None of the above

14. The product of electron and hole concentrations in extrinsic semiconductor

A. Depends on Fermi level B. Is independent of temperature C. Is independent of impurity concentration D. Is independent of bandgap energy E. Is independent of electron effective masse

15. For the graph to include Euler cycle, it is necessary and sufficient that

A. It is not connected and the degrees of some nodes are even B. It is not connected and the degrees of all nodes are odd C. It is not connected and the degrees of all nodes are even D. The degree of its one node is odd E. It is connected and the degrees of all nodes are even

16. The design consists of 30 transistors of different widths. Two groups by 15 and 8 transistors from this

design are chosen. In how many ways can this selection be made such that the width of arbitrary

transistor from the first group will be less than width of arbitrary transistor from the second group?

A. 2330A

B. 2330

C. 2330C

D. 3023

E. 1538A

17. What is channel length modulation in a small signal model of a MOS transistor presented by?

A. Current controlled current source B. Voltage source C. Capacitor D. Resistor E. Current controlled voltage source

18. What is body effect in a small signal model of a MOS transistor presented by?

A. Current controlled current source B. Voltage controlled voltage source C. Voltage controlled current source D. Resistor E. Current controlled voltage source

19. What function is realized by this circuit?

A. Y= x1x3+ x1x2 B. Y= x1x2 + x2x3 +x1x2 C. Y= x1x2 + x1x3 +x1x2 D. Y= x1x2 + x2x3 + x1 E. None of the above

20. The number A is represented in memory in floating point form (IEEE 754 standard) and is equal to

40C0 0000 (hexadecimal system). Which of the mentioned numbers corresponds to the given A

number?

A. 6 B. 10 C. 35 D. 20 E. None of the above

21. For the circuit shown below determine the operating mode if VT0=0.4V.

A. Cut-off B. Linear C. Tetrode D. Non-linear E. Saturation

DC 0 20 1

2

21 3

4

22 5

6

7

0 CD

1 20

2

3 21

4

5 22

6

7

1 1

2 7

3 3

4 2

5 5

6 8

7 6

8 4

x3

x2

x1

Y

0.2V

0.0V

1.2V

22. For the circuit shown below determine the steady state voltage across the capacitor. Assume the

capacitor was initially discharged and VT0=0.4V.

A. 0.4V B. 1.2V C. 0.8V D. 1.0V E. 0.6V

23. The II phase of diffusion (deposition) provides:

A. High surface concentration and large depth of impurities B. High surface concentration and shallow depth of impurities C. Low surface concentration and large depth of impurities D. Low surface concentration and shallow depth of impurities E. Low surface concentration of impurities

24. The gradual channel approximation for the MOS transistors model is conditioned by: (Ex is a vertical

electric field component in the channel, Ey is a lateral electric field component, L channel length, tox

gate oxide thickness)

A. Ex > Ey C. EyL = Ex tox D. EyL >> Ex tox E. Eytox = ExL

25. What does the gate-substrate workfunction of a MOS transistor depend on?

A. The gate material and the gate oxide thickness B. The gate material and the oxide charge C. The positive or negative bias applied to the gate electrod D. The gate material and the substrate doping E. The substrate doping and the electric field in the channel

26. Given is the following numerical integration formula (Adam-Bashford):

Which of the following properties does this method have?

1 V

1.2V

)(xt 24

91)(xt

24

372)(xt

24

593)(xt

24

553)x(4)x(

A. Implicit B. Explicit C. Three-step method D. Four-step method E. B and D variants are correct

27. Find input impedance ratio Zi(C)/ Zi(C=0) of the shown circuit if Re=8k, hie=3k, hre=0, hoe=20S,

and =50>>1.

A. Zi(C)/ Zi(C=0)=0.5 B. Zi(C)/ Zi(C=0)=4.05 C. Zi(C)/ Zi(C=0)=0.56 D. Zi(C)/ Zi(C=0)= 1.014 E. Zi(C)/ Zi(C=0)=2

28. An NMOS transistor starts to conduct when:

A. The potential difference between the drain and the source terminals is higher than the threshold voltage Vt

B. The potential difference between the gate and the source terminals is higher than the threshold voltage Vt

C. The potential difference between the gate and the drain terminals is higher than the threshold voltage Vt

D. The potential difference between the drain and the base terminals is higher than the threshold voltage Vt

E. None of the above

29. The drain induced barrier lowering happens because of:

A. High gate voltage in an NMOS device B. High drain voltage that contributes in reducing the threshold voltage C. The decrease in current in the channel due to high drain voltage D. All of the above E. None of the above

30. The static power is affected by many factors in CMOS ICs, some of these factors are:

A. Temperature, threshold voltage, and supply voltage

Zi=Vi/Ii

Ii

Vi

C

Q1

Q2

Re

0

Rc = Re

B. The activity factor at which the circuit is switching, supply voltage, and threshold voltage C. The capacitive load of the circuit, switching activity, and supply voltage D. The temperature, the switching activity, and the variability in the threshold voltage E. None of the above

Answer Sheet

1. A B C D E

16. A B C D E

2. A B C D E

17. A B C D E

3. A B C D E

18. A B C D E

4. A B C D E

19. A B C D E

5. A B C D E

20. A B C D E

6. A B C D E

21. A B C D E

7. A B C D E

22. A B C D E

8. A B C D E

23. A B C D E

9. A B C D E

24. A B C D E

10. A B C D E

25. A B C D E

11. A B C D E

26. A B C D E

12. A B C D E

27. A B C D E

13. A B C D E

28. A B C D E

14. A B C D E

29. A B C D E

15. A B C D E

30. A B C D E

Participant _________________________________________________