7/2/2015445_23 1 pipelining ece-445 computer organization dr. ron hayne electrical and computer...
TRANSCRIPT
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Pipelining
ECE-445
Computer Organization
Dr. Ron Hayne
Electrical and Computer Engineering
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Pipelining
F1 E1
I1
F2 E2
I2
F3 E3
I3
Sequential Execution
F1 E1I1
F2 E2I2
F3 E3I3
Pipelined Execution
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Hardware Organization
InstructionFetchUnit
ExecutionUnit
Interstage BufferB1
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Four State Pipeline
Fetch (F) Read the instruction from memory
Decode (D) Decode the instruction and fetch the source operand(s)
Execute (E) Perform the operation specified by the instruction
Write (W) Store the result in the destination location
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Four Stage Pipeline
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Hardware Organization
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Data Hazard
Pipeline stalled Source or destination operands not available at time
expected in the pipeline Execution operation taking more than one clock
cycle
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Data Hazard
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Data Dependency
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Operand Forwarding
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Operand Forwarding
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Handling Data Hazards in SW
Compiler detect data dependencies and deal with them Insert NOPs Attempt to reorder instructions to perform useful tasks in
NOP slots
Side effects Instruction changes contents of a register other than the
named destination Autoincrement/autodecrement addressing modes Condition code flags
Give rise to multiple dependencies Should be minimized
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Instruction Hazards
Pipeline stalled Delay in the availability of an instruction
Cache miss Branch instructions
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Instruction Hazard
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Instruction Queue and Prefetch
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Branch Penalty
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Branch Prediction
Attempt to predict whether or not a particular branch will be taken
Speculative execution Continue to execute until outcome of branch evaluated No processor registers or memory can be updated until
branch outcome is confirmed
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Branch Prediction
Static Branch Prediction Some branch instructions predicted as taken and others
as not taken End or program loop Beginning of program loop Hardware or compiler
Dynamic Branch Prediction Based on execution history
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Structural Hazard
Two instructions require use of a given hardware resource at the same time Access to memory
Separate instruction and data caches Access to register file
Multiple port register file
In general avoided by providing sufficient hardware resources on the processor chip
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Structural Hazard
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Summary
Pipelining does not result in individual instructions being executed faster
Throughput increases Rate at which instruction execution is completed
Important goal in designing processors is to identify all hazards that may cause the pipeline to stall Find ways to minimize their impact
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Questions?