8 series chipset pch datasheet

8/10/2019 8 Series Chipset Pch Datasheet

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328904-003

Intel8 Series/C220 Series ChipsetFamily Platform Controller Hub(PCH)

Datasheet

May 2014


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2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OROTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONSOF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATINGTO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence orcharacteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have noresponsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice.Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from publishedspecifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.

Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release.Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product orservices and any such use of Intel's internal code names is at the sole risk of the user.

I2C is a two-wire communications bus/protocol developed by NXP. SMBus is a subset of the I2C bus/protocol and was developed by Intel.Implementations of the I2C bus/protocol may require licenses from various entities, including NXP Semiconductors N.V.

IntelAnti-Theft Technology (IntelAT): No system can provide absolute security under all conditions. Requires an enabled chipset, BIOS, firmware andsoftware and a subscription with a capable Service Provider. Consult your System manufacturer and Service Provider for availability and functionality.Intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof. For more information, visit http://www.intel.com/go/anti-theft

IntelHigh Definition Audio (IntelHD Audio): Requires an IntelHD Audio enabled system. Consult your PC manufacturer for more information. Soundquality will depend on equipment and actual implementation. For more information about IntelHD Audio, refer to http://www.intel.com/design/chipsets/hdaudio.htm

IntelTrusted Execution Technology (IntelTXT): No computer system can provide absolute security under all conditions. IntelTXT requires acomputer system with Intel Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXTcompatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXTrequires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, seehttp://www.intel.com/technology/security

IntelActive Management Technology (IntelAMT) requires activation and a system with a corporate network connection, an IntelAMT-enabledchipset, network hardware and software. For notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly,on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup and configuration. For more information, visit http://www.intel.com/technology/platform-technology/intel-amt

No computer system can provide absolute security under all conditions. IntelTrusted Execution Technology (IntelTXT) requires a computer systemwith IntelVirtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible MeasuredLaunched Environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/

securityIntelVirtualization Technology requires a computer system with an enabled Inte l processor, BIOS, virtual machine monitor (VMM). Functionality,performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with alloperating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization.

IntelvPro Technology is sophisticated and requires setup and activation. Availability of features and results will depend upon the setup andconfiguration of your hardware, software and IT environment. To learn more visit: http://www.intel.com/technology/vpro

Intel, Pentium, Intel vPro, Xeon, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Copyright 20132014, Intel Corporation. All rights reserved.


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Contents

1 Introduction ............................................................................................................ 411.1 About This Manual............................................................................................. 411.1.1 Chapter Descriptions ............................................................................. 42

1.2 Overview ......................................................................................................... 441.2.1 Capability Overview...............................................................................45

1.3 Intel8 Series/C220 Series Chipset Family PCH SKU Definition............................... 521.4 Device and Revision ID Table..............................................................................57

2 Signal Description ................................................................................................... 602.1 Flexible I/O ......................................................................................................622.2 USB Interface ................................................................................................... 632.3 PCI Express*.................................................................................................... 662.4 Serial ATA Interface........................................................................................... 672.5 Clock Signals .................................................................................................... 692.6 Real Time Clock Interface................................................................................... 702.7 External RTC Circuitry........................................................................................ 712.8 Interrupt Interface ............................................................................................ 71

2.9 Processor Interface............................................................................................722.10 DirectMedia Interface (DMI) to Host Controller ..................................................... 722.11 IntelFlexible Display Interface (Intel FDI)........................................................ 732.12 Analog Display/VGA DAC Signals......................................................................... 732.13 Digital Display Signals........................................................................................ 732.14 Embedded DisplayPort* (eDP*) Backlight Control Signals .......................................742.15 IntelHigh Definition Audio (IntelHD Audio) Link ...............................................742.16 Low Pin Count (LPC) Interface............................................................................. 752.17 General Purpose I/O Signals ............................................................................... 752.18 Functional Straps ..............................................................................................812.19 SMBus Interface................................................................................................ 842.20 System Management Interface............................................................................852.21 Controller Link .................................................................................................. 852.22 Serial Peripheral Interface (SPI) .......................................................................... 852.23 Manageability Signals ........................................................................................862.24 Power Management Interface..............................................................................872.25 Power and Ground Signals.................................................................................. 90

2.26 Thermal Signals ................................................................................................ 912.27 Miscellaneous Signals ........................................................................................922.28 Testability Signals ............................................................................................. 932.29 Reserved / Test Pins .......................................................................................... 93

3 PCH Pin States......................................................................................................... 953.1 Integrated Pull-Ups and Pull-Downs.....................................................................953.2 Output Signals Planes and States ........................................................................973.3 Input and I/O Signals Planes and States............................................................. 102

4 PCH and System Clocks ......................................................................................... 1074.1 Straps Related to Clock Configuration ................................................................ 1074.2 Platform Clocking Requirements ........................................................................ 1074.3 Functional Blocks ............................................................................................ 1094.4 Clock Configuration Access Overview ................................................................. 111

5 Functional Description ........................................................................................... 1125.1 Flexible I/O .................................................................................................... 112

5.2 PCI-to-PCI Bridge............................................................................................ 1135.2.1 PCI Bus Interface................................................................................ 1135.2.2 PCI Legacy Mode................................................................................. 113

5.3 PCI Express* Root Ports (D28:F0~F7)................................................................ 1135.3.1 Supported PCI Express* (PCIe*) Port Configurations................................ 1145.3.2 Interrupt Generation ........................................................................... 1145.3.3 Power Management ............................................................................. 115

5.3.3.1 S3/S4/S5 Support................................................................. 1155.3.3.2 Resuming from Suspended State............................................. 1155.3.3.3 Device Initiated PM_PME Message ........................................... 115


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Datasheet 5

5.9.2 Initialization Command Words (ICWx).................................................... 1415.9.2.1 ICW1 .................................................................................. 1415.9.2.2 ICW2 .................................................................................. 1425.9.2.3 ICW3 .................................................................................. 1425.9.2.4 ICW4 .................................................................................. 142

5.9.3 Operation Command Words (OCW)........................................................ 1425.9.4 Modes of Operation ............................................................................. 143

5.9.4.1 Fully Nested Mode................................................................. 1435.9.4.2 Special Fully-Nested Mode...................................................... 1435.9.4.3 Automatic Rotation Mode (Equal Priority Devices)...................... 1435.9.4.4 Specific Rotation Mode (Specific Priority).................................. 1435.9.4.5 Poll Mode............................................................................. 1445.9.4.6 Edge and Level Triggered Mode............................................... 1445.9.4.7 End of Interrupt (EOI) Operations ........................................... 1445.9.4.8 Normal End of Interrupt......................................................... 1445.9.4.9 Automatic End of Interrupt Mode............................................. 145

5.9.5 Masking Interrupts .............................................................................. 1455.9.5.1 Masking on an Individual Interrupt Request.............................. 1455.9.5.2 Special Mask Mode ................................................................ 145

5.9.6 Steering PCI Interrupts........................................................................ 1455.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 146

5.10.1 Interrupt Handling............................................................................... 1465.10.2 Interrupt Mapping ............................................................................... 1465.10.3 PCI / PCI Express* Message-Based Interrupts......................................... 1475.10.4 IOxAPIC Address Remapping ................................................................ 1475.10.5 External Interrupt Controller Support..................................................... 147

5.11 Serial Interrupt (D31:F0) ................................................................................. 1485.11.1 Start Frame........................................................................................ 1485.11.2 Data Frames ...................................................................................... 1485.11.3 Stop Frame........................................................................................ 1495.11.4 Specific Interrupts Not Supported Using SERIRQ ..................................... 1495.11.5 Data Frame Format ............................................................................. 149

5.12 Real Time Clock (D31:F0)................................................................................. 1505.12.1 Update Cycles..................................................................................... 1515.12.2 Interrupts .......................................................................................... 1515.12.3 Lockable RAM Ranges.......................................................................... 1515.12.4 Century Rollover ................................................................................. 1515.12.5 Clearing Battery-Backed RTC RAM......................................................... 151

5.13 Processor Interface (D31:F0)............................................................................ 1535.13.1 Processor Interface Signals and VLW Messages ....................................... 153

5.13.1.1 INIT (Initialization)................................................................ 1535.13.1.2 FERR# (Numeric Coprocessor Error) ........................................ 1535.13.1.3 NMI (Non-Maskable Interrupt) ................................................ 1545.13.1.4 Processor Power Good (PROCPWRGD)...................................... 154

5.13.2 Dual-Processor Issues.......................................................................... 1545.13.2.1 Usage Differences ................................................................. 154

5.13.3 Virtual Legacy Wire (VLW) Messages ..................................................... 1545.14 Power Management ......................................................................................... 155

5.14.1 Features ............................................................................................ 1555.14.2 PCH and System Power States.............................................................. 1555.14.3 System Power Planes........................................................................... 1575.14.4 SMI# / SCI Generation ........................................................................ 157

5.14.4.1 PCI Express* SCI.................................................................. 1605.14.4.2 PCI Express* Hot-Plug........................................................... 160

5.14.5 C-States ............................................................................................ 1605.14.6 Dynamic 33 MHz Clock Control (Mobile Only).......................................... 160

5.14.6.1 Conditions for Checking the 33 MHz Clock ................................ 1615.14.6.2 Conditions for Maintaining the 33MHz Clock .............................. 1615.14.6.3 Conditions for Stopping the 33MHz Clock ................................. 1615.14.6.4 Conditions for Re-Starting the 33MHz Clock.............................. 1615.14.6.5 LPC Devices and CLKRUN#..................................................... 161

5.14.7 Sleep States....................................................................................... 1625.14.7.1 Sleep State Overview ............................................................ 1625.14.7.2 Initiating Sleep State............................................................. 1625.14.7.3 Exiting Sleep States .............................................................. 1625.14.7.4 PCI Express* WAKE# Signal and PME Event Message................. 1645.14.7.5 Sx-G3-Sx, Handling Power Failures.......................................... 164


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5.14.7.6 Deep Sx...............................................................................1655.14.8 Event Input Signals and Their Usage......................................................166

5.14.8.1 PWRBTN# (Power Button) ......................................................1665.14.8.2 RI# (Ring Indicator) ..............................................................1675.14.8.3 PME# (PCI Power Management Event) .....................................1685.14.8.4 SYS_RESET# Signal...............................................................1685.14.8.5 THRMTRIP# Signal ................................................................168

5.14.9 ALT Access Mode.................................................................................1695.14.9.1 Write Only Registers with Read Paths in ALT Access Mode...........1705.14.9.2 PIC Reserved Bits..................................................................1715.14.9.3 Read Only Registers with Write Paths in ALT Access Mode...........171

5.14.10 System Power Supplies, Planes, and Signals ...........................................1725.14.10.1 Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#.............................1725.14.10.2 SLP_S4# and Suspend-To-RAM Sequencing ..............................1725.14.10.3 PWROK Signal.......................................................................1735.14.10.4 BATLOW# (Battery Low) (Mobile Only).....................................1735.14.10.5 SLP_LAN# Pin Behavior..........................................................1735.14.10.6 SLP_WLAN# Pin Behavior .......................................................1755.14.10.7 SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior..1755.14.10.8 RTCRST# and SRTCRST#.......................................................176

5.14.11 Legacy Power Management Theory of Operation ......................................1765.14.11.1 APM Power Management (Desktop Only) ..................................1765.14.11.2 Mobile APM Power Management (Mobile Only) ...........................176

5.14.12 Reset Behavior....................................................................................1775.15 System Management (D31:F0) ..........................................................................178

5.15.1 Theory of Operation.............................................................................1795.15.1.1 Detecting a System Lockup.....................................................1795.15.1.2 Handling an Intruder..............................................................1795.15.1.3 Detecting Improper Flash Programming....................................1805.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus..................180

5.15.2 TCO Modes .........................................................................................1805.15.2.1 TCO Legacy / Compatible Mode...............................................1805.15.2.2 Advanced TCO Mode..............................................................181

5.16 General Purpose I/O (D31:F0)...........................................................................1825.16.1 Power Wells........................................................................................1825.16.2 SMI#, SCI, and NMI Routing .................................................................1825.16.3 Triggering ..........................................................................................1835.16.4 GPIO Registers Lockdown .....................................................................1835.16.5 Serial POST Codes over GPIO................................................................183

5.16.5.1 Theory of Operation...............................................................1845.16.5.2 Serial Message Format ...........................................................185

5.17 SATA Host Controller (D31:F2, F5).....................................................................1865.17.1 SATA 6 Gb/s Support ...........................................................................1865.17.2 SATA Feature Support..........................................................................1865.17.3 Theory of Operation.............................................................................187

5.17.3.1 Standard ATA Emulation.........................................................1875.17.3.2 48-Bit LBA Operation .............................................................188

5.17.4 SATA Swap Bay Support.......................................................................1885.17.5 Hot-Plug Operation ..............................................................................1885.17.6 IntelRapid Storage Technology (Intel RST) Configuration.....................188

5.17.6.1 IntelRapid Storage Technology (IntelRST) RAID Option ROM.1895.17.7 IntelSmart Response Technology........................................................ 1895.17.8 Power Management Operation...............................................................189

5.17.8.1 Power State Mappings............................................................1905.17.8.2 Power State Transitions..........................................................1905.17.8.3 SMI Trapping (APM)...............................................................191

5.17.9 SATA Device Presence..........................................................................1915.17.10 SATA LED...........................................................................................1925.17.11 AHCI Operation...................................................................................1925.17.12 SGPIO Signals.....................................................................................193

5.17.12.1 Mechanism ...........................................................................1935.17.12.2 Message Format....................................................................1945.17.12.3 LED Message Type.................................................................1945.17.12.4 SGPIO Waveform ..................................................................196

5.17.13 External SATA.....................................................................................1975.18 High Precision Event Timers (HPET)....................................................................197


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5.18.1 Timer Accuracy................................................................................... 1975.18.2 Interrupt Mapping ............................................................................... 1975.18.3 Periodic versus Non-Periodic Modes....................................................... 1995.18.4 Enabling the Timers............................................................................. 1995.18.5 Interrupt Levels .................................................................................. 2005.18.6 Handling Interrupts ............................................................................. 2005.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors............................. 200

5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 2015.19.1 EHC Initialization ................................................................................ 201

5.19.1.1 BIOS Initialization................................................................. 2015.19.1.2 Driver Initialization................................................................ 2015.19.1.3 EHC Resets .......................................................................... 201

5.19.2 Data Structures in Main Memory ........................................................... 2015.19.3 USB 2.0 Enhanced Host Controller DMA ................................................. 2025.19.4 Data Encoding and Bit Stuffing.............................................................. 2025.19.5 Packet Formats................................................................................... 2025.19.6 USB 2.0 Interrupts and Error Conditions................................................. 202

5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads .............................. 2035.19.7 USB 2.0 Power Management................................................................. 203

5.19.7.1 Pause Feature ...................................................................... 2035.19.7.2 Suspend Feature................................................................... 2035.19.7.3 ACPI Device States................................................................ 2035.19.7.4 ACPI System States .............................................................. 204

5.19.8 USB 2.0 Legacy Keyboard Operation...................................................... 2045.19.9 USB 2.0 Based Debug Port ................................................................... 204

5.19.9.1 Theory of Operation ............................................................. 2055.19.10 EHCI Caching ..................................................................................... 2095.19.11 IntelUSB Prefetch Based Pause .......................................................... 2095.19.12 Function Level Reset Support (FLR) ....................................................... 209

5.19.12.1 FLR Steps ............................................................................ 2105.19.13 USB Overcurrent Protection.................................................................. 210

5.20 Integrated USB 2.0 Rate Matching Hub .............................................................. 2115.20.1 Overview ........................................................................................... 2115.20.2 Architecture ....................................................................................... 211

5.21 xHCI Controller (D20:F0) ................................................................................. 2125.22 SMBus Controller (D31:F3)............................................................................... 212

5.22.1 Host Controller ................................................................................... 2135.22.1.1 Command Protocols .............................................................. 213

5.22.2 Bus Arbitration ................................................................................... 2175.22.3 Bus Timing......................................................................................... 217

5.22.3.1 Clock Stretching ................................................................... 2175.22.3.2 Bus Time Out (The PCH as SMBus Master)................................ 217

5.22.4 Interrupts / SMI# ............................................................................... 2175.22.5 SMBALERT#....................................................................................... 2185.22.6 SMBus CRC Generation and Checking .................................................... 2195.22.7 SMBus Slave Interface......................................................................... 219

5.22.7.1 Format of Slave Write Cycle ................................................... 2205.22.7.2 Format of Read Command...................................................... 2215.22.7.3 Slave Read of RTC Time Bytes ................................................ 2225.22.7.4 Format of Host Notify Command ............................................. 223

5.23 Thermal Management ...................................................................................... 2245.23.1 Thermal Sensor .................................................................................. 224

5.23.1.1 Internal Thermal Sensor Operation.......................................... 2245.23.2 PCH Thermal Throttling........................................................................ 2255.23.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1)... 226

5.23.3.1 Block Read Address............................................................... 2275.23.3.2 Block Read Command............................................................ 2275.23.3.3 Read Data Format................................................................. 2275.23.3.4 Thermal Data Update Rate ..................................................... 2275.23.3.5 Temperature Comparator and Alert ......................................... 2285.23.3.6 BIOS Set Up......................................................................... 2295.23.3.7 SMBus Rules ........................................................................ 2295.23.3.8 Case for Considerations ......................................................... 230

5.24 IntelHigh Definition Audio (IntelHD Audio) Overview (D27:F0) ........................ 2325.24.1 IntelHigh Definition Audio (IntelHD Audio) Docking (Mobile Only)........ 232

5.24.1.1 Dock Sequence..................................................................... 2325.24.1.2 Exiting D3/CRST# When Docked............................................. 233


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5.24.1.3 Cold Boot/Resume from S3 When Docked.................................2345.24.1.4 Undock Sequence..................................................................2345.24.1.5 Normal Undock .....................................................................2345.24.1.6 Surprise Undock....................................................................2355.24.1.7 Interaction between Dock/Undock and Power Management States2355.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#............235

5.25 IntelManagement Engine (IntelME) and IntelManagement Engine Firmware (IntelME FW) 9.0 ............................................... 2365.25.1 IntelManagement Engine (IntelME) Requirements.............................. 237

5.26 Serial Peripheral Interface (SPI) ........................................................................2385.26.1 SPI Supported Feature Overview ...........................................................238

5.26.1.1 Non-Descriptor Mode .............................................................2385.26.1.2 Descriptor Mode....................................................................239

5.26.2 Flash Descriptor ..................................................................................2405.26.2.1 Descriptor Master Region........................................................241

5.26.3 Flash Access .......................................................................................2415.26.3.1 Direct Access Security............................................................2425.26.3.2 Register Access Security.........................................................242

5.26.4 Serial Flash Device Compatibility Requirements .......................................2425.26.4.1 PCH SPI Based BIOS Requirements..........................................2425.26.4.2 Integrated LAN Firmware SPI Flash Requirements......................2435.26.4.3 IntelManagement Engine Firmware (IntelME FW) SPI Flash

Requirements ....................................................................... 2435.26.4.4 Hardware Sequencing Requirements ........................................244

5.26.5 Multiple Page Write Usage Model ...........................................................2455.26.5.1 Soft Flash Protection..............................................................2455.26.5.2 BIOS Range Write Protection...................................................2465.26.5.3 SMI# Based Global Write Protection.........................................246

5.26.6 Flash Device Configurations ..................................................................2465.26.7 SPI Flash Device Recommended Pinout...................................................2465.26.8 Serial Flash Device Package ..................................................................247

5.26.8.1 Common Footprint Usage Model ..............................................2475.26.8.2 Serial Flash Device Package Recommendations..........................247

5.26.9 PWM Outputs (Server/Workstation Only) ................................................2475.26.10 TACH Inputs (Server/Workstation Only) .................................................248

5.27 Feature Capability Mechanism ...........................................................................2485.28 PCH Display Interface and IntelFlexible Display Interface (IntelFDI)

Interconnect ................................................................................................... 2485.28.1 Analog Display Interface Characteristics .................................................249

5.28.1.1 Integrated RAMDAC...............................................................2505.28.1.2 DDC (Display Data Channel) ...................................................250

5.28.2 Digital Display Side Band Signals...........................................................2505.28.2.1 DisplayPort AUX CH ...............................................................2515.28.2.2 DDC (Display Data Channel) ...................................................2515.28.2.3 Hot-Plug Detect.....................................................................2515.28.2.4 Map of Digital Display Side Band Signals Per Display

Configuration........................................................................ 2515.28.2.5 Panel Power Sequencing andBacklight Control .......................... 251

5.28.3 IntelFlexible Display Interface (IntelFDI) ..........................................2525.29 IntelVirtualization Technology (IntelVT)........................................................253

5.29.1 IntelVirtualization Technology (IntelVT) forDirected I/O (IntelVT-d) Objectives..................................................... 253

5.29.2 IntelVT-d Features Supported ............................................................2535.29.3 Support for Function Level Reset (FLR) in PCH.........................................2535.29.4 Virtualization Support for PCH IOxAPIC...................................................2545.29.5 Virtualization Support for High Precision Event Timer (HPET) .....................254

6 Ballout Definition ...................................................................................................2556.1 Desktop/Server PCH Ballout ..............................................................................2556.2 Mobile PCH Ballout...........................................................................................264

7 Package Information .............................................................................................2727.1 Desktop/Server PCH Package ............................................................................272

7.1.1 Tape and Reel Pin 1 Placement..............................................................2727.2 Mobile PCH Package.........................................................................................274

7.2.1 Tape and Reel Pin 1 Placement..............................................................274


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8 Electrical Characteristics ....................................................................................... 2768.1 Thermal Specifications ..................................................................................... 276

8.1.1 Storage Specifications and Thermal Design Power (TDP) .......................... 2768.2 Absolute Maximum Ratings............................................................................... 2778.3 PCH Power Supply Range ................................................................................. 2778.4 General DC Characteristics ............................................................................... 2788.5 Display DC Characteristics................................................................................ 2878.6 AC Characteristics ........................................................................................... 2888.7 Power Sequencing and Reset Signal Timings ....................................................... 2998.8 Power Management Timing Diagrams................................................................. 3038.9 AC Timing Diagrams ........................................................................................ 3088.10 Sequencing Rails Within The Same Well ............................................................. 319

9 Register and Memory Mapping............................................................................... 3209.1 PCI Devices and Functions................................................................................ 3219.2 PCI Configuration Map ..................................................................................... 3229.3 I/O Map ......................................................................................................... 322

9.3.1 Fixed I/O Address Ranges .................................................................... 3229.3.2 Variable I/O Decode Ranges ................................................................. 324

9.4 Memory Map................................................................................................... 3259.4.1 Boot-Block Update Scheme .................................................................. 327

10 Chipset Configuration Registers............................................................................. 329

10.1 Chipset Configuration Registers (Memory Space)................................................. 32910.1.1 RPCRoot Port Configuration Register ................................................... 33110.1.2 RPFNRoot Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................ 33110.1.3 FLRSTATFunction Level Reset Pending Status Register........................... 33310.1.4 TRSRTrap Status Register.................................................................. 33310.1.5 TRCRTrapped Cycle Register .............................................................. 33410.1.6 TWDRTrapped Write Data Register...................................................... 33410.1.7 IOTRnI/O Trap Register (03) ............................................................ 33510.1.8 V0CTLVirtual Channel 0 Resource Control Register................................ 33610.1.9 V0STSVirtual Channel 0 Resource Status Register................................. 33610.1.10 V1CTLVirtual Channel 1 Resource Control Register................................ 33610.1.11 V1STSVirtual Channel 1 Resource Status Register................................. 33710.1.12 RECRoot Error Command Register ...................................................... 33710.1.13 LCAPLink Capabilities Register............................................................ 33710.1.14 LCTLLink Control Register.................................................................. 33810.1.15 LSTSLink Status Register................................................................... 338

10.1.16 TCTLTCO Configuration Register........................................................ 33810.1.17 D31IPDevice 31 Interrupt Pin Register ................................................ 33910.1.18 D30IPDevice 30 Interrupt Pin Register ................................................ 33910.1.19 D29IPDevice 29 Interrupt Pin Register ................................................ 34010.1.20 D28IPDevice 28 Interrupt Pin Register ................................................ 34010.1.21 D27IPDevice 27 Interrupt Pin Register ................................................ 34110.1.22 D26IPDevice 26 Interrupt Pin Register ................................................ 34210.1.23 D25IPDevice 25 Interrupt Pin Register ................................................ 34210.1.24 D22IPDevice 22 Interrupt Pin Register ................................................ 34210.1.25 D20IPDevice 20 Interrupt Pin Register ................................................ 34310.1.26 D31IRDevice 31 Interrupt Route Register ............................................ 34310.1.27 D30IRDevice 30 Interrupt Route Register ............................................ 34410.1.28 D29IRDevice 29 Interrupt Route Register ............................................ 34410.1.29 D28IRDevice 28 Interrupt Route Register ............................................ 34510.1.30 D27IRDevice 27 Interrupt Route Register ............................................ 34610.1.31 D26IRDevice 26 Interrupt Route Register ............................................ 34710.1.32 D25IRDevice 25 Interrupt Route Register ............................................ 348

10.1.33 D22IRDevice 22 Interrupt Route Register ............................................ 34910.1.34 D20IRDevice 20 Interrupt Route Register ............................................ 35010.1.35 OICOther Interrupt Control Register.................................................... 35110.1.36 WADT_ACWake Alarm Device Timer AC Register................................ 35110.1.37 WADT_DCWake Alarm Device Timer DC Register ............................... 35110.1.38 WADT_EXP_ACWake Alarm Device Expired Timer AC

Register............................................................................................. 35210.1.39 WADT_EXP_DCWake Alarm Device Expired Timer DC

Register............................................................................................. 35210.1.40 PRSTSPower and Reset Status Register ............................................... 352


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10 Datasheet

10.1.41 PM_CFGPower Management Configuration Register ...............................35310.1.42 DEEP_S3_POLDeep Sx From S3 Power Policies Register ......................... 35510.1.43 DEEP_S4_POLDeep Sx From S4 Power Policies Register ......................... 35510.1.44 DEEP_S5_POLDeep Sx From S5 Power Policies Register ......................... 35510.1.45 DSX_CFGDeep Sx Configuration Register .............................................35610.1.46 PMSYNC_CFGPMSYNC Configuration.................................................... 35610.1.47 RCRTC Configuration Register............................................................. 35710.1.48 HPTCHigh Precision Timer Configuration Register ..................................35710.1.49 GCSGeneral Control and Status Register ..............................................35810.1.50 BUCBacked Up Control Register ..........................................................35910.1.51 FDFunction Disable Register ...............................................................35910.1.52 CGClock Gating Register ....................................................................36110.1.53 FDSWFunction Disable SUS Well Register............................................. 36210.1.54 DISPBDFDisplay Bus, Device and Function

Initialization Register ........................................................................... 36210.1.55 FD2Function Disable 2 Register........................................................... 362

11 Gigabit LAN Configuration Registers ...................................................................... 36311.1 Gigabit LAN Configuration Registers

(Gigabit LAND25:F0) ..................................................................................... 36311.1.1 VIDVendor Identification Register

(Gigabit LAND25:F0).........................................................................36411.1.2 DIDDevice Identification Register

(Gigabit LAND25:F0).........................................................................36411.1.3 PCICMDPCI Command Register

(Gigabit LAND25:F0).........................................................................36511.1.4 PCISTSPCI Status Register

(Gigabit LAND25:F0).........................................................................36511.1.5 RIDRevision Identification Register

(Gigabit LAND25:F0).........................................................................36611.1.6 CCClass Code Register

(Gigabit LAND25:F0).........................................................................36611.1.7 CLSCache Line Size Register

(Gigabit LAND25:F0).........................................................................36711.1.8 PLTPrimary Latency Timer Register

(Gigabit LAND25:F0).........................................................................36711.1.9 HEADTYPHeader Type Register

(Gigabit LAND25:F0).........................................................................36711.1.10 MBARAMemory Base Address Register A

(Gigabit LAND25:F0).........................................................................367

11.1.11 MBARBMemory Base Address Register B(Gigabit LAND25:F0).........................................................................368

11.1.12 MBARCMemory Base Address Register C(Gigabit LAND25:F0).........................................................................368

11.1.13 SVIDSubsystem Vendor ID Register(Gigabit LAND25:F0).........................................................................368

11.1.14 SIDSubsystem ID Register(Gigabit LAND25:F0).........................................................................369

11.1.15 ERBAExpansion ROM Base Address Register(Gigabit LAND25:F0).........................................................................369

11.1.16 CAPPCapabilities List Pointer Register(Gigabit LAND25:F0).........................................................................369

11.1.17 INTRInterrupt Information Register(Gigabit LAND25:F0).........................................................................369

11.1.18 MLMGMaximum Latency / Minimum Grant Register(Gigabit LAND25:F0).........................................................................369

11.1.19 STCLSystem Time Control Low Register

(Gigabit LAND25:F0).........................................................................37011.1.20 STCHSystem Time Control High Register

(Gigabit LAND25:F0).........................................................................37011.1.21 LTRCAPSystem Time Control High Register

(Gigabit LAND25:F0).........................................................................37011.1.22 CLIST1Capabilities List Register 1

(Gigabit LAND25:F0).........................................................................37111.1.23 PMCPCI Power Management Capabilities Register

(Gigabit LAND25:F0).........................................................................371


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12 Datasheet

12.1.27 GEN4_DECLPC I/F Generic Decode Range 4 Register(LPC I/FD31:F0) ............................................................................... 391

12.1.28 ULKMCUSB Legacy Keyboard / MouseControl Register(LPC I/FD31:F0)......................................................... 391

12.1.29 LGMRLPC I/F Generic Memory Range Register(LPC I/FD31:F0) ............................................................................... 392

12.1.30 BIOS_SEL1BIOS Select 1 Register(LPC I/FD31:F0) ............................................................................... 393

12.1.31 BIOS_SEL2BIOS Select 2 Register(LPC I/FD31:F0) ............................................................................... 394

12.1.32 BIOS_DEC_EN1BIOS Decode EnableRegister (LPC I/FD31:F0)................................................................... 394

12.1.33 BIOS_CNTLBIOS Control Register(LPC I/FD31:F0) ............................................................................... 396

12.1.34 FDCAPFeature Detection Capability ID Register(LPC I/FD31:F0) ............................................................................... 396

12.1.35 FDLENFeature Detection Capability Length Register(LPC I/FD31:F0) ............................................................................... 397

12.1.36 FDVERFeature Detection Version Register(LPC I/FD31:F0) ............................................................................... 397

12.1.37 FVECIDXFeature Vector Index Register(LPC I/FD31:F0) ............................................................................... 397

12.1.38 FVECDFeature Vector Data Register(LPC I/FD31:F0) ............................................................................... 397

12.1.39 Feature Vector Space...........................................................................39812.1.39.1 FVEC0Feature Vector Register 0............................................ 39812.1.39.2 FVEC1Feature Vector Register 1............................................ 39912.1.39.3 FVEC2Feature Vector Register 2............................................ 39912.1.39.4 FVEC3Feature Vector Register 3............................................ 399

12.1.40 RCBARoot Complex Base Address Register(LPC I/FD31:F0) ............................................................................... 400

12.2 DMA I/O Registers ...........................................................................................40012.2.1 DMABASE_CADMA Base and Current Address Registers .........................40112.2.2 DMABASE_CCDMA Base and Current Count Registers ............................40212.2.3 DMAMEM_LPDMA Memory Low Page Registers ......................................40212.2.4 DMACMDDMA Command Register........................................................40312.2.5 DMASTADMA Status Register..............................................................40312.2.6 DMA_WRSMSKDMA Write Single Mask Register.....................................40412.2.7 DMACH_MODEDMA Channel Mode Register ..........................................40412.2.8 DMA Clear Byte Pointer Register............................................................40512.2.9 DMA Master Clear Register....................................................................40512.2.10 DMA_CLMSKDMA Clear Mask Register .................................................40512.2.11 DMA_WRMSKDMA Write All Mask Register............................................406

12.3 Timer I/O Registers..........................................................................................40612.3.1 TCWTimer Control Word Register ........................................................40712.3.2 SBYTE_FMTInterval Timer Status Byte Format Register..........................40912.3.3 Counter Access Ports Register ...............................................................409

12.4 8259 Interrupt Controller (PIC) Registers............................................................41012.4.1 Interrupt Controller I/O MAP .................................................................41012.4.2 ICW1Initialization Command Word 1 Register .......................................41012.4.3 ICW2Initialization Command Word 2 Register .......................................41112.4.4 ICW3Master Controller Initialization Command

Word 3 Register .................................................................................. 41212.4.5 ICW3Slave Controller Initialization Command

Word 3 Register .................................................................................. 41212.4.6 ICW4Initialization Command Word 4 Register .......................................41212.4.7 OCW1Operational Control Word 1 (Interrupt Mask)

Register ............................................................................................. 41312.4.8 OCW2Operational Control Word 2 Register ...........................................41312.4.9 OCW3Operational Control Word 3 Register ...........................................41412.4.10 ELCR1Master Controller Edge/Level Triggered Register ..........................41512.4.11 ELCR2Slave Controller Edge/Level Triggered Register ............................ 416

12.5 Advanced Programmable Interrupt Controller (APIC) ............................................41712.5.1 APIC Register Map...............................................................................41712.5.2 INDIndex Register ............................................................................41712.5.3 DATData Register .............................................................................41812.5.4 EOIREOI Register .............................................................................418


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12.5.5 IDIdentification Register.................................................................... 41912.5.6 VERVersion Register ......................................................................... 41912.5.7 REDIR_TBLRedirection Table Register ................................................. 420

12.6 Real Time Clock Registers................................................................................. 42112.6.1 I/O Register Address Map..................................................................... 42112.6.2 Indexed Registers ............................................................................... 422

12.6.2.1 RTC_REGARegister A .......................................................... 42312.6.2.2 RTC_REGBRegister B (General Configuration) ........................ 42412.6.2.3 RTC_REGCRegister C (Flag Register)..................................... 42512.6.2.4 RTC_REGDRegister D (Flag Register) .................................... 425

12.7 Processor Interface Registers............................................................................ 42512.7.1 NMI_SCNMI Status and Control Register.............................................. 42612.7.2 NMI_ENNMI Enable (and Real Time Clock Index)

Register............................................................................................. 42612.7.3 PORT92Init Register ......................................................................... 42712.7.4 COPROC_ERRCoprocessor Error Register ............................................. 42712.7.5 RST_CNTReset Control Register ......................................................... 427

12.8 Power Management Registers ........................................................................... 42812.8.1 Power Management PCI Configuration Registers

(PMD31:F0)..................................................................................... 42812.8.1.1 GEN_PMCON_1General PM Configuration 1 Register

(PMD31:F0)....................................................................... 42812.8.1.2 GEN_PMCON_2General PM Configuration 2 Register

(PMD31:F0)....................................................................... 43012.8.1.3 GEN_PMCON_3General PM Configuration 3 Register

(PMD31:F0)....................................................................... 43112.8.1.4 GEN_PMCON_LOCKGeneral Power Management Configuration

Lock Register ....................................................................... 43412.8.1.5 BM_BREAK_EN_2 Register #2 (PMD31:F0) ............................ 43412.8.1.6 BM_BREAK_EN Register (PMD31:F0)..................................... 43512.8.1.7 GPI_ROUTGPI Routing Control Register

(PMD31:F0)....................................................................... 43612.8.1.8 GPI_ROUT2GPI Routing Control Register #2 (PM-D31:F0) ....... 437

12.8.2 APM I/O Decode Register ..................................................................... 43712.8.2.1 APM_CNTAdvanced Power Management Control Port Register... 43712.8.2.2 APM_STSAdvanced Power Management Status Port Register.... 438

12.8.3 Power Management I/O Registers.......................................................... 43812.8.3.1 PM1_STSPower Management 1 Status Register ...................... 43912.8.3.2 PM1_ENPower Management 1 Enable Register........................ 44012.8.3.3 PM1_CNTPower Management 1 Control Register..................... 44112.8.3.4 PM1_TMRPower Management 1 Timer Register....................... 44212.8.3.5 GPE0_STSGeneral Purpose Event 0 Status Register ................ 44212.8.3.6 GPE0_ENGeneral Purpose Event 0 Enables Register ................ 44512.8.3.7 SMI_ENSMI Control and Enable Register................................ 44612.8.3.8 SMI_STSSMI Status Register ............................................... 44812.8.3.9 ALT_GPI_SMI_ENAlternate GPI SMI Enable Register ............... 45012.8.3.10 ALT_GPI_SMI_STSAlternate GPI SMI Status Register .............. 45012.8.3.11 GPE_CNTLGeneral Purpose Control Register........................... 45012.8.3.12 DEVACT_STSDevice Activity Status Register .......................... 45112.8.3.13 PM2_CNTPower Management 2 Control Register ..................... 45212.8.3.14 ALT_GPI_SMI_EN2Alternate GPI SMI Enable 2 Register ........... 45212.8.3.15 ALT_GPI_SMI_STS2Alternate GPI SMI Status 2 Register.......... 452

12.9 System Management TCO Registers................................................................... 45312.9.1 TCO_RLDTCO Timer Reload and Current Value Register ......................... 45412.9.2 TCO_DAT_INTCO Data In Register...................................................... 45412.9.3 TCO_DAT_OUTTCO Data Out Register ................................................. 45412.9.4 TCO1_STSTCO1 Status Register......................................................... 45412.9.5 TCO2_STSTCO2 Status Register......................................................... 45512.9.6 TCO1_CNTTCO1 Control Register........................................................ 45612.9.7 TCO2_CNTTCO2 Control Register........................................................ 45712.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers...................................... 45812.9.9 TCO_WDCNTTCO Watchdog Control Register........................................ 45812.9.10 SW_IRQ_GENSoftware IRQ Generation Register ................................... 45812.9.11 TCO_TMRTCO Timer Initial Value Register ........................................... 458

12.10 General Purpose I/O Registers .......................................................................... 45912.10.1 GPIO_USE_SELGPIO Use Select Register ............................................. 46012.10.2 GP_IO_SELGPIO Input/Output Select Register...................................... 460


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Datasheet 15

13.1.28 PCPCI Power Management Capabilities Register(SATAD31:F2) .................................................................................. 480

13.1.29 PMCSPCI Power Management Control and StatusRegister (SATAD31:F2)...................................................................... 480

13.1.30 MSICIMessage Signaled Interrupt CapabilityIdentification Register (SATAD31:F2) ................................................... 481

13.1.31 MSIMCMessage Signaled Interrupt MessageControl Register (SATAD31:F2) ........................................................... 481

13.1.32 MSIMAMessage Signaled Interrupt MessageAddress Register (SATAD31:F2) .......................................................... 482

13.1.33 MSIMDMessage Signaled Interrupt MessageData Register (SATAD31:F2)............................................................... 483

13.1.34 MAPAddress Map Register (SATAD31:F2)........................................... 48313.1.35 PCSPort Control and Status Register (SATAD31:F2) ............................ 48313.1.36 SCLKCGSATA Clock Gating Control Register ......................................... 48613.1.37 SGCSATA General Configuration Register............................................. 48613.1.38 SATACR0SATA Capability Register 0 (SATAD31:F2)............................. 48713.1.39 SATACR1SATA Capability Register 1 (SATAD31:F2)............................. 48713.1.40 FLRCIDFLR Capability Identification Register (SATAD31:F2) ................. 48813.1.41 FLRCLVFLR Capability Length and Version Register (SATAD31:F2)......... 48813.1.42 FLRCFLR Control Register (SATAD31:F2) ........................................... 48813.1.43 ATCAPM Trapping Control Register (SATAD31:F2) ............................... 48913.1.44 ATSAPM Trapping Status Register (SATAD31:F2)................................ 48913.1.45 SPScratch Pad Register (SATAD31:F2) .............................................. 48913.1.46 BFCSBIST FIS Control/Status Register (SATAD31:F2).......................... 48913.1.47 BFTD1BIST FIS Transmit Data1 Register (SATAD31:F2)....................... 49113.1.48 BFTD2BIST FIS Transmit Data2 Register (SATAD31:F2)....................... 491

13.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 49213.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2)......................... 49313.2.2 BMIS[P,S]Bus Master IDE Status Register (D31:F2).............................. 49313.2.3 BMID[P,S]Bus Master IDE Descriptor Table Pointer

Register (D31:F2) ............................................................................... 49413.2.4 AIRAHCI Index Register (D31:F2)....................................................... 49413.2.5 AIDRAHCI Index Data Register (D31:F2) ............................................. 495

13.3 Serial ATA Index/Data Pair Superset Registers .................................................... 49513.3.1 SINDXSerial ATA Index Register (D31:F2) ........................................... 49513.3.2 SDATASerial ATA Data Register (D31:F2) ............................................ 496

13.3.2.1 PxSSTSSerial ATA Status Register (D31:F2)........................... 49613.3.2.2 PxSCTLSerial ATA Control Register (D31:F2).......................... 49713.3.2.3 PxSERRSerial ATA Error Register (D31:F2) ............................ 498

13.4 AHCI Registers (D31:F2) .................................................................................. 49913.4.1 AHCI Generic Host Control Registers (D31:F2)........................................ 500

13.4.1.1 CAPHost Capabilities Register (D31:F2)................................. 50013.4.1.2 GHCGlobal PCH Control Register (D31:F2)............................. 50113.4.1.3 ISInterrupt Status Register (D31:F2).................................... 50213.4.1.4 PIPorts Implemented Register (D31:F2) ................................ 50313.4.1.5 VSAHCI Version Register (D31:F2) ....................................... 50413.4.1.6 EM_LOCEnclosure Management Location Register (D31:F2) ..... 50413.4.1.7 EM_CTRLEnclosure Management Control Register (D31:F2) ..... 50413.4.1.8 CAP2HBACapabilities Extended Register ............................... 50513.4.1.9 RSTFIntelRST Feature Capabilities Register......................... 506

13.4.2 Port Registers (D31:F2) ....................................................................... 50713.4.2.1 PxCLBPort [5:0] Command List Base Address Register

(D31:F2) ............................................................................. 50913.4.2.2 PxCLBUPort [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ...................................................... 51013.4.2.3 PxFBPort [5:0] FIS Base Address Register (D31:F2)................ 51013.4.2.4 PxFBUPort [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2) ................................................................. 51013.4.2.5 PxISPort [5:0] Interrupt Status Register (D31:F2).................. 51113.4.2.6 PxIEPort [5:0] Interrupt Enable Register (D31:F2).................. 51213.4.2.7 PxCMDPort [5:0] Command Register (D31:F2)....................... 51313.4.2.8 PxTFDPort [5:0] Task File Data Register (D31:F2) .................. 51513.4.2.9 PxSIGPort [5:0] Signature Register (D31:F2)......................... 51613.4.2.10 PxSSTSPort [5:0] Serial ATA Status Register (D31:F2)............ 51613.4.2.11 PxSCTLPort [5:0] Serial ATA Control Register (D31:F2) ........... 51713.4.2.12 PxSERRPort [5:0] Serial ATA Error Register (D31:F2).............. 518


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16 Datasheet

13.4.2.13 PxSACTPort [5:0] Serial ATA Active Register (D31:F2)............. 51913.4.2.14 PxCIPort [5:0] Command Issue Register (D31:F2) ..................520

14 SATA Controller Registers (D31:F5) ....................................................................... 52114.1 PCI Configuration Registers (SATAD31:F5)........................................................521

14.1.1 VIDVendor Identification Register (SATAD31:F5)................................522

14.1.2 DIDDevice Identification Register (SATAD31:F5)................................52214.1.3 PCICMDPCI Command Register (SATAD31:F5)....................................52214.1.4 PCISTSPCI Status Register (SATAD31:F5) ..........................................52314.1.5 RIDRevision Identification Register (SATAD31:F5) ..............................52414.1.6 PIProgramming Interface Register (SATAD31:F5)................................52414.1.7 SCCSub Class Code Register (SATAD31:F5)........................................52414.1.8 BCCBase Class Code Register

(SATAD31:F5SATAD31:F5)................................................................ 52514.1.9 PCMD_BARPrimary Command Block Base Address

Register (SATAD31:F5) ...................................................................... 52514.1.10 PCNL_BARPrimary Control Block Base Address Register

(SATAD31:F5)................................................................................... 52514.1.11 SCMD_BARSecondary Command Block Base Address

Register (SATA D31:F5) ....................................................................... 52614.1.12 SCNL_BARSecondary Control Block Base Address

Register (SATA D31:F5) ....................................................................... 52614.1.13 BARLegacy Bus Master Base Address Register

(SATAD31:F5)................................................................................... 52614.1.14 SIDPBASATA Index/Data Pair Base Address Register

(SATAD31:F5)................................................................................... 52714.1.15 SVIDSubsystem Vendor Identification Register

(SATAD31:F5)................................................................................... 52714.1.16 SIDSubsystem Identification Register (SATAD31:F5) ........................... 52714.1.17 CAPCapabilities Pointer Register (SATAD31:F5)................................... 52714.1.18 INT_LNInterrupt Line Register (SATAD31:F5) .....................................52814.1.19 INT_PNInterrupt Pin Register (SATAD31:F5)....................................... 52814.1.20 IDE_TIMIDE Timing Register (SATAD31:F5)........................................ 52814.1.21 SDMA_CNTSynchronous DMA Control Register

(SATAD31:F5)................................................................................... 52814.1.22 SDMA_TIMSynchronous DMA Timing Register

(SATAD31:F5)................................................................................... 52914.1.23 IDE_CONFIGIDE I/O Configuration Register

(SATAD31:F5)................................................................................... 52914.1.24 PIDPCI Power Management Capability Identification

Register (SATAD31:F5) ...................................................................... 53014.1.25 PCPCI Power Management Capabilities Register

(SATAD31:F5)................................................................................... 53014.1.26 PMCSPCI Power Management Control and Status

Register (SATAD31:F5) ...................................................................... 53014.1.27 MAPAddress Map Register (SATAD31:F5) ...........................................53114.1.28 PCSPort Control and Status Register (SATAD31:F5)............................. 53214.1.29 SATACR0SATA Capability Register 0 (SATAD31:F5) ............................. 53214.1.30 SATACR1SATA Capability Register 1 (SATAD31:F5) ............................. 53314.1.31 FLRCIDFLR Capability ID Register (SATAD31:F5)................................. 53314.1.32 FLRCLVFLR Capability Length and

Value Register (SATAD31:F5)..............................................................53314.1.33 FLRCTRLFLR Control Register (SATAD31:F5)....................................... 53414.1.34 ATCAPM Trapping Control Register (SATAD31:F5) ...............................53414.1.35 ATCAPM Trapping Control Register (SATAD31:F5) ...............................534

14.2 Bus Master IDE I/O Registers (D31:F5)...............................................................53414.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F5) .........................535

14.2.2 BMIS[P,S]Bus Master IDE Status Register (D31:F5) ..............................53614.2.3 BMID[P,S]Bus Master IDE Descriptor Table Pointer

Register (D31:F5)................................................................................ 53614.3 Serial ATA Index/Data Pair Superset Registers.....................................................537

14.3.1 SINDXSATA Index Register (D31:F5)...................................................53714.3.2 SDATASATA Index Data Register (D31:F5)...........................................537

14.3.2.1 PxSSTSSerial ATA Status Register (D31:F5) ...........................53814.3.2.2 PxSCTLSerial ATA Control Register (D31:F5) ..........................53914.3.2.3 PxSERRSerial ATA Error Register (D31:F5).............................540


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Datasheet 17

15 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 54115.1 USB EHCI Configuration Registers

(USB EHCID29:F0, D26:F0) ........................................................................... 54115.1.1 VIDVendor Identification Register

(USB EHCID29:F0, D26:F0)............................................................... 54215.1.2 DIDDevice Identification Register

(USB EHCID29:F0, D26:F0)............................................................... 54215.1.3 PCICMDPCI Command Register

(USB EHCID29:F0, D26:F0)............................................................... 54215.1.4 PCISTSPCI Status Register

(USB EHCID29:F0, D26:F0)............................................................... 54315.1.5 RIDRevision Identification Register

(USB EHCID29:F0, D26:F0)............................................................... 54415.1.6 PIProgramming Interface Register

(USB EHCID29:F0, D26:F0)............................................................... 54515.1.7 SCCSub Class Code Register

(USB EHCID29:F0, D26:F0)............................................................... 54515.1.8 BCCBase Class Code Register

(USB EHCID29:F0, D26:F0)............................................................... 54515.1.9 PMLTPrimary Master Latency Timer Register

(USB EHCID29:F0, D26:F0)............................................................... 54515.1.10 HEADTYPHeader Type Register

(USB EHCID29:F0, D26:F0)............................................................... 54515.1.11 MEM_BASEMemory Base Address Register

(USB EHCID29:F0, D26:F0)............................................................... 54615.1.12 SVIDUSB EHCI Subsystem Vendor ID Register

(USB EHCID29:F0, D26:F0)............................................................... 54615.1.13 SIDUSB EHCI Subsystem ID Register

(USB EHCID29:F0, D26:F0)............................................................... 54615.1.14 CAP_PTRCapabilities Pointer Register

(USB EHCID29:F0, D26:F0)............................................................... 54715.1.15 INT_LNInterrupt Line Register

(USB EHCID29:F0, D26:F0)............................................................... 54715.1.16 INT_PNInterrupt Pin Register

(USB EHCID29:F0, D26:F0)............................................................... 54715.1.17 PWR_CAPIDPCI Power Management Capability

Identification Register (USB EHCID29:F0, D26:F0) ............................... 54715.1.18 NXT_PTR1Next Item Pointer #1 Register

(USB EHCID29:F0, D26:F0)............................................................... 54815.1.19 PWR_CAPPower Management Capabilities Register

(USB EHCID29:F0, D26:F0)............................................................... 54815.1.20 PWR_CNTL_STSPower Management Control /

Status Register (USB EHCID29:F0, D26:F0)......................................... 54915.1.21 DEBUG_CAPIDDebug Port Capability ID Register

(USB EHCID29:F0, D26:F0)............................................................... 54915.1.22 NXT_PTR2Next Item Pointer #2 Register

(USB EHCID29:F0, D26:F0)............................................................... 55015.1.23 DEBUG_BASEDebug Port Base Offset Register

(USB EHCID29:F0, D26:F0)............................................................... 55015.1.24 USB_RELNUMUSB Release Number Register

(USB EHCID29:F0, D26:F0)............................................................... 55015.1.25 FL_ADJFrame Length Adjustment Register

(USB EHCID29:F0, D26:F0)............................................................... 55115.1.26 PWAKE_CAPPort Wake Capability Register

(USB EHCID29:F0, D26:F0)............................................................... 55215.1.27 PDOPort Disable Override Register...................................................... 55215.1.28 RMHDEVRRMH Device Removable Field Register ................................... 55315.1.29 LEG_EXT_CAPUSB EHCI Legacy Support Extended

Capability Register (USB EHCID29:F0, D26:F0).................................... 55315.1.30 LEG_EXT_CSUSB EHCI Legacy Support Extended

Control / Status Register (USB EHCID29:F0, D26:F0)............................ 55415.1.31 SPECIAL_SMIIntelSpecific USB 2.0 SMI Register

(USB EHCID29:F0, D26:F0)............................................................... 55515.1.32 OCMAPOver-Current Mapping Register ................................................ 55715.1.33 RMHWKCTLRMH Wake Control Register ............................................... 55815.1.34 ACCESS_CNTLAccess Control Register

(USB EHCID29:F0, D26:F0)............................................................... 558


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18 Datasheet

15.1.35 EHCIIR1EHCI Initialization Register 1(USB EHCID29:F0, D26:F0) ............................................................... 559

15.1.36 FLR_CIDFunction Level Reset Capability ID Register(USB EHCID29:F0, D26:F0) ............................................................... 559

15.1.37 FLR_NEXTFunction Level Reset Next CapabilityPointer Register (USB EHCID29:F0, D26:F0) ........................................ 559

15.1.38 FLR_CLVFunction Level Reset Capability Length andVersion Register (USB EHCID29:F0, D26:F0)........................................559

15.1.39 FLR_CTRLFunction Level Reset Control Register(USB EHCID29:F0, D26:F0) ............................................................... 560

15.1.40 FLR_STSFunction Level Reset Status Register(USB EHCID29:F0, D26:F0) ............................................................... 560

15.2 Memory-Mapped I/O Registers ..........................................................................56115.2.1 Host Controller Capability Registers .......................................................561

15.2.1.1 CAPLENGTHCapability Registers Length Register .....................56215.2.1.2 HCIVERSIONHost Controller Interface Version Number

Register ............................................................................... 56215.2.1.3 HCSPARAMSHost Controller Structural Parameters ..................56215.2.1.4 HCCPARAMSHost Controller Capability Parameters

Register ............................................................................... 56315.2.2 Host Controller Operational Registers.....................................................564

15.2.2.1 USB2.0_CMDUSB 2.0 Command Register...............................56515.2.2.2 USB2.0_STSUSB 2.0 Status Register.....................................56715.2.2.3 USB2.0_INTRUSB 2.0 Interrupt Enable Register......................56915.2.2.4 FRINDEXFrame Index Register .............................................57015.2.2.5 CTRLDSSEGMENTControl Data Structure Segment

Register ............................................................................... 57115.2.2.6 PERIODICLISTBASEPeriodic Frame List Base Address

Register ............................................................................... 57115.2.2.7 ASYNCLISTADDRCurrent Asynchronous List Address

Register ............................................................................... 57215.2.2.8 CONFIGFLAGConfigure Flag Register .....................................57215.2.2.9 PORTSCPort N Status and Control Register.............................572

15.2.3 USB 2.0-Based Debug Port Registers......................................................57515.2.3.1 CNTL_STSControl / Status Register .......................................57615.2.3.2 USBPIDUSB PIDs Register....................................................57715.2.3.3 DATABUF[7:0]Data Buffer Bytes[7:0] Register .......................57715.2.3.4 CONFIGConfiguration Register..............................................578

16 xHCI Controller Registers (D20:F0)........................................................................ 579

16.1 USB xHCI Configuration Registers(USB xHCID20:F0)........................................................................................57916.1.1 VIDVendor Identification Register

(USB xHCID20:F0)............................................................................58016.1.2 DIDDevice Identification Register

(USB xHCID20:F0)............................................................................58016.1.3 PCICMDPCI Command Register

(USB xHCID20:F0)............................................................................58116.1.4 PCISTSPCI Status Register

(USB xHCID20:F0)............................................................................58216.1.5 RIDRevision Identification Register

(USB xHCID20:F0)............................................................................58316.1.6 PIProgramming Interface Register

(USB xHCID20:F0)............................................................................58316.1.7 SCCSub Class Code Register

(USB xHCID20:F0)............................................................................58316.1.8 BCCBase Class Code Register

(USB xHCID20:F0)............................................................................58316.1.9 PMLTPrimary Master Latency Timer Register

(USB xHCID20:F0)............................................................................58316.1.10 HEADTYPHeader Type Register

(USB xHCID20:F0)............................................................................58416.1.11 MEM_BASE_LMemory Base Address Low Register

(USB xHCID20:F0)............................................................................58416.1.12 MEM_BASE_HMemory Base Address High Register

(USB xHCID20:F0)............................................................................584


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Datasheet 19

16.1.13 SVIDUSB xHCI Subsystem Vendor ID Register(USB xHCID20:F0) ........................................................................... 584

16.1.14 SIDUSB xHCI Subsystem ID Register(USB xHCID20:F0) ........................................................................... 585

16.1.15 CAP_PTRCapabilities Pointer Register(USB xHCID20:F0) ........................................................................... 585

16.1.16 INT_LNInterrupt Line Register(USB xHCID20:F0) ........................................................................... 585

16.1.17 INT_PNInterrupt Pin Register(USB xHCID20:F0) ........................................................................... 585

16.1.18 XHCCxHC System Bus Configuration Register(USB xHCID20:F0) ........................................................................... 585

16.1.19 XHCC2xHC System Bus Configuration Register 2(USB xHCID20:F0) ........................................................................... 586

16.1.20 SBRNSerial Bus Release NumberRegister (USB xHCID20:F0)............................................................... 586

16.1.21 FL_ADJFrame Length Adjustment Register(USB xHCID20:F0) ........................................................................... 587

16.1.22 PWR_CAPIDPCI Power Management Capability IDRegister (USB xHCID20:F0)............................................................... 587

16.1.23 NXT_PTR1Next Item Pointer #1 Register(USB xHCID20:F0) ........................................................................... 588

16.1.24 PWR_CAPPower Management Capabilities Register(USB xHCID20:F0) ........................................................................... 588

16.1.25 PWR_CNTL_STSPower Management Control /Status Register (USB xHCID20:F0)..................................................... 589

16.1.26 MSI_CAPIDMessage Signaled Interrupt Capability ID Register(USB xHCID20:F0) ........................................................................... 589

16.1.27 NEXT_PTR2Next Item Pointer Register #2(USB xHCID20:F0) ........................................................................... 589

16.1.28 MSI_MCTLMSI Message Control Register(USB xHCID20:F0) ........................................................................... 590

16.1.29 MSI_LMADMSI Lower Message Address Register(USB xHCID20:F0) ........................................................................... 590

16.1.30 MSI_UMADMSI Upper Message Address Register(USB xHCID20:F0) ........................................................................... 590

16.1.31 MSI_MDMSI Message Data Register(USB xHCID20:F0) ........................................................................... 591

16.1.32 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1(USB xHCID20:F0) ........................................................................... 591

16.1.33 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2(USB xHCID20:F0) ........................................................................... 591

16.1.34 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1(USB xHCID20:F0) ........................................................................... 592

16.1.35 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2(USB xHCID20:F0) ........................................................................... 593

16.1.36 XUSB2PRxHC USB 2.0 Port Routing Register(USB xHCID20:F0) ........................................................................... 593

16.1.37 XUSB2PRMxHC USB 2.0 Port Routing Mask Register(USB xHCID20:F0) ........................................................................... 594

16.1.38 USB3_PSSENUSB 3.0 Port SuperSpeed Enable Register(USB xHCID20:F0) ........................................................................... 594

16.1.39 USB3PRMUSB 3.0 Port Routing Mask Register(USB xHCID20:F0) ........................................................................... 595

16.1.40 USB2PDOxHCI USB Port Disable Override Register(USB xHCID20:F0) ........................................................................... 595

16.1.41 USB3PDOUSB3 Port Disable Override(USB xHCID20:F0) ........................................................................... 596

16.2 Memory-Mapped I/O Registers.......................................................................... 59616.2.1 Host Controller Capability Registers....................................................... 597

16.2.1.1 CAPLENGTHCapability Registers Length Register..................... 59716.2.1.2 HCIVERSIONHost Controller Interface Version Number

Register...

8 series chipset pch datasheet

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