8085 introduction unit 2

Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF TECHNOLOGY- Durg,India

Email:- [email protected] .

8085 Introduction UNIT-I

MICROPOCESSOR HISTORY :- In 1968 Bob Noyce and Gardon Moore of Fairchild Semiconductor Quit the company And Start their Own . They want to use the name Moore-Noyce for their new company but this Name is already used by Chain of Hotel in US so they decided Integrated Electronics As their company name and this company is known as Intel. Intel released its single 4-bit all-purpose chip, the Intel 4004, in November 1971. It had a clock speed of 108KHz and 2,300 transistors with ports for ROM, RAM, and I/O. Originally designed for use in a calculator intel also had US patent for 4004. After 4004 intel Introduce 4040, which added logical and compare instructions to the 4004. In April 1972 , The Intel 8008 was introduced and it is the basis for the 8080. In the year 1974 Intel Introduce 8080 microprocessor it has 16 bit Address Bus and 8 bit Data Bus. In 1976, Intel updated the 8080 design with the 8085 by adding two instructions to enable/disable three added interrupt pins (and the serial I/O pins). They also simplified hardware so that it used only +5V power, and added clock-generator and bus-controller circuits on the chip.. In 1978, Intel introduced the 8086, a 16-bit processor which gave rise to the x86 architecture. In 1980 the company released the 8087, the first math co-processor they'd developed. There are two Basic Architecture of a microprocessor:- Harvard Architecture Von Neumann Architecture Harvard Architecture

The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard



Mark I relay-based computer, which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache. A Harvard architecture computer can thus be faster for a given circuit complexity because instruction fetches and data access do not contend for a single memory pathway . Von Neumann Architecture

The von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data. It is named after the mathematician and early computer scientist John von Neumann. Such computers implement a universal Turing machine and have a sequential architecture. INTRODUCTION :- The microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. In Another word one can say that microprocessor is a programmable integrated device that has computing and decision making capability. The microprocessor communicate and operate in the binary numbers 0 and 1. Each MP has fixed set of instruction in the form of binary patterns called a Machine Language. Binary patterns are difficult to understand, so the binary pattern are given abbreviated names called mnemonics. Which form the assembly language for given microprocessor.

various computing functions and making decisions to change the sequence



The basic Block Diagram of Micro Computer Above figure consist of two main component ALU(Arithmetic and Logic Unit) and CU ( Control Unit) .these two unit are the main functional unit of any MP but beside these functional unit MP contains a Number of component Like Instruction Register (IR), Program Counter (pc), Stack Pointer (SP), General Purpose Register (GPR),Temporary Register and different set of buses .

Architecture of 8085



The architecture of 8085 can be divided in 5 main group namely 1> The ALU Group 2> Register Array Group 3> Instruction Register, Decoder and Control Group 4> Interrupt Control Group 5> Serial I/O Control Group

The ALU Group :-The ALU performs arithmetic operation such as addition subtraction and logical operation such as ANDing ORing etc. In 8085 input provided to ALU , by 8 bit Accumulator(A) and Temp. Reg.ALU of 8085 is of 8 bit so it can perform any operation on 8 bit data at a tiome.The ALU perform the operation and put the result on 8 bit internal data bus from where it goes to “A”. Accumulator :- It is a 8 bit GPR connected to internal data bus and ALU as shown in above fig.It is the one of the input of the ALU. It is a general purpose nature so it can also used to store 8 bit data Temporarily. Temporary Register :- It is the second input of ALU. It is of 8 bit and not available for programmer. To perform arithmetic and logical operation MP assume that one data is available in A and takes another from other Reg/Mem(depending upon instruction) into temp. reg. and then performs operation on the data. Flag Register :- It is a group of flip-flops. It is connected to ALU. When an operation performed by ALU, the result is transferred on internal data bus and status of result will be stored in F/F.It will only give status if an operation is performed in ALU. Register Group :- It consists of 3 type of register.

1> Temporary register 2> GPR 3> Special Purpose Register

Temporary Register :- The W and Z register are not available for user. It is used by the MP for internal operation such as to store operand, immediate operand or Addr. Of mem.. General Purpose Register(GPR) :- The 8085 contains 6 , 8 bit reg.(other then Accumulator) GPR named as B,C,D,E,H,L. One can store 8 bit data or can be store 16 bit data to form a register pair (RP) , there are 3 register pair available in 8085 named as BC,DE,HL. The content of HL pair represent “M” (memory location) in the Instruction for ex MOV C,M (this instruction move the content of M(Mem. Loc.) to reg. C. This M is defined by HL pair where H holds Upper 8 Bit of Addr. And L holds Lower 8 bit of Addr.. Special Purpose Register (SPR) :- The 8085 contains 3 SPR named as

1> Program Counter (PC) 2> Stack Pointer (SP) 3> Increment Decrement Latch

Program Counter :- It is a memory pointer that’s why it is 16 bit. The MP uses this reg to sequence the execution of the instruction. The function of the PC is to point the mem. Location from which the next byte to be fetched (In case of one byte instruction it point only OPCODE and In case of multiple byte it point first OPCODE then Lower order of data and then Higher Order of data .) Stack Pointer (SP):- It is also memory pointer it points to a memory location in R/W memory called stack. it always point top of the stack.



Increment Decrement Latch :- This 16 bit register is used to increment or decrement the contains of PC & SP. In co ordination with these reg. , two buffers are used (Address Buffer and Addr./Data Buffer). Address Buffer :- 8 bit unidirectional buffer used for A8-A15 addr. Lines thes are used to output higher order address on A8-A15. when they are not in use or under certain condition such as hold ,reset ,halt this buffer is used to tri-state A8-A15 addr. Lines Addr./Data Buffer :- 8 bit bidirectional buffer used for data addr. Thes are used to output lower order Addr./Data on AD0-AD7. under certain condition such as hold ,reset ,halt this buffer is used to tri-state AD0-AD7.Data is taken or transferred on internal data bus and addr.is taken from PC or SP. Instruction Register, Decoder and Control Group:- Instruction Reg.(IR):- When ever instruction is fetched from memory it is loaded in to Addr./Data buffer ,from buffer it is transferred to instruction register.IR is only activated when an instruction is available on internal data bus .It is non Programmable reg. Instruction Decoder :- This accept bit pattern from IR, decode it and gives the decoded information to control logic.the information includes what operation is to be performed who is going to perform it, how many operand byte the instruction contains etc.. Timing and Control:- This is control section of 8085.It accept the information from instruction decoder and generates micro steps to perform it (so 8085 called as micro programmed). It also accept CLK I/P performs sequencing and synchronization operation .The synchronization is required for communication between MP and Peripheral devices. To implement synchronization it was different status and control signal. Interrupt Controller Group:- When a valid interrupt is present, it informs control logic to take action in response to each signal. Serial I/O Control Group:- Serial Data transfer is implemented by 8085 under S/W control for it, it uses SID and SOD Signals.



Pin Configuration Of 8085

A8 - A15 (Output 3 State) Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes. AD0 - 7 (Input/Output 3state) Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes. ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information.



ALE can also be used to strobe the status information. ALE is never 3stated. SO, S1 (Output) Data Bus Status. Encoded status of the bus cycle: S1 S0 O O HALT 0 1 WRITE 1 0 READ 1 1 FETCH S1 can be used as an advanced R/W status. RD (Output 3state) (RD BAR) READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer. WR (Output 3state)(WR BAR) WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes. READY (Input) If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. HOLD (Input) HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M(IO/M BAR) lines are 3stated. HLDA (Output) HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.



INTR (Input) INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. INTA (Output) (INTA BAR) INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD(RD BAR) during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port. RST 5.5 RST 6.5 - (Inputs) RST 7.5 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted. RST 7.5 ~~ Highest Priority RST 6.5 RST 5.5 o Lowest Priority The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR. TRAP (Input) Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt. RESET IN (Input) (RESET IN BAR) Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied. RESET OUT (Output) Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock. X1, X2 (Input)



Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency. CLK (Output) Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period. IO/M (Output) (IO/M BAR) IO/M indicates whether the Read/Write is to memory or I/O Tristated during Hold and Halt modes. If IO/M = 0 then mem. R/W operation other wise I/O R/W Op. SID (Input) Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction. Vcc +5 volt supply. Vss Ground Reference.

Internal register & flag register In 8085 we can classify register in following category Accumulator

Temporary register GPR Special Purpose Register

Accumulator :- It is a 8 bit GPR connected to internal data bus and ALU as shown in above fig. . It is the one of the input of the ALU. It is a general purpose nature so it can also used to store 8 bit data Temporarily. Temporary Register :- The W and Z register are not available for user. It is used by the MP for internal operation such as to store operand, immediate operand or Addr. Of mem.. General Purpose Register(GPR) :- The 8085 contains 6 , 8 bit reg.(other then Accumulator) GPR named as B,C,D,E,H,L. One can store 8 bit data or can be store 16 bit data to form a register pair (RP) , there are 3 register pair available in 8085 named as BC,DE,HL.



The content of HL pair represent “M” (memory location) in the Instruction for ex MOV C,M (this instruction move the content of M(Mem. Loc.) to reg. C. This M is defined by HL pair where H holds Upper 8 Bit of Addr. And L holds Lower 8 bit of Addr.. Special Purpose Register (SPR) :- The 8085 contains 3 SPR named as

Program Counter (PC) Stack Pointer (SP) Increment Decrement Latch

Program Counter :- It is a memory pointer that’s why it is 16 bit. The MP uses this reg to sequence the execution of the instruction. The function of the PC is to point the mem. Location from which the next byte to be fetched (In case of one byte instruction it point only OPCODE and In case of multiple byte it point first OPCODE then Lower order of data and then Higher Order of data .) Stack Pointer (SP):- It is also memory pointer it points to a memory location in R/W memory called stack. it always point top of the stack. Increment Decrement Latch :- This 16 bit register is used to increment or decrement the contains of PC & SP. FLAG REGISTER:-It is 8 bit register ,which is a set of F/F in which five flip-flops are used, which are set or reset after an operation performed by the ALU. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags In Flag Register D1,D3 & D5 bit are not in use CY Flag:- If ALU Generate carry at MSB(D7 bit) the CY flag will be set other wise reset. It work as 9th bit of result. A CY Flag:- If an Operation performed by the ALU, generate carry at MSB of Lower Nibble and pass it to Higher Nibble the A CY will be set . it is used by 8085 for BCD Conversion. It not available for programming. Z Flag:- If operation performed by ALU produce zero(all bit in result is zero) the zero flag will set other wise reset S Flag :- It is called Sign flag and it is the exact copy of D7 bit of result if D7 of result is 1 then S Flag will be set otherwise reset. P Flag:- It is used to maintain ODD PARITY. In other words we can say that including PARITY FLAG the number of ones(1’s) should be odd. Or if the number of 1’s is even in result then P Flag will be set otherwise reset. 1(CY from MSB of Lower Nibble) 1000 1000(88 H) + 1000 1000(88H) ----------------------------

D7 D6 D5 D4 D3 D2 D1 D0

CYP A CY Z S



10001 0000(110H) The ans produce 9th bit, D7 of result is 0,Number of one’s in result odd( do not include 9th bit) , there is carry at MSB of Lower nibble which pass to LSB of Higher Nibble. so the different condition of flag are CY =1(set) A CY=1(set) Z=0(reset) S=0(reset) P=0(reset)

Generation of Control Signals:- The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O. IO/M + WR = MEMW(0+0=0) IO/M +RD= MEMW(0+0=0) (IO/M)’+WR=IOW(0+0=0)(we use invert of IO/M , “ ‘ “ is used to indicate BAR) (IO/M)’+RD=IOR

CKT. Dia. For Gen. OF CTRL Signal As the signal IO/M goes low for memory operation .it negatively NANDed with RD and WR signal to produce memory read and memory write signal. In above diagram we use negative NAND gate and INVERTER gate to produce different signal.

Demultiplexing of address / data bus We know that the AD7– AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7– AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.



Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their purpose as the bi-directional data lines.

Dia. Of 74LS373 It is a transparent latch followed by tri state output buffer. The data from D input are transffered to Q when LE is high and latched when LE goes low. When OC’ goes low latched data appear on the output, otherwise the output remain in high impedance. In Our schematic the OC’ of latch is grounded (not shown in fig.)so whenever ALE is high , the data is transparent;this mean that the output change according to input data i.e. lower order Addr. T- State: One subdivision of an operation. A T-state lasts for one clock period. An instruction’s execution length is usually measured in a number of T-states. (clock cycles). Machine Cycle: The time required to complete one operation of accessing memory, I/O, or acknowledging an external request. This cycle may consist of 3 to 6 T-states.



Instruction Cycle: The time required to complete the execution of an instruction. In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.

Instruction Timings and Operation Status Steps For Fetching an Instruction(Instruction Timing) Lets assume that we are trying to fetch the instruction at memory location 2008H. That means that the program counter is now set to that value. The following is the sequence of operations: The program counter places the address value on the address bus and the controller issues a RD signal. The memory’s address decoder gets the value and determines which memory location is being accessed. The value in the memory location is placed on the data bus. The value on the data bus is read into the instruction decoder inside the microprocessor. After decoding the instruction, the control unit issues the proper control signals to perform the operation.

Timing Signals For Fetching an Instruction At T1 , the high order 8 address bits (20H) are placed on the address lines A8 – A15 and the low order bits are placed on AD7–AD0. The ALE signal goes high to indicate that AD0 – AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory operation. At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7– AD0 and the controller sends the Read (RD) signal to the memory. The signal remains low (active) for two clock periods to allow for slow devices. During T2 , memory places the data from the memory location on the lines AD7– AD0 . During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7– AD0 lines go to high impedence mode.

Opcode Fetch Machine Cycle The first step of executing any instruction is the Opcode fetch cycle. In this cycle, the microprocessor brings in the instruction’s Opcode from memory. To differentiate this machine cycle from the very similar “memory read” cycle, the control & status signals are set as follows: IO/M=0, s0 and s1 are both 1. This machine cycle has four T-states(some time 6 T state). The 8085 uses the first 3 T-states to fetch the opcode. T4 is used to decode and execute it.



SOME POINT TO REMEMBERS Personal Computer:- A small , single user computer based on Microprocessor , also known as Microcomputer. Work Station:- A powerful single user computer. it is like personal computer, but has more powerful microprocessor and system configuration , used in engineering application(CAD/CAM), S/W development work related to high quality graphics. High end PC is equivalent to Low end Work station. (In Networking workstation refers to any computer connected to local area network) Workstation lies between PC and Minicomputer. Minicomputer: - A Multi-user computer capable of supporting 10 to hundreds of user simultaneously. In size and power it lies between workstation and mainframe, minicomputer a term is no longer used. Mainframe:- A very large and expensive computer capable of supporting hundreds or even thousand of user simultaneously . Mainframe is just below to supercomputer. Supercomputer:-An extremely fast computer that can perform hundreds of millions of instruction per second. In the world of microcomputer(PC) the term microprocessor and CPU are used interchangeably. One or more microprocessor can act as Central processing Unit(CPU). RISC ( Reduce Instruction Set Computer) CISC(Complex Instruction Set Computer) General purpose registers are also called “Scratch – Pad” registers. M is also called a “Virtual register”

Some Question Q1:- Define Following Microprocessor(2M) , Machine Language, Assembly Language, High Level Language, Compiler, Interpreter, Assembler, Address Bus, Data Bus, Control Bus, Instruction, Operation Code(opcode) , Operand, Instruction cycle, Machine Cycle, T States, Fetch cycle, Execute Cycle, Mem. Read Cycle, Mem. Write Cycle., Operand Fetch Cycle. Q2:-Explain Microprocessor Initiated Operation. Q3:- Peripheral or Externally Initiated Operation. Q4:-Explain Hardware Model 8085. Q5:- Explain 8085 Programming model. Q6:-Deifine flag register and explain how the flags are affected (with Example). Q7:-Explain the architecture of Microprocessor(with Diagram).



Q8:-What are the different features of 8085. Q9:- Draw the pin configurations of 8085. Q10:- Explain the function of various pins of 8085. Q11:-Draw the logical pinout of 8085 and explain the classification of signals generated at various pin. Q12:- Explain the need and function of control signal. Q13:- explain how control signals are generated. Q14:-How does microprocessor differentiate between data and instruction op code.? Q15:-Explain the need of Demultiplexing of AD0-AD7 and how you can Demultiplex them. Q16:- Explain the function of following register of 8085 Program Counter,Instruction Reg.,Stack Pointer,Flag Reg.,Accumulator. Q17:-Draw and Explain Timing Dia. Of Following M/C Cycle Opcode Fetch, Mem. Read(AkA Operand Fetch),Mem.Write,IO Read,IO write, Bus Idle Machine Cycle, Interrupt Ack M/C Cycle. Q18:-Write Status Signal of various machine cycle. Q19:- Draw and Explain State Transition diagram of 8085. Q20:-How many Pins are multiplexed in 8085. Q21:- which Reg. is known as a Higher order reg. of 8085 and which one is lower order reg. of 8085. Q22:-Explain the function of ALE and IO/M Bar signal. Q23:- Generate control signal for different Read and write operation of 8085 using 74138. Q24:- Mention the general purpose registers in 8085 microprocessor. Q25:- What is the function of accumulator? Q26:- What are the flag registers available in 8085? Q27:- What is buffer? Q28:- Mention the groups of 8085 pin signals. Q29:- Explain the function of program counter. Q30:- What is the function of SP? Q31:- Why HL pair is called a special pair? Q32:- How Accumulator is different from other registers? Q33:- What is memory? Q34:- What are the types of memory? Q35:- What is memory word? Q36:- What are the programming registers in 8085? Q37:- What is memory address? Q38:- What is Opcode? Q39:- What is Operand? Q40:- How many memory locations can be addressed by a microprocessor with 14 address lines? Q41:- How many address lines are necessary to address two megabytes (2048K) of memory? Q42:- How many address lines are necessary to address two megabytes(2048K) of memory? Q43:- Mention the architectural features of 8085 microprocessor Q44:- Explain the function of following pins of 8085 microprocessor: IO/M, ALE, RD, X1 & X2, READY,S0 & S1, WR, AD0

-AD7, HOLD, HLDA

Q45:- Mention the pins of 8085 which are multiplexed. Q46:- Mention the pins of 8085 which obey the followings:

a. Those are acting as input pins



b. Those are acting as output pins c. Those are related to interrupts d. Those are carrying control signals e. Those reflect the status signal f. Those are bidirectional pins g. Those carry data h. Those carry only data i. Those helping serial communication j. Those are used for DMA transfer k. Those are related to clock l. Those can be used to make the CPU wait m. Mention the functions of MEMR , MEMW , IOR and IOW signals? How they are generated?

n. What are micro & macro instructions? Give examples.

8085 introduction unit 2

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