8085 unit-1

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INTEL 8085-Features

• INTEL 8085 is an 8-bit microprocessor.

• The data word size of the 8085 microprocessor is 8-bits.ence has 8-bit data bus.

• The address size of 8085 microprocessor is !"-bits. ence

uses !"-bit address bus.• It can direct#$ process on 8-bits of data in sin%#e operation&

hence it is 'nown to be an 8-bit microprocessor.

• It can direct#$ address (!" ) "5&5*" b$tes i.e.& "+ ,b$tes"+ , memor$ #ocations usin% !"-bits of address.

• 8085 microprocessor is fabricated usin% N/1techno#o%$ and comes in an +0-pin 2I3dua#-in-#ine

pac'a%e.

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INTEL 8085-Features

• It re4uires a sin%#e power supp#$ of 56.

• It has pro7ision of interna# fre4uenc$ %eneration when ancr$sta# is connected between the specified pins.

• The %enerated c#oc' is di7ided b$ a factor of (& hence to

operate an 8085 based s$stem at an fre4uenc$ of * /z&an cr$sta# of " /z fre4uenc$ need to be connected to8085.

• The N/1 8085 is a7ai#ab#e in two 7ersions 8085 and8085-( with ma9imum interna# c#oc' fre4uenc$ of *.0*

/z and 5 /z respecti7e#$ and hence re4uire an cr$sta#of ".0" /z and !0 /z to be connected themrespecti7e#$.

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INTEL 8085-Features

• The enhanced 7ersion of 8085 is desi%ned with /1transistors. It is a7ai#ab#e in three 7ersions 8085&

8085-(& 8085-! with ma9imum interna# c#oc' of

* /z& 5 /z and " /z respecti7e#$.

• The c#oc' c$c#e of 8085 is of order of *(0 ns and that for8085-( 7ersion is (00 ns.

• It has 80 basic instructions and (+" opcodes.

• 8085 is enhanced 7ersion of its predecessor the 8080

microprocessor: thus its instruction set is upwardcompatib#e with that of 8080& i.e.& 8085 instruction set

inc#udes a## the 8080 instructions p#us some more

instructions.

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INTEL 8085-Features

• Thus the pro%rams written for the 8080

wi## be e9ecuted b$ the 8085

microprocessor.

• ;ut 8085 and 8080 are not pin compatib#e&

i.e.& the 8085 microprocessor can not be

used in p#ace of 8080 microprocessor inan 8080 based s$stem.

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INTEL 8085-rchitecture

• The interna# b#oc' dia%ram of 8085

microprocessor consists of the fo##owin% main

sections<

n arithmetic and #o%ic unit

timin% and contro# unit

set of re%isters

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ccumu#ator 1tatusF#a%s

Temporar$=e%ister

rithmeticnd

Lo%ica# >nitL>

Instruction

2ecoder nd

/?@ c$c#eEncodin%

Instruction=e%ister

I=

Timin% nd @ontro#>nit

------------------

A!

A(

@L, @ontro# 1i%na#s

2ata?ddress;uffer ddress

;uffer

Incrementer?2ecrementer ddress #atch

3ro%ram @ounter3@

1tac' 3ointer 13

@;E2L

8-!5

ddress;us

20-2B

ddress?2ata

;us

Interrupt@ontro#

1eria#I? contro#

.

.

.

Interrupt

1i%na#s

1I2

12

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L>

• The arithmetic and #o%ica# unitL>& performs thefo##owin% arithmetic and #o%ica# operations<

ddition

1ubtraction

Lo%ica# N2 Lo%ica# =

Lo%ica# E9c#usi7e-=

@omp#ement Lo%ica# NT

Increment add !

2ecrement1ubtract !

Left shift& =i%ht shift& =otate Left&=otate ri%ht

@#ear CCCCCCe.t.c.

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Timin% nd @ontro# >nit

• It is section of @3>.

• It %enerates timin% and contro# si%na#s which are necessar$

for the e9ecution of instructions

• It contro#s data f#ow between @3> and periphera#s

inc#udin% memor$.

• 3ro7ides status& contro# and timin% si%na#s which are

re4uired for the operation of memor$ and I? de7ices.

• @ontro#s a## the operations of microprocessor and

periphera#s

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=e%isters• =e%isters are used b$ the microprocessor for temporar$

stora%e and manipu#ation of data and instructions.• 2ata remains in the re%ister ti## the$ are sent to the memor$

or I? de7ices.

• INTEL 8085 microprocessor has the fo##owin% re%isters<

ne 8-bit accumu#ator @@ i.e.& =e%ister- 1i9 8-bit %enera# purpose re%isters. These are ;&@&2&E& and L.

ne !"-bit stac' pointer 13

ne !"-bit pro%ram counter 3@

Instruction re%ister

Temporar$ re%ister

Incrementer?2ecrementer

F#a% re%ister a re%ister made up of indi7idua# f#ip-f#ops out of

which on#$ fi7e are acti7e.

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=e%isters

• ccumu#ator< ccumu#ator is an 8-bit re%ister associated with the

L>.

It is used to ho#d one of the operands of an arithmetic or

#o%ica# operation& the other operand is he#d in either one

of the %enera# purpose re%isters or in memor$.

fter the operation is comp#eted the accumu#ator ho#ds

the fina# resu#t.

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=e%isters• Denera# 3urpose =e%isters<

si9 8-bit %enera# purpose re%isters are present in 8085.

The %enera# purpose re%isters present in 8085 microprocessor are<;&@&2&E& and L.

To ho#d !"-bit data a combination of two 8-bit re%isters can beused and are 'nown as re%ister pair.

The 7a#id re%ister pairs in 8085 are< ;-@&2-E and -L. -L pair can be used as an memor$ pointer to access the !"-bit

address of an memor$ #ocation indirect#$.

The %enera# purpose re%isters and accumu#ator are pro%rammeraccessib#e.

;@& 2E and L re%isters are 'nown as scratch pad re%isters. ;asica##$ this re%ister arra$ is #i'e a sma## chip of =/ with

addressab#e memor$ #ocations. ;$ usin% proper contro# si%na#s&the@3> can either #oad a re%ister from the interna# data bus or theoutput of these re%isters to the bus.

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=e%isters

• 3ro%ram @ounter 3@<

It is a !"-bit specia# purpose re%ister.

It is used to ho#d the memor$ address of the ne9t

instruction to be e9ecuted.

It 'eeps the trac' of memor$ address of the instructionsin a pro%ram whi#e the$ are bein% e9ecuted.

The microprocessor increments the contents of the

pro%ram counter durin% the e9ecution of an instruction

so that it points to the address of the ne9t instruction inthe pro%ram at the end of the e9ecution of an

instruction.

It is not pro%rammer accessib#e.

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=e%isters• 1tac' 3ointer 13<

It is a !"-bit specia# function re%ister.The stac' pointer ho#ds the address of the top of the

stac' i.e.& the top most e#ement of data stored in stac'and contro#s the addressin% of the stac' of 8085.

The stac' is a se4uence of memor$ #ocations set aside b$ a pro%rammer to store?retrie7e the contents ofinterna# re%isters of microprocessor such asaccumu#ator&f#a%s&pro%ram counter and %enera# purposere%isters durin% the e9ecution of the pro%ram.

n$ portion of the memor$ can be used as stac'.1tac' wor's on FIFfirst-in-first-out princip#e.

Denera##$ the stac' operations of storin%?retrie7in%shou#d be faster compared to norma# store?retrie7eoperations of memor$ #ocations.

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=e%isters 2urin% the e9ecution of a pro%ram some times it becomes

necessar$ to sa7e the contents of the re%isters which are needed for

some other operations in the subse4uent steps of the pro%ram. Thecontents of such re%isters is sa7ed in stac'.

fter sa7in% the contents in the stac' the re%isters can be used for

some other operations. fter comp#etin% the needed operations the

contents which were sa7ed in the stac' are brou%ht bac' to the

re%isters. The contents of on#$ those re%isters which are needed inthe #ater part of the pro%ram.

The order of the storin% into stac' shou#d be fo##owed b$ the

retrie7in% princip#e of the e#ement stored #ast wi## be retrie7ed first

and 7ice 7ersa.

The stac' is defined and stac' pointer is initia#ized b$ the

pro%rammer at the be%innin% of a pro%ram which needs stac'

operation and then updated due to either stac' instructions in the

pro%ram or b$ the microprocessor whi#e e9ecutin% some of the

instructions #i'e @LL.

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=e%isters• Instruction =e%ister ? 2ecoder <

The instruction re%ister ho#ds the opcode operation code orinstruction code of the instruction which is bein% decoded and

e9ecuted.

The decoder interprets the instruction and produces the proper

si%na#s to carr$ it out.

It is not pro%rammer accessib#e.

• Temporar$ =e%ister<

It is an 8-bit re%ister associated with the L>.

It ho#ds data durin% an arithmetic?#o%ica# operation. It is used b$ the microprocessor.

It is not accessib#e to pro%rammer.

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=e%isters

•Incrementer ? 2ecrementer<The Incrementer ? 2ecrementer a##ows the contents of

an$ of the !"-bit re%isters to be incremented or

decremented& b$ !.

3ro%ram 1tatus Gord<The fi7e bits of the f#a% re%ister which pro7ide the

information about the status of the instruction e9ecution

a#on% with the three undefined bits is 'nown as 31G

pro%ram status word.

Thus the pro%ram status word is the f#a% re%ister of the

microprocessor.

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F#a% =e%ister • The f#a% re%ister of 8085 microprocessor

B " 5 + * ( ! 0

The INTEL 8085 microprocessor contains fi7e f#ip-f#ops to ser7e the

status of the pro%ram?instruction e9ecution as status f#a%s. The f#ip-

f#ops are set or reset accordin% to the conditions which arise durin% an

arithmetic or #o%ica# operation.

The fi7e status f#a%s of INTEL 8085 are <

!. @arr$ F#a% @H(. 3arit$ F#a% 3

*. u9i#iar$ @arr$ F#a% @

+. ero F#a%

5. 1i%n F#a% 1

A 3A@ @H1 A

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F#a% =e%ister • If a f#ip-f#op for a particu#ar f#a% is set& it indicates !. Ghen

it resets it indicates 0. @arr$ F#a% @H<

fter the e9ecution of an arithmetic instruction if a carr$ is

produced& the carr$ f#a% @H is set to !& otherwise it is 0.

The carr$ f#a% is set or reset in case of addition as we## as

subtraction.

fter the addition of ( 8-bit numbers is performed if the resu#t is

%reater than 8-bits& a carr$ is produced& and the carr$ f#a% is set to

!.

In case of subtraction& if the borrow occurs& the carr$ f#a% is set to!.

Thus carr$ f#a% ho#ds the carr$ out of the most si%nificant bit

position resu#tin% from the e9ecution of an arithmetic operation.

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F#a% =e%ister 3arit$ F#a% 3<

The parit$ status f#a% 3 is set to !& if the resu#t of anarithmetic or #o%ica# operation contains e7en number of!Js. It is reset i.e.& it is 0& if the resu#t contains odd numberof !Js

u9i#iar$ @arr$ F#a% @<The u9i#iar$ @arr$ f#a% @ ho#ds carr$ out of the #owermost nibb#e to the ne9t nibb#e i.e.& from bit position * tothe bit position + resu#tin% from the e9ecution of anarithmetic operation.

ero F#a% <

The ero status f#a% is set to !& if the resu#t of anarithmetic or #o%ica# operation is 0.If the resu#t is notzero&the f#a% is reset i.e& set to 0.

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F#a% =e%ister

1i%n F#a% 1<

The 1i%n f#a% 1 is set to !& if the resu#t of an arithmetic or

#o%ica# operation e9ecuted is ne%ati7e. If the resu#t is

positi7e it is reset i.e.& set to 0.

The si%n f#a% has its si%nificance on#$ when si%ned

arithmetic operation is performed.

To represent a si%ned number the most si%nificant bit is

reser7ed b$ the pro%rammer to represent the si%n of a

number i.e.& the /1; is used as a si%n bit which represents

the si%n of the number& if the number is ne%ati7e the si%n bit is ! and if the number is positi7e the si%n bit is 0.

For an 8-bit si%ned number on#$ B-bits are used to

represent the ma%nitude of the number.

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F#a% =e%ister 1i%n F#a% 1<

fter the e9ecution of si%ned arithmetic operation& the/1; of the resu#t represents its si%n.The si%n f#a% ac4uiresthe 7a#ue of the /1; of the resu#t fo##owin% the e9ecutionof the si%ned arithmetic operation. ence& it represents thesi%n of the resu#t.

For unsi%ned arithmetic operations& a## the 8-bits are usedto represent the ma%nitude of the number. fter thee9ecution of an arithmetic operation& a## the 8-bits of theresu#t represents its ma%nitude. Thus the si%n f#a% has no

si%nificance in unsi%ned arithmetic operations.For #o%ica# operations a#so the si%n bit has no si%nificance&as the si%n f#a% is set or reset dependin% on the 7a#ue of the/1; of the resu#t& it is set or reset on the 7a#ue of /1; ofthe resu#t of #o%ica# operations a#so.

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F#a% =e%ister

1i%n F#a% 1<

The si%n f#a% is affected in the simi#ar wa$ for an si%ned

arithmetic operation of !"-bit& *(-bit or more.

In case of !"-bit operation !5-bits are used for representin%

the ma%nitude of the number and the !"th bit is used for

representin% the si%n of the number.

simi#ar#$ in case of *(-bit number *!-bits are used for

representin% the ma%nitude and !-bit is used for

representin% the si%n of the number.

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F#a% =e%ister

• Effect on the f#a% re%ister for e9amp#e of @; EK

@; ) ! ! 0 0 ! 0 ! !

EK ) ! ! ! 0 ! 0 0 !

! --------------------

! 0 ! ! 0 ! 0 0There is a carr$ from bit position * to bit position + thus@ ) !Jset

There is a carr$ from bit position B to bit position 8 thus@H ) !Jset

There is a non zero resu#t thus ) 0J

There are e7en number of !Js thus 3 ) !J

/1; ) ! thus 1 ) !J.

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Functiona# unit of 8085

• The other functiona# b#oc's other than the L> and other

re%isters is as fo##ows< !. Interna# 2ata ;us

(. 1eria# I? @ontro#

*. Interrupt @ontro#

+.Timin% and @ontro#

5. ddress ;uffer and ddress ? 2ata ;uffer

Interna# 2ata ;us<

The interna# data bus is 8-bits inside and carriesinstructions and data between the @3> re%isters.

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• 1eria# I? @ontro# <

Denera##$ the 2ata f#owin% between microprocessor wi## be either para##e# or seria#& but for some de7ices it is

necessar$ to accept data seria##$ and output data seria##$

and if there is a pro7ision bui#t in in the microprocessor for

this purpose it is 7er$ efficient.

In 8085 there is such pro7ision throu%h 1I2 and 12 pins.

The 1I2 pin is used for acceptin% seria# data input.

The 12 pin is used for seria# output.

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• Interrupt @ontro#<

For hand#in% the interrupts of 8085 this b#oc' is pro7ided.There is pro7ision of both hardware and software interrupts in INTEL8085 microprocessor.

ardware Interrupts<

There are fi7e hardware interrupt inputs name#$ T=3& =1T B.5&

=1T ".5& =1T 5.5& INT=.T=3 has the hi%hest priorit$& fo##owed b$ =1T B.5& =1T ".5&=1T 5.5.

INT= has the #owest priorit$.

Ghen these hardware interrupts are used the$ are to be enab#ed b$

enab#in% EI f#ip-f#op usin% software instruction EI Enab#eInterrupt in the main pro%ram.

The use of instruction EI enab#es a## the interrupts.

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The instruction 2I disab#e Interrupts is used to disab#e a##

the interrupts e9cept the non-mas'ab#e interrupt T=3The s$stem reset a#so resets the interrupt enab#e f#a%f#ip-f#op.

Ghen an interrupt #ine %oes hi%h the processor comp#etesits current instruction and sa7es the pro%ram counter on the

stac'. It a#so resets the Interrupt enab#e f#ip-f#op beforeta'in% up I1= so that further occurrence of an$ interrupt isa7oided durin% the e9ecution of current I1=& as a## theinterrupts e9cept T=3 can be pre7ented b$ resettin% theEI f#ip-f#op.

Thus the resettin% of EI f#ip-f#op can be done usin% threedifferent wa$s < ;$ software instruction 2I& 1$stem resetor ;$ reco%nition of an interrupt re4uest.

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;efore the pro%ram returns bac' from the I1= to the main

pro%ram a## the interrupts are to be enab#ed usin% theinstruction EI before =ET instruction in the I1=.

1oftware Interrupts<

There is pro7ision for 1oftware interrupts a#so for 8085

microprocessor usin% =1T n where n ) !&(C.B.

Ghen =1T n instruction is inserted in a pro%ram & the

pro%ram is e9ecuted upto the point where =1T n has

been inserted. This is used in debu%%in% of a pro%ram.

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• The interrupts of the 8085 microprocessor are 7ectored

interrupts and the pro%ram contro# is transferredautomatica##$ to a particu#ar address which is 'nown as

7ector address of the interrupt.

Interrupt @a##-#ocation in EA

T=3 00(+=1T B.5 00*@

=1T ".5 00*+

=1T 5.5 00(@

=1T B.5&=1T ".5& =1T5.5 are mas'ab#e interrupts. These interrupts

are enab#ed b$ software usin% instructions EI and 1I/ 1et Interrupt

/as'. The e9ecution of the instruction 1I/ enab#es ? 2isab#es

interrupts accordin% to the bit 3attern of the accumu#ator.

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• ccumu#ator contents for a 1I/ instruction<

12 1E A = B.5 /1E / B.5 / ".5 / 5.5

=1T 5.5 /1,

=1T ".5 /1,

=1T B.5 /1,

/1, 1ET EN;LE

=eset =1T B.5

>ndefined

1eria# utput 2ata

12 Enab#e

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=1T n EA-@ode @LL-Locations

=1T 0 @B 0000

=1T ! @F 0008

=1T ( 2B 00!0

=1T * 2F 00!8=1T + EB 00(0

=1T 5 EF 00(8

=1T " FB 00*0

=1T B FF 00*8

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• Timin% and @ontro#<

This section is a part of the @3> and %enerates timin% andcontro# si%na#s for the e9ecution of instructions. ;asica##$

this section inc#udes an osci##ator and contro##er se4uence.

The contro# si%na#s of this unit contro#s data f#ow between

@3> and periphera#s: and contro#s the entire operations ofthe microprocessor and the periphera#s connected to it.

• ddress ;uffer and ddress ? 2ata ;uffer<

The contents of stac' pointer or pro%ram counter can be

#oaded into these buffers. These buffers dri7e the e9terna#address bus and address-data bus. The interna# data bus is

a#so connected to the address ? data buffer to send or

recei7e the data.

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2ata and ddress ;us

• The INTEL 8085 is an 8-bit microprocessor. Its data bus is8-bit wide and hence& 8 bits of data can be transmitted in

para##e# from or to the microprocessor.

• The INTEL 8085 re4uires a !"-bit wide address bus as thememor$ address are of !"-bits.

• The 8 most si%nificant bits of the address are transmitted

b$ the address bus& -bus pins 8 M !5.• The 8 #east si%nificant bits of the address are transmitted

b$ ddress ? 2ata bus& 2- bus pins 20 M 2B.

• The ddress ? 2ata bus transmits data and address at

different moments. t a particu#ar moment it transmitseither data or address. Thus the 2 M bus operates in timeshared mode. This techni4ue is 'nown as Time/u#tip#e9in% .

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INTEL

8085

611

6@@

A!

A(

=eset In

=eset ut

I?/

10

1!

=2

G=

LE

1I2

12

=E2H

20 M 2B

8 M !5

@L, >T

L2

L2

T=3

=1T B.5

=1T ".5

=1T 5.5

INT=

INT

3in @onfi%uration f 8085

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• The #o%ica# pin out of an 8085 microprocessor consists of

an +0-pin 2I3 pac'a%e.

• The pins of the 8085 microprocessor can be cate%orized int

the fo##owin% %roups<

ddress bus

2ata bus

@ontro# and 1tatus si%na#s

3ower 1upp#$ and Fre4uenc$ si%na#s

E9terna##$ initiated si%na#s

1eria# I? ports

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• ddress ;us< 8 M !5

utput and Tri-stated #ines These are the address bus and are used for the most

si%nificant bits of the memor$ address or 8-bits of I?address

/u#tip#e9ed ddress ? 2ata ;us < 20 M 2B ;i-directiona# and Tri-stated #ines

These are time mu#tip#e9ed address ? data bus I.e.&the$ ser7e dua# purpose. The$ are used for the #eastsi%nificant 8-bits of memor$ address or I? address

durin% the first c#oc' c$c#e of the machine c$c#e. For the remainin% period of the machine c$c#e the$

are used to carr$ data to?from the specified #ocation orde7ice.

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• @ontro# and 1tatus si%na#s<

This %roup of si%na#s inc#udes two contro# si%na#s =2

and G=& three status si%na#s I?/ & 1! and 10 to

identif$ the nature of the operation& and one specia# si%na#

LE to indicate the be%innin% of the operation. Thesesi%na#s are as fo##ows<

LE M ddress Latch Enab#e<

utput and Tri-stated #ine

It is a ddress Latch Enab#e si%na#. It %oes hi%h durin%the first c#oc' c$c#e of a machine c$c#e and enab#es the#ower 8 bits of the address to be #atched either into thememor$ or e9terna# #atch.

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3in @onfi%uration f 8085•

=2 < =ead

utput and a tri-stated #ine

It is a si%na# to contro# read operation

Ghen it %oes #ow the microprocessor reads the data fromthe se#ected memor$ #ocation or an I? de7ice.

•

G= < Grite

utput and Tri-stated #ine

It is a si%na# to contro# Grite operation

Ghen it %oes #ow the microprocessor writes the data intothe se#ected memor$ or I? de7ice.

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• .

I?/ < I? or /emor$ indicator utput and Tri-stated #ine.

It is a status si%na# which distin%uishes whether the

ddress is for /emor$ or I?.

Ghen it %oes hi%h the address is for an I? de7ice and

when it %oes #ow the address on the address bus is for a

memor$ #ocation.

• 1! and 10 < ;us state? status indicator

utput #ines.

The status output si%na#s from microprocessor and these

si%na#s %i7es the information about the 7arious t$pes of

operations that ta'e p#ace.

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. 1! 10 perations

0 0 LT0 ! G=ITE

! 0 =E2

! ! FET@

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• 3ower 1upp#$ and @#oc' Fre4uenc$ 1i%na#s

The power supp#$ and fre4uenc$ si%na#s are as fo##ows<

6@@ < 5 6 3ower 1upp#$

611 < Dround =eference

A! and A( < @r$sta# or =@ @onnections

Input #ines

These are termina#s to be connected to an e9terna# cr$sta#

osci##ator which dri7es an interna# circuitr$ of themicroprocessor to produce a suitab#e c#oc' for theoperation of microprocessor.

@L,ut < @#oc' si%na#utput #ine

It is a @#oc' utput for user&which can be used for otherdi%ita# I@Js. Its fre4uenc$ is same at which processoroperates.

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• INTE==>3T 1i%na#s

T=3 & =1T 5.5& =1T ".5& =1T B.5

INT= < IN3>T It is an interrupt re4uest si%na#. mon% a## the

interrupts this has the #east priorit$& when it %oes hi%h the pro%ram

counter does not increment its contents.The microprocessor suspends

its norma# se4uence of instructions after comp#etin% the instruction in

hand and then it Oumps to the startin% address of the I1= after sa7in%

the contents of re4uired re%isters into stac'.

The INT= #ine is samp#ed in the #ast state of the #ast machine c$c#e of

the instruction bein% e9ecuted.

The microprocessor ac'now#ed%es the interrupt si%na# and issues an

INTJ si%na#.The INT= is enab#ed or disab#ed b$ software.

n interrupt is used b$ I? de7ices to transfer data to the

microprocessor with out wastin% its time.

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• INTJ < utput

It is an Interrupt c'now#ed%ement sent b$ themicroprocessor after INT= is recei7ed.

• L2< Input

It indicates that another de7ice is re4uestin% for the use of

address and data bus.a7in% recei7ed a L2 re4uest themicroprocessor re#in4uishes the use of the buses as soon as

the current machine c$c#e is comp#eted.

Interna# processin% ma$ continue& the processor re%ains the

buses after the remo7a# of L2 si%na#.Ghen a L2 is ac'now#ed%ed&address bus& data bus&

=2J& G=J and I?/J are Tri-stated.

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• L2 < utput

It is a si%na# for L2 ac'now#ed%ement. It indicates thatthe L2 re4uest has been recei7ed.

The L2 %oes #ow after the L2 si%na# %oes #ow.

The @3> ta'es o7er the buses after a#f c#oc' c$c#e of

remo7a# of L2 si%na#.• =E2H < Input

It is used b$ the microprocessor to sense whether a periphera# is read$ to transfer data or not.

s#ow periphera# ma$ be connected to the microprocessorthrou%h the =ead$ #ine.

If =E2H is hi%h the periphera# is read$.If it is #ow themicroprocessor waits ti## it %oes hi%h.

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• =E1ET >T < utput

Indicates that @3> is bein% reseted& and is used b$ themicroprocessor to reset the other sub-s$stems in the

microprocessor based s$stem.

• =E1ET INJ < Input

It resets the pro%ram counter to zero. It a#so resets interruptenab#e and L2 f#ip-f#ops. It does not affect an$ other

f#a% or re%ister e9cept the instruction re%ister.

The @3> is he#d in the reset condition as #on% as =E1ET is

app#ied.

3i @ fi ti f 8085

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• 1eria# I? ports

The 8085 microprocessor has two si%na#s for seria#communication i.e.& 1I2 and 12

1I2< 1eria# Input 2ata Input

It is data #ine for seria# input. The data on this #ine is

#oaded into the Bth

bit of the accumu#ator when =I/ instruction is e9ecuted.

12 < 1eria# utput 2ata utput

It is a data #ine for seria# output. The Bth bit of the

accumu#ator is output on 12 #ine when 1I/ instruction is e9ecuted.

8085 unit-1

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